diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-01-18 16:30:06 -0600 |
| commit | 9b67f3723e48efdd0a0b640ff82cfcf8aad3a659 (patch) | |
| tree | 79c5001cce6b9d92d1ad04d4a2cd4e442f56803c /tests/quick/10.linux-boot | |
| parent | 77853b9f529947c3a9db78ef3458289f387289ce (diff) | |
| download | gem5-9b67f3723e48efdd0a0b640ff82cfcf8aad3a659.tar.xz | |
Stats: Update stats for previous set of patches.
Diffstat (limited to 'tests/quick/10.linux-boot')
5 files changed, 260 insertions, 254 deletions
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index b338978a2..c7f419728 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -9,7 +9,7 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux.arm +kernel=/dist/m5/system/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -155,7 +155,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/chips/pd/randd/dist/disks/ael-arm.ext2 +file=/dist/m5/system/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 122561307..e76a50eec 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -30,8 +30,14 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis For more information see: http://www.m5sim.org/warn/7998f2ea warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 +warn: Complete acc isn't called on normal stores in O3. +For more information see: http://www.m5sim.org/warn/138d8573 warn: Need to flush all TLBs in MP For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 715d7a4d1..8382cb48d 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Oct 15 2010 11:17:32 -M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip -M5 started Oct 15 2010 11:17:48 -M5 executing on aus-bc3-b4 -command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing +M5 compiled Jan 17 2011 18:36:49 +M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase +M5 started Jan 17 2011 18:36:52 +M5 executing on zizzer +command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 120261685000 because m5_exit instruction encountered +Exiting @ tick 114721074000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index d79fbb100..157177a6b 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,254 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 571745 # Simulator instruction rate (inst/s) -host_mem_usage 384580 # Number of bytes of host memory used -host_seconds 88.62 # Real time elapsed on the host -host_tick_rate 1356995451 # Simulator tick rate (ticks/s) +host_inst_rate 1461109 # Simulator instruction rate (inst/s) +host_mem_usage 340352 # Number of bytes of host memory used +host_seconds 34.61 # Real time elapsed on the host +host_tick_rate 3314430509 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50669854 # Number of instructions simulated -sim_seconds 0.120262 # Number of seconds simulated -sim_ticks 120261685000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100213 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100213 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15144.474290 # average LoadLockedReq miss latency +sim_insts 50572425 # Number of instructions simulated +sim_seconds 0.114721 # Number of seconds simulated +sim_ticks 114721074000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12144.474290 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 95001 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95001 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 78933000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052009 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5212 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5212 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63297000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052009 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7824422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7824422 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15793.989050 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12793.661656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7587704 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7587704 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3738721500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030254 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236718 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3028490000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 236718 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43432839000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100212 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100212 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100212 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100212 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6671650 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6671650 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40817.981450 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37817.693965 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6499467 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499467 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7028162500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025808 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172183 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172183 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6511564000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025808 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172183 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.639363 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14496072 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14496072 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26331.273340 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14087171 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14087171 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10766884000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028208 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408901 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408901 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9540054000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028208 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 408901 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994782 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.328153 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14496072 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14496072 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26331.273340 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23330.962751 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14087171 # number of overall hits +system.cpu.dcache.overall_hits::0 14087950 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14087171 # number of overall hits -system.cpu.dcache.overall_miss_latency 10766884000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028208 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14087950 # number of overall hits +system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408901 # number of overall misses +system.cpu.dcache.overall_misses::0 408690 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408901 # number of overall misses +system.cpu.dcache.overall_misses::total 408690 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9540054000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028208 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 408901 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 44358885500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411855 # number of replacements -system.cpu.dcache.sampled_refs 412367 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411628 # number of replacements +system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.328153 # Cycle average of tags in use -system.cpu.dcache.total_refs 14284130 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use +system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 383037 # number of writebacks -system.cpu.dtb.accesses 15524365 # DTB accesses +system.cpu.dcache.writebacks 382676 # number of writebacks +system.cpu.dtb.accesses 15524935 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2228 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15518843 # DTB hits +system.cpu.dtb.hits 15519414 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5522 # DTB misses +system.cpu.dtb.misses 5521 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8739944 # DTB read accesses -system.cpu.dtb.read_hits 8735402 # DTB read hits -system.cpu.dtb.read_misses 4542 # DTB read misses -system.cpu.dtb.write_accesses 6784421 # DTB write accesses -system.cpu.dtb.write_hits 6783441 # DTB write hits +system.cpu.dtb.read_accesses 8740303 # DTB read accesses +system.cpu.dtb.read_hits 8735762 # DTB read hits +system.cpu.dtb.read_misses 4541 # DTB read misses +system.cpu.dtb.write_accesses 6784632 # DTB write accesses +system.cpu.dtb.write_hits 6783652 # DTB write hits system.cpu.dtb.write_misses 980 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41542689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41542689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14799.146758 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11797.848096 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41109166 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41109166 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6415770500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010436 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433523 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433523 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5114638500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010436 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433523 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.826020 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41542689 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41542689 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14799.146758 # average overall miss latency +system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41109166 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41109166 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6415770500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010436 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433523 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433523 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5114638500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010436 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433523 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.948287 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 485.522726 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41542689 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41542689 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14799.146758 # average overall miss latency +system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11797.848096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41109166 # number of overall hits +system.cpu.icache.overall_hits::0 41110405 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41109166 # number of overall hits -system.cpu.icache.overall_miss_latency 6415770500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010436 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41110405 # number of overall hits +system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433523 # number of overall misses +system.cpu.icache.overall_misses::0 433396 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433523 # number of overall misses +system.cpu.icache.overall_misses::total 433396 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5114638500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010436 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433523 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 433010 # number of replacements -system.cpu.icache.sampled_refs 433522 # Sample count of references to valid blocks. +system.cpu.icache.replacements 432883 # number of replacements +system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 485.522726 # Cycle average of tags in use -system.cpu.icache.total_refs 41109166 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use +system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33595 # number of writebacks +system.cpu.icache.writebacks 33555 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41545508 # DTB accesses +system.cpu.itb.accesses 41546620 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41542689 # DTB hits -system.cpu.itb.inst_accesses 41545508 # ITB inst accesses -system.cpu.itb.inst_hits 41542689 # ITB inst hits +system.cpu.itb.hits 41543801 # DTB hits +system.cpu.itb.inst_accesses 41546620 # ITB inst accesses +system.cpu.itb.inst_hits 41543801 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,9 +272,9 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 240523370 # number of cpu cycles simulated -system.cpu.num_insts 50669854 # Number of instructions executed -system.cpu.num_refs 16289326 # Number of memory references +system.cpu.numCycles 229442148 # number of cpu cycles simulated +system.cpu.num_insts 50572425 # Number of instructions executed +system.cpu.num_refs 16289993 # Number of memory references system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -344,140 +344,140 @@ system.iocache.warmup_cycle 0 # Cy system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 170437 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170437 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62185 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62185 # number of ReadExReq hits +system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.635144 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.635144 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 673342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5664 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 679006 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52102.216096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 26560864.864865 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 26612967.080961 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 654480 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5627 # number of ReadReq hits -system.l2c.ReadReq_hits::total 660107 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 982752000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.028013 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006532 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.034545 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18862 # number of ReadReq misses -system.l2c.ReadReq_misses::1 37 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18899 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 755960000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028067 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.336688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.364755 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18899 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 33155867000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1746 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1746 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 721.804511 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits +system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses +system.l2c.ReadReq_misses::1 35 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1248000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990263 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1729 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1729 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 69160000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990263 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1729 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 416632 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 416632 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 416632 # number of Writeback hits -system.l2c.Writeback_hits::total 416632 # number of Writeback hits +system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 416231 # number of Writeback hits +system.l2c.Writeback_hits::total 416231 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.976763 # Average number of references to valid blocks. +system.l2c.avg_refs 6.975292 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 843779 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5664 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 849443 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52015.167487 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 178698810.810811 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 178750825.978298 # average overall miss latency +system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 716665 # number of demand (read+write) hits -system.l2c.demand_hits::1 5627 # number of demand (read+write) hits -system.l2c.demand_hits::total 722292 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6611856000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.150648 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.006532 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.157181 # miss rate for demand accesses -system.l2c.demand_misses::0 127114 # number of demand (read+write) misses -system.l2c.demand_misses::1 37 # number of demand (read+write) misses -system.l2c.demand_misses::total 127151 # number of demand (read+write) misses +system.l2c.demand_hits::0 716275 # number of demand (read+write) hits +system.l2c.demand_hits::1 5617 # number of demand (read+write) hits +system.l2c.demand_hits::total 721892 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses +system.l2c.demand_misses::0 127149 # number of demand (read+write) misses +system.l2c.demand_misses::1 35 # number of demand (read+write) misses +system.l2c.demand_misses::total 127184 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5086040000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.150692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 22.448976 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.599668 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 127151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.087309 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.478511 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5721.907765 # Average occupied blocks per context -system.l2c.occ_blocks::1 31359.701032 # Average occupied blocks per context -system.l2c.overall_accesses::0 843779 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5664 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 849443 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52015.167487 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 178698810.810811 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 178750825.978298 # average overall miss latency +system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context +system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context +system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 716665 # number of overall hits -system.l2c.overall_hits::1 5627 # number of overall hits -system.l2c.overall_hits::total 722292 # number of overall hits -system.l2c.overall_miss_latency 6611856000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.150648 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.006532 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.157181 # miss rate for overall accesses -system.l2c.overall_misses::0 127114 # number of overall misses -system.l2c.overall_misses::1 37 # number of overall misses -system.l2c.overall_misses::total 127151 # number of overall misses +system.l2c.overall_hits::0 716275 # number of overall hits +system.l2c.overall_hits::1 5617 # number of overall hits +system.l2c.overall_hits::total 721892 # number of overall hits +system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses +system.l2c.overall_misses::0 127149 # number of overall misses +system.l2c.overall_misses::1 35 # number of overall misses +system.l2c.overall_misses::total 127184 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5086040000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.150692 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 22.448976 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.599668 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 127151 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 33895711000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94181 # number of replacements -system.l2c.sampled_refs 125790 # Sample count of references to valid blocks. +system.l2c.replacements 94170 # number of replacements +system.l2c.sampled_refs 125831 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 37081.608797 # Cycle average of tags in use -system.l2c.total_refs 877607 # Total number of references to valid blocks. +system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use +system.l2c.total_refs 877708 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87612 # number of writebacks +system.l2c.writebacks 87626 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status index 8953751c2..624e9a5f7 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status @@ -1 +1 @@ -build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! +build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! |