Update the stats for the fixes to the PCI device class.

12 files changed, 810 insertions, 802 deletions

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index a9bd0ea3f..2e7c9e61b 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:37:23
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+M5 compiled Dec 14 2008 21:47:07
+M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
+M5 commit date Sun Dec 14 21:45:15 2008 -0800
+M5 started Dec 14 2008 21:48:26
+M5 executing on tater
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 1e6af66f7..55ea1f24a 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,44 +1,44 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                3333474                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 290708                       # Number of bytes of host memory used
-host_seconds                                    18.93                       # Real time elapsed on the host
-host_tick_rate                            98784311223                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1560779                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 292076                       # Number of bytes of host memory used
+host_seconds                                    40.46                       # Real time elapsed on the host
+host_tick_rate                            46222973494                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    63113507                       # Number of instructions simulated
+sim_insts                                    63154034                       # Number of instructions simulated
 sim_seconds                                  1.870336                       # Number of seconds simulated
 sim_ticks                                1870335522500                       # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses       188283                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_hits          172122                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_rate     0.085834                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses         16161                       # number of LoadLockedReq misses
-system.cpu0.dcache.ReadReq_accesses           8975619                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits               7292050                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate         0.187571                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses             1683569                       # number of ReadReq misses
-system.cpu0.dcache.StoreCondReq_accesses       187323                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_hits           159821                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_rate     0.146816                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses          27502                       # number of StoreCondReq misses
-system.cpu0.dcache.WriteReq_accesses          5746054                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits              5372248                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate        0.065054                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses             373806                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_accesses       188297                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_hits          172138                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_rate     0.085817                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses         16159                       # number of LoadLockedReq misses
+system.cpu0.dcache.ReadReq_accesses           8981669                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_hits               7298106                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_rate         0.187444                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses             1683563                       # number of ReadReq misses
+system.cpu0.dcache.StoreCondReq_accesses       187338                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_hits           159838                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_rate     0.146793                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses          27500                       # number of StoreCondReq misses
+system.cpu0.dcache.WriteReq_accesses          5748261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_hits              5374453                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate        0.065030                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses             373808                       # number of WriteReq misses
 system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  6.625587                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                  6.629793                       # Average number of references to valid blocks.
 system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses           14721673                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses           14729930                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits               12664298                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits               12672559                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate          0.139751                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses              2057375                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_miss_rate          0.139673                       # miss rate for demand accesses
+system.cpu0.dcache.demand_misses              2057371                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
@@ -46,14 +46,14 @@ system.cpu0.dcache.demand_mshr_misses               0                       # nu
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses          14721673                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses          14729930                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits              12664298                       # number of overall hits
+system.cpu0.dcache.overall_hits              12672559                       # number of overall hits
 system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate         0.139751                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses             2057375                       # number of overall misses
+system.cpu0.dcache.overall_miss_rate         0.139673                       # miss rate for overall accesses
+system.cpu0.dcache.overall_misses             2057371                       # number of overall misses
 system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu0.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
@@ -69,44 +69,44 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued            0
 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements               1978967                       # number of replacements
-system.cpu0.dcache.sampled_refs               1979479                       # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements               1978962                       # number of replacements
+system.cpu0.dcache.sampled_refs               1979474                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               504.827685                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                13115211                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               504.827058                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                13123502                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.writebacks                  396793                       # number of writebacks
 system.cpu0.dtb.accesses                       698037                       # DTB accesses
 system.cpu0.dtb.acv                               251                       # DTB access violations
-system.cpu0.dtb.hits                         15082911                       # DTB hits
+system.cpu0.dtb.hits                         15091429                       # DTB hits
 system.cpu0.dtb.misses                           7805                       # DTB misses
 system.cpu0.dtb.read_accesses                  508987                       # DTB read accesses
 system.cpu0.dtb.read_acv                          152                       # DTB read access violations
-system.cpu0.dtb.read_hits                     9148351                       # DTB read hits
+system.cpu0.dtb.read_hits                     9154530                       # DTB read hits
 system.cpu0.dtb.read_misses                      7079                       # DTB read misses
 system.cpu0.dtb.write_accesses                 189050                       # DTB write accesses
 system.cpu0.dtb.write_acv                          99                       # DTB write access violations
-system.cpu0.dtb.write_hits                    5934560                       # DTB write hits
+system.cpu0.dtb.write_hits                    5936899                       # DTB write hits
 system.cpu0.dtb.write_misses                      726                       # DTB write misses
-system.cpu0.icache.ReadReq_accesses          57189605                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits              56304737                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate         0.015473                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses              884868                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_accesses          57230132                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_hits              56345132                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_rate         0.015464                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses              885000                       # number of ReadReq misses
 system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                 63.636703                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                 63.672859                       # Average number of references to valid blocks.
 system.cpu0.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses           57189605                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses           57230132                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits               56304737                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits               56345132                       # number of demand (read+write) hits
 system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate          0.015473                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses               884868                       # number of demand (read+write) misses
+system.cpu0.icache.demand_miss_rate          0.015464                       # miss rate for demand accesses
+system.cpu0.icache.demand_misses               885000                       # number of demand (read+write) misses
 system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
 system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
@@ -114,14 +114,14 @@ system.cpu0.icache.demand_mshr_misses               0                       # nu
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses          57189605                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses          57230132                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits              56304737                       # number of overall hits
+system.cpu0.icache.overall_hits              56345132                       # number of overall hits
 system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate         0.015473                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses              884868                       # number of overall misses
+system.cpu0.icache.overall_miss_rate         0.015464                       # miss rate for overall accesses
+system.cpu0.icache.overall_misses              885000                       # number of overall misses
 system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
 system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu0.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
@@ -137,28 +137,28 @@ system.cpu0.icache.prefetcher.num_hwpf_issued            0
 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements                884272                       # number of replacements
-system.cpu0.icache.sampled_refs                884784                       # Sample count of references to valid blocks.
+system.cpu0.icache.replacements                884404                       # number of replacements
+system.cpu0.icache.sampled_refs                884916                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu0.icache.tagsinuse               511.244754                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                56304737                       # Total number of references to valid blocks.
+system.cpu0.icache.total_refs                56345132                       # Total number of references to valid blocks.
 system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.idle_fraction                    0.984710                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      3858857                       # ITB accesses
+system.cpu0.idle_fraction                    0.984700                       # Percentage of idle cycles
+system.cpu0.itb.accesses                      3859041                       # ITB accesses
 system.cpu0.itb.acv                               127                       # ITB acv
-system.cpu0.itb.hits                          3855372                       # ITB hits
+system.cpu0.itb.hits                          3855556                       # ITB hits
 system.cpu0.itb.misses                           3485                       # ITB misses
-system.cpu0.kern.callpal                       183274                       # number of callpals executed
+system.cpu0.kern.callpal                       183291                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal_wripir                   110      0.06%      0.06% # number of callpals executed
 system.cpu0.kern.callpal_wrmces                     1      0.00%      0.06% # number of callpals executed
 system.cpu0.kern.callpal_wrfen                      1      0.00%      0.06% # number of callpals executed
 system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.06% # number of callpals executed
-system.cpu0.kern.callpal_swpctx                  3761      2.05%      2.11% # number of callpals executed
+system.cpu0.kern.callpal_swpctx                  3762      2.05%      2.11% # number of callpals executed
 system.cpu0.kern.callpal_tbi                       38      0.02%      2.14% # number of callpals executed
 system.cpu0.kern.callpal_wrent                      7      0.00%      2.14% # number of callpals executed
-system.cpu0.kern.callpal_swpipl                168019     91.68%     93.82% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                168035     91.68%     93.82% # number of callpals executed
 system.cpu0.kern.callpal_rdps                    6150      3.36%     97.17% # number of callpals executed
 system.cpu0.kern.callpal_wrkgp                      1      0.00%     97.17% # number of callpals executed
 system.cpu0.kern.callpal_wrusp                      3      0.00%     97.17% # number of callpals executed
@@ -168,45 +168,45 @@ system.cpu0.kern.callpal_rti                     4673      2.55%     99.73% # nu
 system.cpu0.kern.callpal_callsys                  357      0.19%     99.92% # number of callpals executed
 system.cpu0.kern.callpal_imb                      142      0.08%    100.00% # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    197103                       # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce                    6167                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count                     174852                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0                    70996     40.60%     40.60% # number of times we switched to this ipl
+system.cpu0.kern.inst.hwrei                    197120                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6283                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count                     174868                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    71004     40.60%     40.60% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count_21                     243      0.14%     40.74% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count_22                    1908      1.09%     41.83% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count_30                       8      0.00%     41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31                  101697     58.16%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good                      141409                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0                     69629     49.24%     49.24% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count_31                  101705     58.16%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                      141425                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     69637     49.24%     49.24% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_21                      243      0.17%     49.41% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_22                     1908      1.35%     50.76% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_30                        8      0.01%     50.77% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31                    69621     49.23%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31                    69629     49.23%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_ticks               1870335315000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0             1853125830000     99.08%     99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21                20110000      0.00%     99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22                82044000      0.00%     99.09% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30                  949500      0.00%     99.09% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31             17106381500      0.91%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0                  0.980745                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_ticks_0             1852989766500     99.07%     99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21                20110000      0.00%     99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22                82044000      0.00%     99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30                  949500      0.00%     99.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31             17242445000      0.92%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0                  0.980748                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31                 0.684592                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used_31                 0.684617                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.mode_good_kernel                1157                      
 system.cpu0.kern.mode_good_user                  1158                      
 system.cpu0.kern.mode_good_idle                     0                      
-system.cpu0.kern.mode_switch_kernel              7090                       # number of protection mode switches
+system.cpu0.kern.mode_switch_kernel              7091                       # number of protection mode switches
 system.cpu0.kern.mode_switch_user                1158                       # number of protection mode switches
 system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
 system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel     0.163188                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.163165                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_ticks_kernel       1869378305000     99.95%     99.95% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks_user            957009000      0.05%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3762                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3763                       # number of times the context was actually changed
 system.cpu0.kern.syscall                          226                       # number of syscalls executed
 system.cpu0.kern.syscall_2                          6      2.65%      2.65% # number of syscalls executed
 system.cpu0.kern.syscall_3                         19      8.41%     11.06% # number of syscalls executed
@@ -238,10 +238,10 @@ system.cpu0.kern.syscall_98                         2      0.88%     97.35% # nu
 system.cpu0.kern.syscall_132                        2      0.88%     98.23% # number of syscalls executed
 system.cpu0.kern.syscall_144                        2      0.88%     99.12% # number of syscalls executed
 system.cpu0.kern.syscall_147                        2      0.88%    100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction                0.015290                       # Percentage of non-idle cycles
+system.cpu0.not_idle_fraction                0.015300                       # Percentage of non-idle cycles
 system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
-system.cpu0.num_insts                        57181549                       # Number of instructions executed
-system.cpu0.num_refs                         15322361                       # Number of memory references
+system.cpu0.num_insts                        57222076                       # Number of instructions executed
+system.cpu0.num_refs                         15330887                       # Number of memory references
 system.cpu1.dcache.LoadLockedReq_accesses        16418                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_hits           15129                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_miss_rate     0.078511                       # miss rate for LoadLockedReq accesses
@@ -306,7 +306,7 @@ system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu1.dcache.replacements                 62338                       # number of replacements
 system.cpu1.dcache.sampled_refs                 62657                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               391.950049                       # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse               391.951263                       # Cycle average of tags in use
 system.cpu1.dcache.total_refs                 1834544                       # Total number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.writebacks                   30848                       # number of writebacks
@@ -529,33 +529,33 @@ system.iocache.tagsinuse                     0.435437                       # Cy
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses                  306244                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses                  306247                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    306244                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses                   2724143                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits                       1759609                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate                 0.354069                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                      964534                       # number of ReadReq misses
-system.l2c.UpgradeReq_accesses                 125010                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_misses                    306247                       # number of ReadExReq misses
+system.l2c.ReadReq_accesses                   2724267                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits                       1759731                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate                 0.354053                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                      964536                       # number of ReadReq misses
+system.l2c.UpgradeReq_accesses                 125007                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   125010                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses                   125007                       # number of UpgradeReq misses
 system.l2c.Writeback_accesses                  427641                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_hits                      427641                       # number of Writeback hits
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.789118                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          1.788900                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    3030387                       # number of demand (read+write) accesses
+system.l2c.demand_accesses                    3030514                       # number of demand (read+write) accesses
 system.l2c.demand_avg_miss_latency                  0                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency  <err: div-0>                       # average overall mshr miss latency
-system.l2c.demand_hits                        1759609                       # number of demand (read+write) hits
+system.l2c.demand_hits                        1759731                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.419345                       # miss rate for demand accesses
-system.l2c.demand_misses                      1270778                       # number of demand (read+write) misses
+system.l2c.demand_miss_rate                  0.419329                       # miss rate for demand accesses
+system.l2c.demand_misses                      1270783                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_rate                    0                       # mshr miss rate for demand accesses
@@ -563,14 +563,14 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   3030387                       # number of overall (read+write) accesses
+system.l2c.overall_accesses                   3030514                       # number of overall (read+write) accesses
 system.l2c.overall_avg_miss_latency                 0                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1759609                       # number of overall hits
+system.l2c.overall_hits                       1759731                       # number of overall hits
 system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.419345                       # miss rate for overall accesses
-system.l2c.overall_misses                     1270778                       # number of overall misses
+system.l2c.overall_miss_rate                 0.419329                       # miss rate for overall accesses
+system.l2c.overall_misses                     1270783                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate                   0                       # mshr miss rate for overall accesses
@@ -586,13 +586,13 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                       1056800                       # number of replacements
-system.l2c.sampled_refs                       1091449                       # Sample count of references to valid blocks.
+system.l2c.replacements                       1056803                       # number of replacements
+system.l2c.sampled_refs                       1091452                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     30522.432687                       # Cycle average of tags in use
-system.l2c.total_refs                         1952731                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     30526.475636                       # Cycle average of tags in use
+system.l2c.total_refs                         1952499                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                     990121000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          123878                       # number of writebacks
+system.l2c.writebacks                          123882                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
index c2aeea3f1..6129834bd 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
@@ -60,6 +60,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
PCI: Setting latency timer of device 0000:00:01.0 to 64
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
@@ -71,6 +72,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
 
PIIX4: chipset revision 0
 
PIIX4: 100% native mode on irq 31
+
PCI: Setting latency timer of device 0000:00:00.0 to 64
 
    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
 
    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
 
hda: M5 IDE Disk, ATA DISK drive
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 6989105c7..2ea90534e 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:37:01
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+M5 compiled Dec 14 2008 21:47:07
+M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
+M5 commit date Sun Dec 14 21:45:15 2008 -0800
+M5 started Dec 14 2008 21:47:54
+M5 executing on tater
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1828355695500 because m5_exit instruction encountered
+Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 8c53afda6..19b0c43d9 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,44 +1,44 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                2786128                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 289464                       # Number of bytes of host memory used
-host_seconds                                    21.53                       # Real time elapsed on the host
-host_tick_rate                            84905818409                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1610025                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 290828                       # Number of bytes of host memory used
+host_seconds                                    37.29                       # Real time elapsed on the host
+host_tick_rate                            49056237387                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    59995351                       # Number of instructions simulated
-sim_seconds                                  1.828356                       # Number of seconds simulated
-sim_ticks                                1828355695500                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses       200279                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits           183118                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate     0.085685                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses          17161                       # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses            9523053                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits                7801372                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate          0.180791                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1721681                       # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses        199258                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits            169391                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate     0.149891                       # miss rate for StoreCondReq accesses
+sim_insts                                    60038305                       # Number of instructions simulated
+sim_seconds                                  1.829332                       # Number of seconds simulated
+sim_ticks                                1829332258000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses       200303                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits           183141                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate     0.085680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses          17162                       # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses            9529487                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits                7807782                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate          0.180671                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1721705                       # number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses        199282                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits            169415                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_rate     0.149873                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_misses           29867                       # number of StoreCondReq misses
-system.cpu.dcache.WriteReq_accesses           6150189                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits               5750766                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate         0.064945                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              399423                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_accesses           6152574                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits               5753150                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate         0.064920                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              399424                       # number of WriteReq misses
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   6.866519                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.870767                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            15673242                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses            15682061                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_avg_miss_latency            0                       # average overall miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                13552138                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits                13560932                       # number of demand (read+write) hits
 system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.135333                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2121104                       # number of demand (read+write) misses
+system.cpu.dcache.demand_miss_rate           0.135258                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2121129                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_rate             0                       # mshr miss rate for demand accesses
@@ -46,14 +46,14 @@ system.cpu.dcache.demand_mshr_misses                0                       # nu
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           15673242                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses           15682061                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               13552138                       # number of overall hits
+system.cpu.dcache.overall_hits               13560932                       # number of overall hits
 system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.135333                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2121104                       # number of overall misses
+system.cpu.dcache.overall_miss_rate          0.135258                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2121129                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
@@ -69,44 +69,44 @@ system.cpu.dcache.prefetcher.num_hwpf_issued            0
 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                2042676                       # number of replacements
-system.cpu.dcache.sampled_refs                2043188                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                2042700                       # number of replacements
+system.cpu.dcache.sampled_refs                2043212                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.997800                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14029590                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14038433                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   428892                       # number of writebacks
+system.cpu.dcache.writebacks                   428893                       # number of writebacks
 system.cpu.dtb.accesses                       1020787                       # DTB accesses
 system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          16053817                       # DTB hits
+system.cpu.dtb.hits                          16062925                       # DTB hits
 system.cpu.dtb.misses                           11471                       # DTB misses
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                      9703849                       # DTB read hits
+system.cpu.dtb.read_hits                      9710427                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6349968                       # DTB write hits
+system.cpu.dtb.write_hits                     6352498                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.icache.ReadReq_accesses           60007189                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits               59087131                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate          0.015332                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses               920058                       # number of ReadReq misses
+system.cpu.icache.ReadReq_accesses           60050143                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_hits               59129922                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_rate          0.015324                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses               920221                       # number of ReadReq misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  64.229122                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  64.264250                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            60007189                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses            60050143                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency            0                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                59087131                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits                59129922                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.015332                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                920058                       # number of demand (read+write) misses
+system.cpu.icache.demand_miss_rate           0.015324                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                920221                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_rate             0                       # mshr miss rate for demand accesses
@@ -114,14 +114,14 @@ system.cpu.icache.demand_mshr_misses                0                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           60007189                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses           60050143                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency            0                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               59087131                       # number of overall hits
+system.cpu.icache.overall_hits               59129922                       # number of overall hits
 system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.015332                       # miss rate for overall accesses
-system.cpu.icache.overall_misses               920058                       # number of overall misses
+system.cpu.icache.overall_miss_rate          0.015324                       # miss rate for overall accesses
+system.cpu.icache.overall_misses               920221                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
@@ -137,19 +137,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued            0
 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                 919431                       # number of replacements
-system.cpu.icache.sampled_refs                 919943                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 919594                       # number of replacements
+system.cpu.icache.sampled_refs                 920106                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                511.214823                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59087131                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                511.215243                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 59129922                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                     0.983588                       # Percentage of idle cycles
-system.cpu.itb.accesses                       4979228                       # ITB accesses
+system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
+system.cpu.itb.accesses                       4979654                       # ITB accesses
 system.cpu.itb.acv                                184                       # ITB acv
-system.cpu.itb.hits                           4974222                       # ITB hits
+system.cpu.itb.hits                           4974648                       # ITB hits
 system.cpu.itb.misses                            5006                       # ITB misses
-system.cpu.kern.callpal                        192140                       # number of callpals executed
+system.cpu.kern.callpal                        192180                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
@@ -157,50 +157,50 @@ system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # nu
 system.cpu.kern.callpal_swpctx                   4177      2.17%      2.18% # number of callpals executed
 system.cpu.kern.callpal_tbi                        54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal_wrent                       7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal_swpipl                 175211     91.19%     93.40% # number of callpals executed
-system.cpu.kern.callpal_rdps                     6770      3.52%     96.92% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 175249     91.19%     93.40% # number of callpals executed
+system.cpu.kern.callpal_rdps                     6771      3.52%     96.92% # number of callpals executed
 system.cpu.kern.callpal_wrkgp                       1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal_wrusp                       7      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal_rdusp                       9      0.00%     96.93% # number of callpals executed
 system.cpu.kern.callpal_whami                       2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal_rti                      5202      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal_rti                      5203      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal_callsys                   515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211278                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6240                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count                      182522                       # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0                     74815     40.99%     40.99% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      182562                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     74830     40.99%     40.99% # number of times we switched to this ipl
 system.cpu.kern.ipl_count_21                      243      0.13%     41.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22                     1865      1.02%     42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31                   105599     57.86%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good                       149004                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0                      73448     49.29%     49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count_22                     1866      1.02%     42.14% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31                   105623     57.86%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       149035                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_21                       243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22                      1865      1.25%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31                     73448     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                1828355488000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0              1811087822500     99.06%     99.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21                 20110000      0.00%     99.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22                 80195000      0.00%     99.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31              17167360500      0.94%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0                   0.981728                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good_22                      1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31                     73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                1829332050500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0              1811927407500     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21                 20110000      0.00%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22                 80238000      0.00%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31              17304295000      0.95%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0                   0.981732                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31                  0.695537                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used_31                  0.695521                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.mode_good_kernel                 1909                      
 system.cpu.kern.mode_good_user                   1738                      
 system.cpu.kern.mode_good_idle                    171                      
-system.cpu.kern.mode_switch_kernel               5948                       # number of protection mode switches
+system.cpu.kern.mode_switch_kernel               5949                       # number of protection mode switches
 system.cpu.kern.mode_switch_user                 1738                       # number of protection mode switches
 system.cpu.kern.mode_switch_idle                 2097                       # number of protection mode switches
-system.cpu.kern.mode_switch_good             1.402493                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel      0.320948                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good             1.402439                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.320894                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_idle        0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel         26834029500      1.47%      1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_kernel         26834202500      1.47%      1.47% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks_user            1465074000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle          1800056383500     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle          1801032773000     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.cpu.kern.syscall                           326                       # number of syscalls executed
 system.cpu.kern.syscall_2                           8      2.45%      2.45% # number of syscalls executed
@@ -233,10 +233,10 @@ system.cpu.kern.syscall_98                          2      0.61%     97.55% # nu
 system.cpu.kern.syscall_132                         4      1.23%     98.77% # number of syscalls executed
 system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
-system.cpu.not_idle_fraction                 0.016412                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3656711283                       # number of cpu cycles simulated
-system.cpu.num_insts                         59995351                       # Number of instructions executed
-system.cpu.num_refs                          16302128                       # Number of memory references
+system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
+system.cpu.numCycles                       3658664408                       # number of cpu cycles simulated
+system.cpu.num_insts                         60038305                       # Number of instructions executed
+system.cpu.num_refs                          16311238                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -303,37 +303,37 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss            0
 system.iocache.replacements                     41686                       # number of replacements
 system.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.226225                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.225570                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1684804097017                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses                  304347                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses                  304346                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    304347                       # number of ReadExReq misses
-system.l2c.ReadReq_accesses                   2658883                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits                       1696464                       # number of ReadReq hits
-system.l2c.ReadReq_miss_rate                 0.361964                       # miss rate for ReadReq accesses
+system.l2c.ReadExReq_misses                    304346                       # number of ReadExReq misses
+system.l2c.ReadReq_accesses                   2659071                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_hits                       1696652                       # number of ReadReq hits
+system.l2c.ReadReq_miss_rate                 0.361938                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_misses                      962419                       # number of ReadReq misses
-system.l2c.UpgradeReq_accesses                 124943                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses                 124945                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   124943                       # number of UpgradeReq misses
-system.l2c.Writeback_accesses                  428892                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits                      428892                       # number of Writeback hits
+system.l2c.UpgradeReq_misses                   124945                       # number of UpgradeReq misses
+system.l2c.Writeback_accesses                  428893                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits                      428893                       # number of Writeback hits
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.726803                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          1.727246                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2963230                       # number of demand (read+write) accesses
+system.l2c.demand_accesses                    2963417                       # number of demand (read+write) accesses
 system.l2c.demand_avg_miss_latency                  0                       # average overall miss latency
 system.l2c.demand_avg_mshr_miss_latency  <err: div-0>                       # average overall mshr miss latency
-system.l2c.demand_hits                        1696464                       # number of demand (read+write) hits
+system.l2c.demand_hits                        1696652                       # number of demand (read+write) hits
 system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.427495                       # miss rate for demand accesses
-system.l2c.demand_misses                      1266766                       # number of demand (read+write) misses
+system.l2c.demand_miss_rate                  0.427468                       # miss rate for demand accesses
+system.l2c.demand_misses                      1266765                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_rate                    0                       # mshr miss rate for demand accesses
@@ -341,14 +341,14 @@ system.l2c.demand_mshr_misses                       0                       # nu
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   2963230                       # number of overall (read+write) accesses
+system.l2c.overall_accesses                   2963417                       # number of overall (read+write) accesses
 system.l2c.overall_avg_miss_latency                 0                       # average overall miss latency
 system.l2c.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1696464                       # number of overall hits
+system.l2c.overall_hits                       1696652                       # number of overall hits
 system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.427495                       # miss rate for overall accesses
-system.l2c.overall_misses                     1266766                       # number of overall misses
+system.l2c.overall_miss_rate                 0.427468                       # miss rate for overall accesses
+system.l2c.overall_misses                     1266765                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
 system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_rate                   0                       # mshr miss rate for overall accesses
@@ -364,13 +364,13 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                       1050731                       # number of replacements
-system.l2c.sampled_refs                       1081071                       # Sample count of references to valid blocks.
+system.l2c.replacements                       1050724                       # number of replacements
+system.l2c.sampled_refs                       1081067                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     30223.992851                       # Cycle average of tags in use
-system.l2c.total_refs                         1866797                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     30228.585605                       # Cycle average of tags in use
+system.l2c.total_refs                         1867269                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                     765422500                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          119150                       # number of writebacks
+system.l2c.writebacks                          119147                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
index 7930e9e46..f17158b67 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
@@ -55,6 +55,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
PCI: Setting latency timer of device 0000:00:01.0 to 64
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
@@ -66,6 +67,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
 
PIIX4: chipset revision 0
 
PIIX4: 100% native mode on irq 31
+
PCI: Setting latency timer of device 0000:00:00.0 to 64
 
    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
 
    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
 
hda: M5 IDE Disk, ATA DISK drive
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 06723d964..9f8bf8070 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:38:12
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+M5 compiled Dec 14 2008 21:47:07
+M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
+M5 commit date Sun Dec 14 21:45:15 2008 -0800
+M5 started Dec 14 2008 21:47:52
+M5 executing on tater
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1972135479000 because m5_exit instruction encountered
+Exiting @ tick 1972135461000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 39aa94315..2f2449fdc 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,92 +1,92 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1388930                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 287800                       # Number of bytes of host memory used
-host_seconds                                    42.75                       # Real time elapsed on the host
-host_tick_rate                            46129218174                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 741695                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 289172                       # Number of bytes of host memory used
+host_seconds                                    80.11                       # Real time elapsed on the host
+host_tick_rate                            24616375840                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    59379829                       # Number of instructions simulated
+sim_insts                                    59420593                       # Number of instructions simulated
 sim_seconds                                  1.972135                       # Number of seconds simulated
-sim_ticks                                1972135479000                       # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses       192618                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14266.203842                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11266.203842                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits          175909                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency    238374000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate     0.086747                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses         16709                       # number of LoadLockedReq misses
+sim_ticks                                1972135461000                       # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses       192630                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14259.465279                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits          175911                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency    238404000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate     0.086793                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses         16719                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    188247000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.086747                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        16709                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses           8482392                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 25694.187455                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.147984                       # average ReadReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.086793                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses        16719                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses           8488393                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 25694.266311                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits               7443656                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency   26689477500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate         0.122458                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses             1038736                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency  23573228500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate     0.122458                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses        1038736                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    868701000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses       191654                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 55352.322833                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52352.322833                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits           163305                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency   1569183000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate     0.147918                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses          28349                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency   1484136000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.147918                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses        28349                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses          5845269                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 55891.595936                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.595936                       # average WriteReq mshr miss latency
+system.cpu0.dcache.ReadReq_hits               7449690                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency   26688711500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate         0.122367                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses             1038703                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency  23572561500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate     0.122367                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses        1038703                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    883604000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses       191666                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 55344.484086                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits           163357                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency   1566747000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate     0.147700                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses          28309                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency   1481820000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.147700                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses        28309                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses          5847430                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 55891.373878                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits              5466012                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency  21197279000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate        0.064883                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses             379257                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency  20059508000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate     0.064883                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses        379257                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1225890000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_hits              5468175                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency  21197083000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate        0.064858                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses             379255                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency  20059318000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate     0.064858                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses        379255                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1240870000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  9.984583                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                  9.990826                       # Average number of references to valid blocks.
 system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses           14327661                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 33770.798939                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.770025                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits               12909668                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency    47886756500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate          0.098969                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses              1417993                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_accesses           14335823                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 33770.954076                       # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits               12917865                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency    47885794500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate          0.098910                       # miss rate for demand accesses
+system.cpu0.dcache.demand_misses              1417958                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency  43632736500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate     0.098969                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses         1417993                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_miss_latency  43631879500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate     0.098910                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses         1417958                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses          14327661                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 33770.798939                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.770025                       # average overall mshr miss latency
+system.cpu0.dcache.overall_accesses          14335823                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 33770.954076                       # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits              12909668                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency   47886756500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate         0.098969                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses             1417993                       # number of overall misses
+system.cpu0.dcache.overall_hits              12917865                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency   47885794500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate         0.098910                       # miss rate for overall accesses
+system.cpu0.dcache.overall_misses             1417958                       # number of overall misses
 system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency  43632736500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate     0.098969                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses        1417993                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2094591000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_miss_latency  43631879500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate     0.098910                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses        1417958                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2124474000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued            0
 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements               1338626                       # number of replacements
-system.cpu0.dcache.sampled_refs               1339138                       # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements               1338610                       # number of replacements
+system.cpu0.dcache.sampled_refs               1339122                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               503.746259                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                13370734                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               503.609177                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                13378935                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              84055000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  403562                       # number of writebacks
+system.cpu0.dcache.writebacks                  403520                       # number of writebacks
 system.cpu0.dtb.accesses                       719860                       # DTB accesses
 system.cpu0.dtb.acv                               289                       # DTB access violations
-system.cpu0.dtb.hits                         14696400                       # DTB hits
+system.cpu0.dtb.hits                         14704826                       # DTB hits
 system.cpu0.dtb.misses                           8485                       # DTB misses
 system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
 system.cpu0.dtb.read_acv                          174                       # DTB read access violations
-system.cpu0.dtb.read_hits                     8658591                       # DTB read hits
+system.cpu0.dtb.read_hits                     8664724                       # DTB read hits
 system.cpu0.dtb.read_misses                      7687                       # DTB read misses
 system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
 system.cpu0.dtb.write_acv                         115                       # DTB write access violations
-system.cpu0.dtb.write_hits                    6037809                       # DTB write hits
+system.cpu0.dtb.write_hits                    6040102                       # DTB write hits
 system.cpu0.dtb.write_misses                      798                       # DTB write misses
-system.cpu0.icache.ReadReq_accesses          54124252                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 14681.475669                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.724759                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits              53208030                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency   13451491000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate         0.016928                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses              916222                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency  10702137000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate     0.016928                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses         916222                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_accesses          54164416                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 14681.637172                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits              53248092                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency   13453136500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate         0.016917                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses              916324                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency  10703476000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate     0.016917                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses         916324                       # number of ReadReq MSHR misses
 system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                 58.081472                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                 58.118732                       # Average number of references to valid blocks.
 system.cpu0.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses           54124252                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 14681.475669                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11680.724759                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits               53208030                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency    13451491000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate          0.016928                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses               916222                       # number of demand (read+write) misses
+system.cpu0.icache.demand_accesses           54164416                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 14681.637172                       # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits               53248092                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency    13453136500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate          0.016917                       # miss rate for demand accesses
+system.cpu0.icache.demand_misses               916324                       # number of demand (read+write) misses
 system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency  10702137000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate     0.016928                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses          916222                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_miss_latency  10703476000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate     0.016917                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses          916324                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses          54124252                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 14681.475669                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11680.724759                       # average overall mshr miss latency
+system.cpu0.icache.overall_accesses          54164416                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 14681.637172                       # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits              53208030                       # number of overall hits
-system.cpu0.icache.overall_miss_latency   13451491000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate         0.016928                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses              916222                       # number of overall misses
+system.cpu0.icache.overall_hits              53248092                       # number of overall hits
+system.cpu0.icache.overall_miss_latency   13453136500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate         0.016917                       # miss rate for overall accesses
+system.cpu0.icache.overall_misses              916324                       # number of overall misses
 system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency  10702137000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate     0.016928                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses         916222                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_miss_latency  10703476000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate     0.016917                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses         916324                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -171,19 +171,19 @@ system.cpu0.icache.prefetcher.num_hwpf_issued            0
 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements                915582                       # number of replacements
-system.cpu0.icache.sampled_refs                916093                       # Sample count of references to valid blocks.
+system.cpu0.icache.replacements                915684                       # number of replacements
+system.cpu0.icache.sampled_refs                916195                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse               508.642784                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                53208030                       # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse               508.642782                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                53248092                       # Total number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           39455749000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.idle_fraction                    0.933199                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      3953623                       # ITB accesses
+system.cpu0.idle_fraction                    0.933160                       # Percentage of idle cycles
+system.cpu0.itb.accesses                      3953747                       # ITB accesses
 system.cpu0.itb.acv                               143                       # ITB acv
-system.cpu0.itb.hits                          3949782                       # ITB hits
+system.cpu0.itb.hits                          3949906                       # ITB hits
 system.cpu0.itb.misses                           3841                       # ITB misses
-system.cpu0.kern.callpal                       187998                       # number of callpals executed
+system.cpu0.kern.callpal                       188012                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu0.kern.callpal_wripir                    91      0.05%      0.05% # number of callpals executed
 system.cpu0.kern.callpal_wrmces                     1      0.00%      0.05% # number of callpals executed
@@ -191,8 +191,8 @@ system.cpu0.kern.callpal_wrfen                      1      0.00%      0.05% # nu
 system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.05% # number of callpals executed
 system.cpu0.kern.callpal_swpctx                  3868      2.06%      2.11% # number of callpals executed
 system.cpu0.kern.callpal_tbi                       44      0.02%      2.13% # number of callpals executed
-system.cpu0.kern.callpal_wrent                      7      0.00%      2.14% # number of callpals executed
-system.cpu0.kern.callpal_swpipl                172054     91.52%     93.65% # number of callpals executed
+system.cpu0.kern.callpal_wrent                      7      0.00%      2.13% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                172068     91.52%     93.65% # number of callpals executed
 system.cpu0.kern.callpal_rdps                    6698      3.56%     97.22% # number of callpals executed
 system.cpu0.kern.callpal_wrkgp                      1      0.00%     97.22% # number of callpals executed
 system.cpu0.kern.callpal_wrusp                      4      0.00%     97.22% # number of callpals executed
@@ -202,43 +202,43 @@ system.cpu0.kern.callpal_rti                     4713      2.51%     99.73% # nu
 system.cpu0.kern.callpal_callsys                  356      0.19%     99.92% # number of callpals executed
 system.cpu0.kern.callpal_imb                      149      0.08%    100.00% # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    202882                       # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce                    6254                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count                     178892                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0                    72633     40.60%     40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21                     131      0.07%     40.67% # number of times we switched to this ipl
+system.cpu0.kern.inst.hwrei                    202896                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6369                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count                     178906                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    72641     40.60%     40.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21                     131      0.07%     40.68% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count_22                    1987      1.11%     41.79% # number of times we switched to this ipl
 system.cpu0.kern.ipl_count_30                       6      0.00%     41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31                  104135     58.21%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good                      144646                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0                     71264     49.27%     49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count_31                  104141     58.21%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                      144662                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     71272     49.27%     49.27% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_21                      131      0.09%     49.36% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_22                     1987      1.37%     50.73% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_30                        6      0.00%     50.74% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31                    71258     49.26%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks               1972134721000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0             1908424308500     96.77%     96.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21                96335500      0.00%     96.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22               576469500      0.03%     96.80% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30                 5442500      0.00%     96.80% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31             63032165000      3.20%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0                  0.981152                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good_31                    71266     49.26%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks               1972134703000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0             1908230091000     96.76%     96.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21                96186500      0.00%     96.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22               576952000      0.03%     96.79% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30                 5442500      0.00%     96.79% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31             63226031000      3.21%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0                  0.981154                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31                 0.684285                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel                1232                      
-system.cpu0.kern.mode_good_user                  1233                      
+system.cpu0.kern.ipl_used_31                 0.684322                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel                1231                      
+system.cpu0.kern.mode_good_user                  1232                      
 system.cpu0.kern.mode_good_idle                     0                      
 system.cpu0.kern.mode_switch_kernel              7237                       # number of protection mode switches
-system.cpu0.kern.mode_switch_user                1233                       # number of protection mode switches
+system.cpu0.kern.mode_switch_user                1232                       # number of protection mode switches
 system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
 system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel     0.170236                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.170098                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel       1968330428000     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user           3804291000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_kernel       1968330503000     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user           3804198000      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.swap_context                    3869                       # number of times the context was actually changed
 system.cpu0.kern.syscall                          224                       # number of syscalls executed
@@ -272,89 +272,89 @@ system.cpu0.kern.syscall_98                         2      0.89%     97.77% # nu
 system.cpu0.kern.syscall_132                        2      0.89%     98.66% # number of syscalls executed
 system.cpu0.kern.syscall_144                        1      0.45%     99.11% # number of syscalls executed
 system.cpu0.kern.syscall_147                        2      0.89%    100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction                0.066801                       # Percentage of non-idle cycles
-system.cpu0.numCycles                      3944270958                       # number of cpu cycles simulated
-system.cpu0.num_insts                        54115477                       # Number of instructions executed
-system.cpu0.num_refs                         14937789                       # Number of memory references
+system.cpu0.not_idle_fraction                0.066840                       # Percentage of non-idle cycles
+system.cpu0.numCycles                      3944270922                       # number of cpu cycles simulated
+system.cpu0.num_insts                        54155641                       # Number of instructions executed
+system.cpu0.num_refs                         14946215                       # Number of memory references
 system.cpu1.dcache.LoadLockedReq_accesses        12334                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13393.700787                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10393.700787                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits           11318                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency     13608000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate     0.082374                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses          1016                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     10560000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.082374                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         1016                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses           1020508                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 15788.930188                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12788.832374                       # average ReadReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13303.501946                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits           11306                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency     13676000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate     0.083347                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses          1028                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     10592000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.083347                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_misses         1028                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses           1020543                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 15771.782317                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits                984726                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency     564959500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate         0.035063                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses               35782                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency    457610000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate     0.035063                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses          35782                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_hits                984803                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency     563683500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate         0.035021                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses               35740                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency    456460000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate     0.035021                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses          35740                       # number of ReadReq MSHR misses
 system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     12526000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses        12269                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency 46915.603129                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43915.603129                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits             9840                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency    113958000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate     0.197979                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses           2429                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency    106671000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.197979                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses         2429                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses           649988                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 54642.103265                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51642.103265                       # average WriteReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_accesses        12270                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency 46841.453344                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits             9848                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency    113450000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate     0.197392                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses           2422                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency    106184000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.197392                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_misses         2422                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses           650008                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 54644.846691                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits               623648                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency   1439273000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate        0.040524                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses              26340                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency   1360253000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate     0.040524                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses         26340                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    303022000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_hits               623656                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency   1440001000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate        0.040541                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses              26352                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency   1360945000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate     0.040541                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses         26352                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    303019000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 30.126995                       # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs                 30.141759                       # Average number of references to valid blocks.
 system.cpu1.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses            1670496                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 32262.845691                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 29262.789350                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits                1608374                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency     2004232500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate          0.037188                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses                62122                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_accesses            1670551                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 32269.608001                       # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits                1608459                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency     2003684500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate          0.037169                       # miss rate for demand accesses
+system.cpu1.dcache.demand_misses                62092                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency   1817863000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate     0.037188                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses           62122                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_miss_latency   1817405000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate     0.037169                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses           62092                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses           1670496                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 32262.845691                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 29262.789350                       # average overall mshr miss latency
+system.cpu1.dcache.overall_accesses           1670551                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 32269.608001                       # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits               1608374                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency    2004232500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate         0.037188                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses               62122                       # number of overall misses
+system.cpu1.dcache.overall_hits               1608459                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency    2003684500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate         0.037169                       # miss rate for overall accesses
+system.cpu1.dcache.overall_misses               62092                       # number of overall misses
 system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency   1817863000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate     0.037188                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses          62122                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency    315548000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_miss_latency   1817405000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate     0.037169                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses          62092                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency    315545000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -365,69 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued            0
 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements                 53749                       # number of replacements
-system.cpu1.dcache.sampled_refs                 54144                       # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements                 53724                       # number of replacements
+system.cpu1.dcache.sampled_refs                 54120                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               388.873056                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 1631196                       # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1954644714000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   26833                       # number of writebacks
+system.cpu1.dcache.tagsinuse               388.878897                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 1631272                       # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1954643578000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks                   26831                       # number of writebacks
 system.cpu1.dtb.accesses                       302878                       # DTB accesses
 system.cpu1.dtb.acv                                84                       # DTB access violations
-system.cpu1.dtb.hits                          1693796                       # DTB hits
+system.cpu1.dtb.hits                          1693851                       # DTB hits
 system.cpu1.dtb.misses                           3106                       # DTB misses
 system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
 system.cpu1.dtb.read_acv                           36                       # DTB read access violations
-system.cpu1.dtb.read_hits                     1029675                       # DTB read hits
+system.cpu1.dtb.read_hits                     1029710                       # DTB read hits
 system.cpu1.dtb.read_misses                      2750                       # DTB read misses
 system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
 system.cpu1.dtb.write_acv                          48                       # DTB write access violations
-system.cpu1.dtb.write_hits                     664121                       # DTB write hits
+system.cpu1.dtb.write_hits                     664141                       # DTB write hits
 system.cpu1.dtb.write_misses                      356                       # DTB write misses
-system.cpu1.icache.ReadReq_accesses           5267542                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 14619.415532                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11618.958024                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits               5180112                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency    1278175500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate         0.016598                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses               87430                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency   1015845500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate     0.016598                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses          87430                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_accesses           5268142                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 14617.211446                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits               5180706                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency    1278070500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate         0.016597                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses               87436                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency   1015724000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate     0.016597                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses          87436                       # number of ReadReq MSHR misses
 system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                 59.267660                       # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs                 59.270387                       # Average number of references to valid blocks.
 system.cpu1.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses            5267542                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 14619.415532                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11618.958024                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits                5180112                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency     1278175500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate          0.016598                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses                87430                       # number of demand (read+write) misses
+system.cpu1.icache.demand_accesses            5268142                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 14617.211446                       # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits                5180706                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency     1278070500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate          0.016597                       # miss rate for demand accesses
+system.cpu1.icache.demand_misses                87436                       # number of demand (read+write) misses
 system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency   1015845500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate     0.016598                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses           87430                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_miss_latency   1015724000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate     0.016597                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses           87436                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses           5267542                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 14619.415532                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11618.958024                       # average overall mshr miss latency
+system.cpu1.icache.overall_accesses           5268142                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 14617.211446                       # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits               5180112                       # number of overall hits
-system.cpu1.icache.overall_miss_latency    1278175500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate         0.016598                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses               87430                       # number of overall misses
+system.cpu1.icache.overall_hits               5180706                       # number of overall hits
+system.cpu1.icache.overall_miss_latency    1278070500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate         0.016597                       # miss rate for overall accesses
+system.cpu1.icache.overall_misses               87436                       # number of overall misses
 system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency   1015845500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate     0.016598                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses          87430                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_miss_latency   1015724000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate     0.016597                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses          87436                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -439,19 +439,19 @@ system.cpu1.icache.prefetcher.num_hwpf_issued            0
 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements                 86890                       # number of replacements
-system.cpu1.icache.sampled_refs                 87402                       # Sample count of references to valid blocks.
+system.cpu1.icache.replacements                 86896                       # number of replacements
+system.cpu1.icache.sampled_refs                 87408                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               419.405623                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 5180112                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1967879772000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tagsinuse               419.405627                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 5180706                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1967880295000                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                       0                       # number of writebacks
 system.cpu1.idle_fraction                    0.994655                       # Percentage of idle cycles
-system.cpu1.itb.accesses                      1397499                       # ITB accesses
+system.cpu1.itb.accesses                      1397517                       # ITB accesses
 system.cpu1.itb.acv                                41                       # ITB acv
-system.cpu1.itb.hits                          1396253                       # ITB hits
+system.cpu1.itb.hits                          1396271                       # ITB hits
 system.cpu1.itb.misses                           1246                       # ITB misses
-system.cpu1.kern.callpal                        29501                       # number of callpals executed
+system.cpu1.kern.callpal                        29503                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
 system.cpu1.kern.callpal_wripir                     6      0.02%      0.02% # number of callpals executed
 system.cpu1.kern.callpal_wrmces                     1      0.00%      0.03% # number of callpals executed
@@ -459,7 +459,7 @@ system.cpu1.kern.callpal_wrfen                      1      0.00%      0.03% # nu
 system.cpu1.kern.callpal_swpctx                   365      1.24%      1.27% # number of callpals executed
 system.cpu1.kern.callpal_tbi                       10      0.03%      1.30% # number of callpals executed
 system.cpu1.kern.callpal_wrent                      7      0.02%      1.33% # number of callpals executed
-system.cpu1.kern.callpal_swpipl                 24142     81.83%     83.16% # number of callpals executed
+system.cpu1.kern.callpal_swpipl                 24144     81.84%     83.16% # number of callpals executed
 system.cpu1.kern.callpal_rdps                    2172      7.36%     90.52% # number of callpals executed
 system.cpu1.kern.callpal_wrkgp                      1      0.00%     90.53% # number of callpals executed
 system.cpu1.kern.callpal_wrusp                      3      0.01%     90.54% # number of callpals executed
@@ -470,27 +470,27 @@ system.cpu1.kern.callpal_callsys                  161      0.55%     99.89% # nu
 system.cpu1.kern.callpal_imb                       31      0.11%    100.00% # number of callpals executed
 system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     36051                       # number of hwrei instructions executed
+system.cpu1.kern.inst.hwrei                     36053                       # number of hwrei instructions executed
 system.cpu1.kern.inst.quiesce                    2351                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count                      28808                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0                     9172     31.84%     31.84% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count                      28810                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0                     9173     31.84%     31.84% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count_22                    1980      6.87%     38.71% # number of times we switched to this ipl
 system.cpu1.kern.ipl_count_30                      91      0.32%     39.03% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31                   17565     60.97%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good                       20308                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0                      9164     45.13%     45.13% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_count_31                   17566     60.97%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good                       20310                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0                      9165     45.13%     45.13% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good_22                     1980      9.75%     54.87% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_good_30                       91      0.45%     55.32% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31                     9073     44.68%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31                     9074     44.68%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu1.kern.ipl_ticks               1971683837000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0             1927969399500     97.78%     97.78% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22               511268500      0.03%     97.81% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0             1927968787500     97.78%     97.78% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22               511194500      0.03%     97.81% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_ticks_30                58584000      0.00%     97.81% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31             43144585000      2.19%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31             43145271000      2.19%    100.00% # number of cycles we spent at this ipl
 system.cpu1.kern.ipl_used_0                  0.999128                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31                 0.516539                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used_31                 0.516566                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.mode_good_kernel                 532                      
 system.cpu1.kern.mode_good_user                   516                      
 system.cpu1.kern.mode_good_idle                    16                      
@@ -501,9 +501,9 @@ system.cpu1.kern.mode_switch_good            1.612234                       # fr
 system.cpu1.kern.mode_switch_good_kernel     0.604545                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good_idle       0.007689                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel         4597806000      0.23%      0.23% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user           1703603000      0.09%      0.32% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle         1964669629000     99.68%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_kernel         4596640000      0.23%      0.23% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user           1703543000      0.09%      0.32% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle         1964670722000     99.68%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                     366                       # number of times the context was actually changed
 system.cpu1.kern.syscall                          102                       # number of syscalls executed
 system.cpu1.kern.syscall_2                          2      1.96%      1.96% # number of syscalls executed
@@ -529,8 +529,8 @@ system.cpu1.kern.syscall_132                        2      1.96%     99.02% # nu
 system.cpu1.kern.syscall_144                        1      0.98%    100.00% # number of syscalls executed
 system.cpu1.not_idle_fraction                0.005345                       # Percentage of non-idle cycles
 system.cpu1.numCycles                      3943367734                       # number of cpu cycles simulated
-system.cpu1.num_insts                         5264352                       # Number of instructions executed
-system.cpu1.num_refs                          1703685                       # Number of memory references
+system.cpu1.num_insts                         5264952                       # Number of instructions executed
+system.cpu1.num_refs                          1703740                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -553,46 +553,46 @@ system.iocache.ReadReq_mshr_miss_latency     11248998                       # nu
 system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_misses                178                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137906.834954                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85903.204082                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5730304806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_miss_latency 137902.310503                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5730116806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3569449936                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3569262880                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs  6168.564107                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_mshrs  6169.706090                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.blocked_no_mshrs                 10459                       # number of cycles access was blocked
 system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs       64517012                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs       64528956                       # number of cycles access was blocked
 system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses                  41730                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency   137809.964150                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85806.348766                       # average overall mshr miss latency
+system.iocache.demand_avg_miss_latency   137805.458998                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85801.866235                       # average overall mshr miss latency
 system.iocache.demand_hits                          0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5750809804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5750621804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
 system.iocache.demand_misses                    41730                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3580698934                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3580511878                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_misses               41730                       # number of demand (read+write) MSHR misses
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.iocache.overall_accesses                 41730                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency  137809.964150                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85806.348766                       # average overall mshr miss latency
+system.iocache.overall_avg_miss_latency  137805.458998                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85801.866235                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.iocache.overall_hits                         0                       # number of overall hits
-system.iocache.overall_miss_latency        5750809804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5750621804                       # number of overall miss cycles
 system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
 system.iocache.overall_misses                   41730                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3580698934                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3580511878                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_misses              41730                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -609,80 +609,80 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss            0
 system.iocache.replacements                     41698                       # number of replacements
 system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     0.582076                       # Cycle average of tags in use
+system.iocache.tagsinuse                     0.582075                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1762323729000                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              1762323389000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41520                       # number of writebacks
-system.l2c.ReadExReq_accesses                  306796                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency    52002.653229                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40002.653229                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency         15954206000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_accesses                  306814                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency    52002.656333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency         15955143000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    306796                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency    12272654000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_misses                    306814                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency    12273375000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               306796                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses                   2090247                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency      52016.274350                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.322096                       # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses               306814                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses                   2090305                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency      52016.275832                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits                       1782800                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           15992247500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate                 0.147086                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                      307447                       # number of ReadReq misses
+system.l2c.ReadReq_hits                       1782886                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           15990791500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate                 0.147069                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                      307419                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                       11                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12302458000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate            0.147081                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 307436                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    789200000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses                 127300                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency   50741.146897                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40004.988217                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency         6459348000                       # number of UpgradeReq miss cycles
+system.l2c.ReadReq_mshr_miss_latency      12301338000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate            0.147064                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                 307408                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    802543000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses                 127238                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency   50741.170091                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency         6456205000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   127300                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    5092635000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses                   127238                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency    5090187000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses              127300                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses              127238                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1381237000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses                  430395                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits                      430395                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1394774000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses                  430351                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits                      430351                       # number of Writeback hits
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          4.558799                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          4.554189                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2397043                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency       52009.471007                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40009.494784                       # average overall mshr miss latency
-system.l2c.demand_hits                        1782800                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            31946453500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.256250                       # miss rate for demand accesses
-system.l2c.demand_misses                       614243                       # number of demand (read+write) misses
+system.l2c.demand_accesses                    2397119                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency       52009.472790                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  40009.496566                       # average overall mshr miss latency
+system.l2c.demand_hits                        1782886                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            31945934500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate                  0.256238                       # miss rate for demand accesses
+system.l2c.demand_misses                       614233                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                        11                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       24575112000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate             0.256246                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  614232                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency       24574713000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate             0.256233                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                  614222                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   2397043                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency      52009.471007                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.494784                       # average overall mshr miss latency
+system.l2c.overall_accesses                   2397119                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency      52009.472790                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.496566                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1782800                       # number of overall hits
-system.l2c.overall_miss_latency           31946453500                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.256250                       # miss rate for overall accesses
-system.l2c.overall_misses                      614243                       # number of overall misses
+system.l2c.overall_hits                       1782886                       # number of overall hits
+system.l2c.overall_miss_latency           31945934500                       # number of overall miss cycles
+system.l2c.overall_miss_rate                 0.256238                       # miss rate for overall accesses
+system.l2c.overall_misses                      614233                       # number of overall misses
 system.l2c.overall_mshr_hits                       11                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      24575112000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate            0.256246                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 614232                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   2170437000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency      24574713000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate            0.256233                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                 614222                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   2197317000                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -693,13 +693,13 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                        399043                       # number of replacements
-system.l2c.sampled_refs                        430765                       # Sample count of references to valid blocks.
+system.l2c.replacements                        399005                       # number of replacements
+system.l2c.sampled_refs                        430732                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     30865.823052                       # Cycle average of tags in use
-system.l2c.total_refs                         1963771                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     30859.505450                       # Cycle average of tags in use
+system.l2c.total_refs                         1961635                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                   10912833000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          123178                       # number of writebacks
+system.l2c.writebacks                          123162                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index 6974143c8..7399f4d84 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
@@ -61,6 +61,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
PCI: Setting latency timer of device 0000:00:01.0 to 64
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
@@ -72,6 +73,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
 
PIIX4: chipset revision 0
 
PIIX4: 100% native mode on irq 31
+
PCI: Setting latency timer of device 0000:00:00.0 to 64
 
    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
 
    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
 
hda: M5 IDE Disk, ATA DISK drive
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index b4ba00cf0..b196d52a3 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -5,12 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Dec  4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec  4 2008 21:37:43
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+M5 compiled Dec 14 2008 21:47:07
+M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
+M5 commit date Sun Dec 14 21:45:15 2008 -0800
+M5 started Dec 14 2008 21:47:59
+M5 executing on tater
+command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1930165791000 because m5_exit instruction encountered
+Exiting @ tick 1930164593000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index bcad4cd62..76e60eed0 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,92 +1,92 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1283720                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 286560                       # Number of bytes of host memory used
-host_seconds                                    43.75                       # Real time elapsed on the host
-host_tick_rate                            44115985890                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 715830                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 287924                       # Number of bytes of host memory used
+host_seconds                                    78.52                       # Real time elapsed on the host
+host_tick_rate                            24582295405                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    56165112                       # Number of instructions simulated
-sim_seconds                                  1.930166                       # Number of seconds simulated
-sim_ticks                                1930165791000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses       200388                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.212121                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.212121                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits           183063                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency    248808000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.086457                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses          17325                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    196833000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.086457                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17325                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses            8882666                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 25452.857499                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.814515                       # average ReadReq mshr miss latency
+sim_insts                                    56205703                       # Number of instructions simulated
+sim_seconds                                  1.930165                       # Number of seconds simulated
+sim_ticks                                1930164593000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses       200404                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits           183095                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency    248584000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.086371                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses          17309                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    196657000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.086371                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses        17309                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses            8888653                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits                7812517                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    27238350000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.120476                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1070149                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  24027857000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.120476                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1070149                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    847845000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses        199368                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.365794                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.365794                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits            169362                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency   1680467000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate     0.150506                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses           30006                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency   1590449000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate     0.150506                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses        30006                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           6158164                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56004.032630                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.032630                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_hits                7818479                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    27238448000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.120398                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1070174                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  24027880000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.120398                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1070174                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency    862763000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses        199383                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits            169379                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency   1680355000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate     0.150484                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses           30004                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency   1590343000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate     0.150484                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses        30004                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses           6160337                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits               5757309                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency   22449496500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.065093                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits               5759482                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency   22449492500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.065070                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_misses              400855                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency  21246931500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.065093                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_latency  21246927500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.065070                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_misses         400855                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1186275000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1201243500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                  10.091593                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.097318                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            15040830                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 33778.185851                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30778.154580                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                13569826                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     49687846500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.097801                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1471004                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses            15048990                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 33777.675695                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                13577961                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     49687940500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.097749                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1471029                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  45274788500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.097801                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1471004                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  45274807500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.097749                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1471029                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           15040830                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 33778.185851                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30778.154580                       # average overall mshr miss latency
+system.cpu.dcache.overall_accesses           15048990                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 33777.675695                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               13569826                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    49687846500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.097801                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1471004                       # number of overall misses
+system.cpu.dcache.overall_hits               13577961                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    49687940500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.097749                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1471029                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  45274788500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.097801                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1471004                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency   2034120000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_miss_latency  45274807500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.097749                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1471029                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency   2064006500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued            0
 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                1391586                       # number of replacements
-system.cpu.dcache.sampled_refs                1392098                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                1391606                       # number of replacements
+system.cpu.dcache.sampled_refs                1392118                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.984141                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14048487                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                511.984142                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14056658                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               84139000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   430461                       # number of writebacks
+system.cpu.dcache.writebacks                   430459                       # number of writebacks
 system.cpu.dtb.accesses                       1020784                       # DTB accesses
 system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          15421361                       # DTB hits
+system.cpu.dtb.hits                          15429793                       # DTB hits
 system.cpu.dtb.misses                           11466                       # DTB misses
 system.cpu.dtb.read_accesses                   728853                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                      9063577                       # DTB read hits
+system.cpu.dtb.read_hits                      9069700                       # DTB read hits
 system.cpu.dtb.read_misses                      10324                       # DTB read misses
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6357784                       # DTB write hits
+system.cpu.dtb.write_hits                     6360093                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.icache.ReadReq_accesses           56176946                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 14711.628674                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.898216                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               55246023                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency    13695393500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.016571                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses               930923                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency  10901944500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.016571                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          930923                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses           56217537                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 14711.221983                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               55286436                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency    13697633500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.016562                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses               931101                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency  10903650500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.016562                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses          931101                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  59.355692                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  59.387754                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            56176946                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 14711.628674                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11710.898216                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                55246023                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency     13695393500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.016571                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                930923                       # number of demand (read+write) misses
+system.cpu.icache.demand_accesses            56217537                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 14711.221983                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                55286436                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency     13697633500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.016562                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                931101                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency  10901944500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.016571                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           930923                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency  10903650500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.016562                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses           931101                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           56176946                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 14711.628674                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11710.898216                       # average overall mshr miss latency
+system.cpu.icache.overall_accesses           56217537                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 14711.221983                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               55246023                       # number of overall hits
-system.cpu.icache.overall_miss_latency    13695393500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.016571                       # miss rate for overall accesses
-system.cpu.icache.overall_misses               930923                       # number of overall misses
+system.cpu.icache.overall_hits               55286436                       # number of overall hits
+system.cpu.icache.overall_miss_latency    13697633500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.016562                       # miss rate for overall accesses
+system.cpu.icache.overall_misses               931101                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency  10901944500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.016571                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          930923                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency  10903650500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.016562                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses          931101                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -171,19 +171,19 @@ system.cpu.icache.prefetcher.num_hwpf_issued            0
 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                 930251                       # number of replacements
-system.cpu.icache.sampled_refs                 930762                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 930429                       # number of replacements
+system.cpu.icache.sampled_refs                 930940                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                508.559731                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 55246023                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                508.559728                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 55286436                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle            39055604000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                     0.929251                       # Percentage of idle cycles
-system.cpu.itb.accesses                       4982832                       # ITB accesses
+system.cpu.idle_fraction                     0.929209                       # Percentage of idle cycles
+system.cpu.itb.accesses                       4982987                       # ITB accesses
 system.cpu.itb.acv                                184                       # ITB acv
-system.cpu.itb.hits                           4977822                       # ITB hits
+system.cpu.itb.hits                           4977977                       # ITB hits
 system.cpu.itb.misses                            5010                       # ITB misses
-system.cpu.kern.callpal                        193204                       # number of callpals executed
+system.cpu.kern.callpal                        193221                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
@@ -191,7 +191,7 @@ system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # nu
 system.cpu.kern.callpal_swpctx                   4171      2.16%      2.16% # number of callpals executed
 system.cpu.kern.callpal_tbi                        54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal_wrent                       7      0.00%      2.19% # number of callpals executed
-system.cpu.kern.callpal_swpipl                 176240     91.22%     93.41% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 176257     91.22%     93.41% # number of callpals executed
 system.cpu.kern.callpal_rdps                     6844      3.54%     96.95% # number of callpals executed
 system.cpu.kern.callpal_wrkgp                       1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal_wrusp                       7      0.00%     96.96% # number of callpals executed
@@ -201,40 +201,40 @@ system.cpu.kern.callpal_rti                      5169      2.68%     99.64% # nu
 system.cpu.kern.callpal_callsys                   515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     212308                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6258                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count                      183485                       # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0                     74993     40.87%     40.87% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     212325                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6374                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      183502                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     75001     40.87%     40.87% # number of times we switched to this ipl
 system.cpu.kern.ipl_count_21                      131      0.07%     40.94% # number of times we switched to this ipl
 system.cpu.kern.ipl_count_22                     1944      1.06%     42.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31                   106417     58.00%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good                       149327                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0                      73626     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count_31                   106426     58.00%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       149343                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      73634     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_21                       131      0.09%     49.39% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_22                      1944      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31                     73626     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                1930165033000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0              1867007591000     96.73%     96.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21                 96059500      0.00%     96.73% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22                565327500      0.03%     96.76% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31              62496055000      3.24%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0                   0.981772                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good_31                     73634     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                1930163835000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0              1866810523000     96.72%     96.72% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21                 96331500      0.00%     96.72% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22                565310500      0.03%     96.75% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31              62691670000      3.25%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0                   0.981774                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31                  0.691863                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel                 1910                      
-system.cpu.kern.mode_good_user                   1743                      
+system.cpu.kern.ipl_used_31                  0.691880                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel                 1911                      
+system.cpu.kern.mode_good_user                   1744                      
 system.cpu.kern.mode_good_idle                    167                      
 system.cpu.kern.mode_switch_kernel               5917                       # number of protection mode switches
-system.cpu.kern.mode_switch_user                 1743                       # number of protection mode switches
+system.cpu.kern.mode_switch_user                 1744                       # number of protection mode switches
 system.cpu.kern.mode_switch_idle                 2089                       # number of protection mode switches
-system.cpu.kern.mode_switch_good             1.402741                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel      0.322799                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good             1.402910                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.322968                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_idle        0.079943                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel         48448667000      2.51%      2.51% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user            5540662000      0.29%      2.80% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle          1876175702000     97.20%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_kernel         48447088000      2.51%      2.51% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user            5539986000      0.29%      2.80% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle          1876176759000     97.20%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4172                       # number of times the context was actually changed
 system.cpu.kern.syscall                           326                       # number of syscalls executed
 system.cpu.kern.syscall_2                           8      2.45%      2.45% # number of syscalls executed
@@ -267,10 +267,10 @@ system.cpu.kern.syscall_98                          2      0.61%     97.55% # nu
 system.cpu.kern.syscall_132                         4      1.23%     98.77% # number of syscalls executed
 system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
-system.cpu.not_idle_fraction                 0.070749                       # Percentage of non-idle cycles
-system.cpu.numCycles                       3860331582                       # number of cpu cycles simulated
-system.cpu.num_insts                         56165112                       # Number of instructions executed
-system.cpu.num_refs                          15669461                       # Number of memory references
+system.cpu.not_idle_fraction                 0.070791                       # Percentage of non-idle cycles
+system.cpu.numCycles                       3860329186                       # number of cpu cycles simulated
+system.cpu.num_insts                         56205703                       # Number of instructions executed
+system.cpu.num_refs                          15677891                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -293,46 +293,46 @@ system.iocache.ReadReq_mshr_miss_latency     10942998                       # nu
 system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.WriteReq_avg_miss_latency 137880.578697                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85877.091981                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency       5729213806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_miss_latency 137876.559636                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       5729046806                       # number of WriteReq miss cycles
 system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
 system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency   3568364926                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency   3568197926                       # number of WriteReq MSHR miss cycles
 system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
 system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles_no_mshrs  6163.865928                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_mshrs  6163.674943                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.blocked_no_mshrs                 10472                       # number of cycles access was blocked
 system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
-system.iocache.blocked_cycles_no_mshrs       64548004                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs       64546004                       # number of cycles access was blocked
 system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.demand_accesses                  41725                       # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency   137786.765824                       # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85783.293565                       # average overall mshr miss latency
+system.iocache.demand_avg_miss_latency   137782.763427                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 85779.291168                       # average overall mshr miss latency
 system.iocache.demand_hits                          0                       # number of demand (read+write) hits
-system.iocache.demand_miss_latency         5749152804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency         5748985804                       # number of demand (read+write) miss cycles
 system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
 system.iocache.demand_misses                    41725                       # number of demand (read+write) misses
 system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency    3579307924                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency    3579140924                       # number of demand (read+write) MSHR miss cycles
 system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
 system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.iocache.overall_accesses                 41725                       # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency  137786.765824                       # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85783.293565                       # average overall mshr miss latency
+system.iocache.overall_avg_miss_latency  137782.763427                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 85779.291168                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.iocache.overall_hits                         0                       # number of overall hits
-system.iocache.overall_miss_latency        5749152804                       # number of overall miss cycles
+system.iocache.overall_miss_latency        5748985804                       # number of overall miss cycles
 system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
 system.iocache.overall_misses                   41725                       # number of overall misses
 system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency   3579307924                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency   3579140924                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
 system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
@@ -349,79 +349,79 @@ system.iocache.prefetcher.num_hwpf_squashed_from_miss            0
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse                     1.353410                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.353399                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.warmup_cycle              1762299198000                       # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle              1762299470000                       # Cycle when the warmup percentage was hit.
 system.iocache.writebacks                       41512                       # number of writebacks
-system.l2c.ReadExReq_accesses                  304625                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency    52003.272876                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.272876                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency         15841497000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_accesses                  304636                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency    52003.289171                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency         15842074000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    304625                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency    12185997000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_misses                    304636                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency    12186442000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               304625                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses                   2018377                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency      52016.376522                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.358642                       # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses               304636                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses                   2018564                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency      52016.377161                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits                       1710772                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           16000497500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate                 0.152402                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                      307605                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency      12309232000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate            0.152402                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                 307605                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    759315000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses                 126236                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency   52001.881397                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.980861                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency         6564509500                       # number of UpgradeReq miss cycles
+system.l2c.ReadReq_hits                       1710971                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           15999873500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate                 0.152382                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                      307593                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency      12308752000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate            0.152382                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                 307593                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    772673000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses                 126223                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency   52001.810288                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency         6563824500                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   126236                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    5050195000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses                   126223                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency    5049666000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses              126236                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses              126223                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1071771000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses                  430461                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits                      430461                       # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency   1085299500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses                  430459                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits                      430459                       # number of Writeback hits
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          4.436452                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          4.436562                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2323002                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency       52009.856590                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  40009.847606                       # average overall mshr miss latency
-system.l2c.demand_hits                        1710772                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            31841994500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.263551                       # miss rate for demand accesses
-system.l2c.demand_misses                       612230                       # number of demand (read+write) misses
+system.l2c.demand_accesses                    2323200                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency       52009.864773                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  40009.855789                       # average overall mshr miss latency
+system.l2c.demand_hits                        1710971                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            31841947500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate                  0.263528                       # miss rate for demand accesses
+system.l2c.demand_misses                       612229                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       24495229000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate             0.263551                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  612230                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency       24495194000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate             0.263528                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                  612229                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   2323002                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency      52009.856590                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.847606                       # average overall mshr miss latency
+system.l2c.overall_accesses                   2323200                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency      52009.864773                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.855789                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1710772                       # number of overall hits
-system.l2c.overall_miss_latency           31841994500                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.263551                       # miss rate for overall accesses
-system.l2c.overall_misses                      612230                       # number of overall misses
+system.l2c.overall_hits                       1710971                       # number of overall hits
+system.l2c.overall_miss_latency           31841947500                       # number of overall miss cycles
+system.l2c.overall_miss_rate                 0.263528                       # miss rate for overall accesses
+system.l2c.overall_misses                      612229                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      24495229000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate            0.263551                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 612230                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1831086000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency      24495194000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate            0.263528                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                 612229                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1857972500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -432,13 +432,13 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                        394925                       # number of replacements
-system.l2c.sampled_refs                        425907                       # Sample count of references to valid blocks.
+system.l2c.replacements                        394928                       # number of replacements
+system.l2c.sampled_refs                        425903                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     30594.024615                       # Cycle average of tags in use
-system.l2c.total_refs                         1889516                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     30591.543942                       # Cycle average of tags in use
+system.l2c.total_refs                         1889545                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                    6968733000                       # Cycle when the warmup percentage was hit.
-system.l2c.writebacks                          119047                       # number of writebacks
+system.l2c.writebacks                          119060                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
 system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
 system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
index 3efa225a8..ff644ed3f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
@@ -56,6 +56,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
loop: loaded (max 8 devices)
 
nbd: registered device at major 43
 
ns83820.c: National Semiconductor DP83820 10/100/1000 driver.
+
PCI: Setting latency timer of device 0000:00:01.0 to 64
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
@@ -67,6 +68,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
PIIX4: IDE controller at PCI slot 0000:00:00.0
 
PIIX4: chipset revision 0
 
PIIX4: 100% native mode on irq 31
+
PCI: Setting latency timer of device 0000:00:00.0 to 64
 
    ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA
 
    ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA
 
hda: M5 IDE Disk, ATA DISK drive