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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-06 22:14:23 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-06 22:14:23 -0800
commit45f881919fc9c4d2b2d4ea9f165fb567aad9849a (patch)
tree2a6ebbec93e62ef5279ec35e27e06f86577372fd /tests/quick/10.linux-boot
parentf5aa75fdc528aca122ac1369fa4ac3df8a915027 (diff)
downloadgem5-45f881919fc9c4d2b2d4ea9f165fb567aad9849a.tar.xz
regress: Regression Tester output updates
Diffstat (limited to 'tests/quick/10.linux-boot')
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini25
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr4
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt44
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini25
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr4
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt26
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini25
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr4
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt44
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini25
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr4
-rwxr-xr-xtests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt26
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini15
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr44
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout14
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt399
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status2
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini15
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr50
-rwxr-xr-xtests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout12
-rw-r--r--tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt483
25 files changed, 272 insertions, 1066 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 26eb3724f..a8dd05895 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -1,24 +1,33 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.bridge]
type=Bridge
@@ -265,7 +274,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -285,7 +294,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -411,7 +420,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -882,7 +891,9 @@ SubsystemID=0
SubsystemVendorID=0
VendorID=32902
config_latency=20000
+ctrl_offset=0
disks=system.disk0 system.disk2
+io_shift=0
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 41c773ee0..05b982df2 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 23:09:56
-M5 executing on aus-bc2-b15
+M5 compiled Feb 6 2011 15:18:06
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb 6 2011 20:44:52
+M5 executing on SC2B0617
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
Exiting @ tick 1870335522500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 8f44fff37..bea2dec1c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 4418519 # Simulator instruction rate (inst/s)
-host_mem_usage 326752 # Number of bytes of host memory used
-host_seconds 14.29 # Real time elapsed on the host
-host_tick_rate 130854140423 # Simulator tick rate (ticks/s)
+host_inst_rate 2482903 # Simulator instruction rate (inst/s)
+host_mem_usage 294432 # Number of bytes of host memory used
+host_seconds 25.44 # Real time elapsed on the host
+host_tick_rate 73531568595 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63154034 # Number of instructions simulated
sim_seconds 1.870336 # Number of seconds simulated
@@ -305,8 +305,24 @@ system.cpu0.kern.syscall::147 2 0.88% 100.00% # nu
system.cpu0.kern.syscall::total 226 # number of syscalls executed
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles
+system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
+system.cpu0.num_fp_insts 299810 # number of float instructions
+system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
+system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
+system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles
system.cpu0.num_insts 57222076 # Number of instructions executed
-system.cpu0.num_refs 15135515 # Number of memory references
+system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
+system.cpu0.num_int_insts 53249924 # number of integer instructions
+system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written
+system.cpu0.num_load_insts 9184477 # Number of load instructions
+system.cpu0.num_mem_refs 15135515 # number of memory refs
+system.cpu0.num_store_insts 5951038 # Number of store instructions
system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits
@@ -587,8 +603,24 @@ system.cpu1.kern.syscall::132 2 2.00% 100.00% # nu
system.cpu1.kern.syscall::total 100 # number of syscalls executed
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles
+system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
+system.cpu1.num_fp_insts 28590 # number of float instructions
+system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
+system.cpu1.num_func_calls 182742 # number of times a function call or return occured
+system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles
system.cpu1.num_insts 5931958 # Number of instructions executed
-system.cpu1.num_refs 1926244 # Number of memory references
+system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses
+system.cpu1.num_int_insts 5550578 # number of integer instructions
+system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written
+system.cpu1.num_load_insts 1170888 # Number of load instructions
+system.cpu1.num_mem_refs 1926244 # number of memory refs
+system.cpu1.num_store_insts 755356 # Number of store instructions
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index c5b353159..948e07caa 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -1,24 +1,33 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.bridge]
type=Bridge
@@ -158,7 +167,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -178,7 +187,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -304,7 +313,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -775,7 +784,9 @@ SubsystemID=0
SubsystemVendorID=0
VendorID=32902
config_latency=20000
+ctrl_offset=0
disks=system.disk0 system.disk2
+io_shift=0
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index 85e98e7a4..b54139f40 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 23:09:41
-M5 executing on aus-bc2-b15
+M5 compiled Feb 6 2011 15:18:06
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb 6 2011 20:44:51
+M5 executing on SC2B0617
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332258000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index e2b7c8ed7..09f938159 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 4413707 # Simulator instruction rate (inst/s)
-host_mem_usage 325356 # Number of bytes of host memory used
-host_seconds 13.60 # Real time elapsed on the host
-host_tick_rate 134480396261 # Simulator tick rate (ticks/s)
+host_inst_rate 2515835 # Simulator instruction rate (inst/s)
+host_mem_usage 293128 # Number of bytes of host memory used
+host_seconds 23.86 # Real time elapsed on the host
+host_tick_rate 76655119142 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60038305 # Number of instructions simulated
sim_seconds 1.829332 # Number of seconds simulated
@@ -297,8 +297,24 @@ system.cpu.kern.syscall::147 2 0.61% 100.00% # nu
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
system.cpu.numCycles 3658664408 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
+system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
+system.cpu.num_fp_insts 324460 # number of float instructions
+system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
+system.cpu.num_func_calls 1484182 # number of times a function call or return occured
+system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
system.cpu.num_insts 60038305 # Number of instructions executed
-system.cpu.num_refs 16115709 # Number of memory references
+system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
+system.cpu.num_int_insts 55913521 # number of integer instructions
+system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
+system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
+system.cpu.num_load_insts 9747513 # Number of load instructions
+system.cpu.num_mem_refs 16115709 # number of memory refs
+system.cpu.num_store_insts 6368196 # Number of store instructions
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index ef977d929..d4e4b7f37 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -1,24 +1,33 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.bridge]
type=Bridge
@@ -259,7 +268,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -279,7 +288,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -405,7 +414,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -876,7 +885,9 @@ SubsystemID=0
SubsystemVendorID=0
VendorID=32902
config_latency=20000
+ctrl_offset=0
disks=system.disk0 system.disk2
+io_shift=0
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 8585e8d27..f2cae639d 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,13 +5,13 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 23:10:42
-M5 executing on aus-bc2-b15
+M5 compiled Feb 6 2011 15:18:06
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb 6 2011 20:44:52
+M5 executing on SC2B0617
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 562628000
Exiting @ tick 1958647095000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 0517b4d72..9839f1b5a 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1781653 # Simulator instruction rate (inst/s)
-host_mem_usage 323564 # Number of bytes of host memory used
-host_seconds 33.32 # Real time elapsed on the host
-host_tick_rate 58791386546 # Simulator tick rate (ticks/s)
+host_inst_rate 1140947 # Simulator instruction rate (inst/s)
+host_mem_usage 291380 # Number of bytes of host memory used
+host_seconds 52.02 # Real time elapsed on the host
+host_tick_rate 37649358214 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 59355643 # Number of instructions simulated
sim_seconds 1.958647 # Number of seconds simulated
@@ -360,8 +360,24 @@ system.cpu0.kern.syscall::147 2 0.90% 100.00% # nu
system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles
system.cpu0.numCycles 3916023774 # number of cpu cycles simulated
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles
+system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls
+system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses
+system.cpu0.num_fp_insts 293967 # number of float instructions
+system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written
+system.cpu0.num_func_calls 1426863 # number of times a function call or return occured
+system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles
system.cpu0.num_insts 54072652 # Number of instructions executed
-system.cpu0.num_refs 14724357 # Number of memory references
+system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses
+system.cpu0.num_int_insts 50043234 # number of integer instructions
+system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written
+system.cpu0.num_load_insts 8664914 # Number of load instructions
+system.cpu0.num_mem_refs 14724357 # number of memory refs
+system.cpu0.num_store_insts 6059443 # Number of store instructions
system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency
@@ -691,8 +707,24 @@ system.cpu1.kern.syscall::132 3 2.88% 100.00% # nu
system.cpu1.kern.syscall::total 104 # number of syscalls executed
system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles
system.cpu1.numCycles 3917294190 # number of cpu cycles simulated
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles
+system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls
+system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
+system.cpu1.num_fp_insts 34031 # number of float instructions
+system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
+system.cpu1.num_func_calls 158031 # number of times a function call or return occured
+system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles
system.cpu1.num_insts 5282991 # Number of instructions executed
-system.cpu1.num_refs 1710778 # Number of memory references
+system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses
+system.cpu1.num_int_insts 4948310 # number of integer instructions
+system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written
+system.cpu1.num_load_insts 1056124 # Number of load instructions
+system.cpu1.num_mem_refs 1710778 # number of memory refs
+system.cpu1.num_store_insts 654654 # Number of store instructions
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 14aa8c52d..5942af7ad 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -1,24 +1,33 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=LinuxAlphaSystem
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/chips/pd/randd/dist/binaries/console
+console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
-pal=/chips/pd/randd/dist/binaries/ts_osfpal
+pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.bridge]
type=Bridge
@@ -155,7 +164,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -175,7 +184,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -301,7 +310,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/chips/pd/randd/dist/disks/linux-latest.img
+image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -772,7 +781,9 @@ SubsystemID=0
SubsystemVendorID=0
VendorID=32902
config_latency=20000
+ctrl_offset=0
disks=system.disk0 system.disk2
+io_shift=0
max_backoff_delay=10000000
min_backoff_delay=4000
pci_bus=0
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
index 83c71fc5c..0372a3b05 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
@@ -2,4 +2,8 @@ warn: Sockets disabled, not accepting terminal connections
For more information see: http://www.m5sim.org/warn/8742226b
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
+warn: Prefetch instrutions is Alpha do not do anything
+For more information see: http://www.m5sim.org/warn/3e0eccba
hack: be nice to actually delete the event here
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index af718c31f..7f56804aa 100755
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,5 +1,3 @@
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -7,12 +5,12 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Nov 2 2010 23:00:12
-M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
-M5 started Nov 2 2010 23:10:12
-M5 executing on aus-bc2-b15
+M5 compiled Feb 6 2011 15:18:06
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb 6 2011 20:44:52
+M5 executing on SC2B0617
command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1915548867000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 37bf681b4..cff4040d5 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1917155 # Simulator instruction rate (inst/s)
-host_mem_usage 322176 # Number of bytes of host memory used
-host_seconds 29.28 # Real time elapsed on the host
-host_tick_rate 65417896896 # Simulator tick rate (ticks/s)
+host_inst_rate 1177916 # Simulator instruction rate (inst/s)
+host_mem_usage 289856 # Number of bytes of host memory used
+host_seconds 47.66 # Real time elapsed on the host
+host_tick_rate 40193458044 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 56137087 # Number of instructions simulated
sim_seconds 1.915549 # Number of seconds simulated
@@ -341,8 +341,24 @@ system.cpu.kern.syscall::147 2 0.61% 100.00% # nu
system.cpu.kern.syscall::total 326 # number of syscalls executed
system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles
system.cpu.numCycles 3831097734 # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.num_busy_cycles 243154546.001873 # Number of busy cycles
+system.cpu.num_conditional_control_insts 6464616 # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses
+system.cpu.num_fp_insts 324192 # number of float instructions
+system.cpu.num_fp_register_reads 163510 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166384 # number of times the floating registers were written
+system.cpu.num_func_calls 1482242 # number of times a function call or return occured
+system.cpu.num_idle_cycles 3587943187.998127 # Number of idle cycles
system.cpu.num_insts 56137087 # Number of instructions executed
-system.cpu.num_refs 15462519 # Number of memory references
+system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses
+system.cpu.num_int_insts 52011214 # number of integer instructions
+system.cpu.num_int_register_reads 71259077 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38485860 # number of times the integer registers were written
+system.cpu.num_load_insts 9094324 # Number of load instructions
+system.cpu.num_mem_refs 15462519 # number of memory refs
+system.cpu.num_store_insts 6368195 # Number of store instructions
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 505488008..260c1cb37 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
@@ -9,13 +11,20 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
boot_cpu_frequency=500
boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
init_param=0
-kernel=/chips/pd/randd/dist/binaries/vmlinux.arm
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.bridge]
type=Bridge
@@ -158,7 +167,7 @@ type=ExeTracer
[system.diskmem]
type=PhysicalMemory
-file=/chips/pd/randd/dist/disks/ael-arm.ext2
+file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index 122561307..8914d507c 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
@@ -1,39 +1,5 @@
-warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: The clidr register always reports 0 caches.
-For more information see: http://www.m5sim.org/warn/23a3c326
-warn: The csselr register isn't implemented.
-For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: The ccsidr register isn't implemented and always reads as 0.
-For more information see: http://www.m5sim.org/warn/2c4acb9c
-warn: instruction 'mcr dccimvac' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr dccmvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr icimvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-For more information see: http://www.m5sim.org/warn/7998f2ea
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-hack: be nice to actually delete the event here
+fatal: Could not load kernel file /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
+ @ cycle 0
+[System:build/ARM_FS/sim/system.cc, line 118]
+Memory Usage: 210184 KBytes
+For more information see: http://www.m5sim.org/fatal/406aceb6
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 05fcdedb2..ea23f1508 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -5,12 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 15 2010 11:17:32
-M5 revision e459beb39dd0 7713 default ext/amba_kmi_pl050.patch qtip tip
-M5 started Oct 15 2010 11:17:48
-M5 executing on aus-bc3-b4
-command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
+M5 compiled Feb 6 2011 15:34:42
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb 6 2011 15:35:03
+M5 executing on svnxelk05
+command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 25821310500 because m5_exit instruction encountered
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 1bfa8bc8a..e69de29bb 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -1,399 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1831927 # Simulator instruction rate (inst/s)
-host_mem_usage 384484 # Number of bytes of host memory used
-host_seconds 27.81 # Real time elapsed on the host
-host_tick_rate 928414614 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 50949504 # Number of instructions simulated
-sim_seconds 0.025821 # Number of seconds simulated
-sim_ticks 25821310500 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 96794 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 96794 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::0 91895 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 91895 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 4899 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 4899 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0 7714516 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7714516 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 7482193 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7482193 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.030115 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 232323 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 232323 # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses::0 96793 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 96793 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 96793 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 96793 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6604860 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6604860 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 6433311 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6433311 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.025973 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 171549 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 171549 # number of WriteReq misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.663994 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14319376 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14319376 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 13915504 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13915504 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028205 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 403872 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 403872 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999475 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.731250 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 14319376 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 14319376 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 13915504 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 13915504 # number of overall hits
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.028205 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 403872 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 403872 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 406424 # number of replacements
-system.cpu.dcache.sampled_refs 406936 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.731250 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14106027 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21760000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 379025 # number of writebacks
-system.cpu.dtb.accesses 15336291 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 2242 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15330762 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5529 # DTB misses
-system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 768 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8622893 # DTB read accesses
-system.cpu.dtb.read_hits 8618361 # DTB read hits
-system.cpu.dtb.read_misses 4532 # DTB read misses
-system.cpu.dtb.write_accesses 6713398 # DTB write accesses
-system.cpu.dtb.write_hits 6712401 # DTB write hits
-system.cpu.dtb.write_misses 997 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 41172623 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 41172623 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0 40741841 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 40741841 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::0 0.010463 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 430782 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 430782 # number of ReadReq misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 94.576690 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 41172623 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 41172623 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 40741841 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 40741841 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.010463 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 430782 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 430782 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.929162 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 475.731149 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 41172623 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 41172623 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 40741841 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 40741841 # number of overall hits
-system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.010463 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 430782 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 430782 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 430269 # number of replacements
-system.cpu.icache.sampled_refs 430781 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 475.731149 # Cycle average of tags in use
-system.cpu.icache.total_refs 40741841 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 4544230000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 33727 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41173750 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41170928 # DTB hits
-system.cpu.itb.inst_accesses 41173750 # ITB inst accesses
-system.cpu.itb.inst_hits 41170928 # ITB inst hits
-system.cpu.itb.inst_misses 2822 # ITB inst misses
-system.cpu.itb.misses 2822 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 51642622 # number of cpu cycles simulated
-system.cpu.num_insts 50949504 # Number of instructions executed
-system.cpu.num_refs 16092645 # Number of memory references
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 0 # number of replacements
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 169714 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 169714 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0 60310 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 60310 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0 0.644637 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 109404 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 109404 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 665898 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 6073 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 671971 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 648226 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 6049 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 654275 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.026539 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.003952 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.030491 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 17672 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 24 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 17696 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 1835 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0 0.990736 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1818 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1818 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 412752 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 412752 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 412752 # number of Writeback hits
-system.l2c.Writeback_hits::total 412752 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 6.885433 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 835612 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 6073 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 841685 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 708536 # number of demand (read+write) hits
-system.l2c.demand_hits::1 6049 # number of demand (read+write) hits
-system.l2c.demand_hits::total 714585 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.152075 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.003952 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.156027 # miss rate for demand accesses
-system.l2c.demand_misses::0 127076 # number of demand (read+write) misses
-system.l2c.demand_misses::1 24 # number of demand (read+write) misses
-system.l2c.demand_misses::total 127100 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.072507 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.478199 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 4751.792305 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31339.221407 # Average occupied blocks per context
-system.l2c.overall_accesses::0 835612 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 6073 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 841685 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 708536 # number of overall hits
-system.l2c.overall_hits::1 6049 # number of overall hits
-system.l2c.overall_hits::total 714585 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.152075 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.003952 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.156027 # miss rate for overall accesses
-system.l2c.overall_misses::0 127076 # number of overall misses
-system.l2c.overall_misses::1 24 # number of overall misses
-system.l2c.overall_misses::total 127100 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 95922 # number of replacements
-system.l2c.sampled_refs 125830 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36091.013712 # Cycle average of tags in use
-system.l2c.total_refs 866394 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 90126 # number of writebacks
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
index 586cb6b73..53b01d583 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
@@ -1 +1 @@
-build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index c7f419728..55ac85829 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -1,7 +1,9 @@
[root]
type=Root
children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
@@ -9,13 +11,20 @@ children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview t
boot_cpu_frequency=500
boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm
+kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
[system.bridge]
type=Bridge
@@ -155,7 +164,7 @@ type=ExeTracer
[system.diskmem]
type=PhysicalMemory
-file=/dist/m5/system/disks/ael-arm.ext2
+file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index e76a50eec..8914d507c 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
@@ -1,45 +1,5 @@
-warn: Sockets disabled, not accepting terminal connections
-For more information see: http://www.m5sim.org/warn/8742226b
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-warn: The clidr register always reports 0 caches.
-For more information see: http://www.m5sim.org/warn/23a3c326
-warn: The csselr register isn't implemented.
-For more information see: http://www.m5sim.org/warn/c0c486b8
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: The ccsidr register isn't implemented and always reads as 0.
-For more information see: http://www.m5sim.org/warn/2c4acb9c
-warn: instruction 'mcr dccimvac' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr dccmvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr icimvau' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-For more information see: http://www.m5sim.org/warn/7998f2ea
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Complete acc isn't called on normal stores in O3.
-For more information see: http://www.m5sim.org/warn/138d8573
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-warn: Complete acc isn't called on normal stores in O3.
-For more information see: http://www.m5sim.org/warn/138d8573
-warn: Complete acc isn't called on normal stores in O3.
-For more information see: http://www.m5sim.org/warn/138d8573
-warn: Need to flush all TLBs in MP
-For more information see: http://www.m5sim.org/warn/6cccf999
-warn: instruction 'mcr bpiall' unimplemented
-For more information see: http://www.m5sim.org/warn/21b09adb
-hack: be nice to actually delete the event here
+fatal: Could not load kernel file /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
+ @ cycle 0
+[System:build/ARM_FS/sim/system.cc, line 118]
+Memory Usage: 210184 KBytes
+For more information see: http://www.m5sim.org/fatal/406aceb6
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index 8382cb48d..2dd6d32f6 100755
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -5,12 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jan 17 2011 18:36:49
-M5 revision f72d94f8c275 7839 default qtip tip outgoing.patch qbase
-M5 started Jan 17 2011 18:36:52
-M5 executing on zizzer
+M5 compiled Feb 6 2011 15:34:42
+M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
+M5 started Feb 6 2011 15:35:03
+M5 executing on svnxelk05
command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 114721074000 because m5_exit instruction encountered
+info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux.arm
diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index 157177a6b..e69de29bb 100644
--- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -1,483 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1461109 # Simulator instruction rate (inst/s)
-host_mem_usage 340352 # Number of bytes of host memory used
-host_seconds 34.61 # Real time elapsed on the host
-host_tick_rate 3314430509 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 50572425 # Number of instructions simulated
-sim_seconds 0.114721 # Number of seconds simulated
-sim_ticks 114721074000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
-system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 14087950 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 14087950 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 408690 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 408690 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 411628 # number of replacements
-system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 382676 # number of writebacks
-system.cpu.dtb.accesses 15524935 # DTB accesses
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB
-system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15519414 # DTB hits
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5521 # DTB misses
-system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8740303 # DTB read accesses
-system.cpu.dtb.read_hits 8735762 # DTB read hits
-system.cpu.dtb.read_misses 4541 # DTB read misses
-system.cpu.dtb.write_accesses 6784632 # DTB write accesses
-system.cpu.dtb.write_hits 6783652 # DTB write hits
-system.cpu.dtb.write_misses 980 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 41110405 # number of overall hits
-system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 41110405 # number of overall hits
-system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 433396 # number of overall misses
-system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 433396 # number of overall misses
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 432883 # number of replacements
-system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use
-system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 33555 # number of writebacks
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41546620 # DTB accesses
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
-system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41543801 # DTB hits
-system.cpu.itb.inst_accesses 41546620 # ITB inst accesses
-system.cpu.itb.inst_hits 41543801 # ITB inst hits
-system.cpu.itb.inst_misses 2819 # ITB inst misses
-system.cpu.itb.misses 2819 # DTB misses
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 229442148 # number of cpu cycles simulated
-system.cpu.num_insts 50572425 # Number of instructions executed
-system.cpu.num_refs 16289993 # Number of memory references
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 0 # number of replacements
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.writebacks 0 # number of writebacks
-system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
-system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles
-system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 35 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 416231 # number of Writeback hits
-system.l2c.Writeback_hits::total 416231 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 6.975292 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.l2c.demand_hits::0 716275 # number of demand (read+write) hits
-system.l2c.demand_hits::1 5617 # number of demand (read+write) hits
-system.l2c.demand_hits::total 721892 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses
-system.l2c.demand_misses::0 127149 # number of demand (read+write) misses
-system.l2c.demand_misses::1 35 # number of demand (read+write) misses
-system.l2c.demand_misses::total 127184 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context
-system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 716275 # number of overall hits
-system.l2c.overall_hits::1 5617 # number of overall hits
-system.l2c.overall_hits::total 721892 # number of overall hits
-system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses
-system.l2c.overall_misses::0 127149 # number of overall misses
-system.l2c.overall_misses::1 35 # number of overall misses
-system.l2c.overall_misses::total 127184 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 94170 # number of replacements
-system.l2c.sampled_refs 125831 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use
-system.l2c.total_refs 877708 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 87626 # number of writebacks
-
----------- End Simulation Statistics ----------