diff options
| author | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
|---|---|---|
| committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2010-02-25 10:08:41 -0800 |
| commit | ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c (patch) | |
| tree | 93b9bd8be890468c550b85eae4b467285b4d6811 /tests/quick/10.linux-boot | |
| parent | 7f3cd9a9fd636c1e48dcec20de3f6c14214d0ce4 (diff) | |
| download | gem5-ee20a7c0bddf1f2a1913ddb176910bdce4c13b9c.tar.xz | |
stats: update stats for the changes I pushed re: shared cache occupancy
Diffstat (limited to 'tests/quick/10.linux-boot')
12 files changed, 1386 insertions, 562 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 40be52d31..e7e943434 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -74,7 +74,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -181,7 +181,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -216,7 +216,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -264,7 +264,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -284,7 +284,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -312,7 +312,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -343,7 +343,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=2 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -410,7 +410,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index fbb703fe5..643403e5a 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:46 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:12 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 7f868c60a..591b54757 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,29 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4214021 # Simulator instruction rate (inst/s) -host_mem_usage 277380 # Number of bytes of host memory used -host_seconds 14.99 # Real time elapsed on the host -host_tick_rate 124797908529 # Simulator tick rate (ticks/s) +host_inst_rate 2090501 # Simulator instruction rate (inst/s) +host_mem_usage 278608 # Number of bytes of host memory used +host_seconds 30.21 # Real time elapsed on the host +host_tick_rate 61910551280 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated sim_ticks 1870335522500 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_hits 172138 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_rate 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16159 # number of LoadLockedReq misses -system.cpu0.dcache.ReadReq_accesses 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 7298106 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1683563 # number of ReadReq misses -system.cpu0.dcache.StoreCondReq_accesses 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_hits 159838 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_rate 0.146793 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 27500 # number of StoreCondReq misses -system.cpu0.dcache.WriteReq_accesses 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 5374453 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.065030 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 373808 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_accesses::0 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_hits::0 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 16159 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_accesses::0 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::0 7298106 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_rate::0 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1683563 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses +system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_hits::0 159838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 159838 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.146793 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 27500 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 27500 # number of StoreCondReq misses +system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_hits::0 5374453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5374453 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_rate::0 0.065030 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 373808 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 373808 # number of WriteReq misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. @@ -32,31 +44,57 @@ system.cpu0.dcache.blocked::no_targets 0 # nu system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.demand_accesses::0 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::0 12672559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12672559 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.139673 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate::0 0.139673 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.dcache.demand_misses::0 2057371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2057371 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.dcache.occ_%::0 0.985990 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 504.827058 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::0 12672559 # number of overall hits +system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::total 12672559 # number of overall hits system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.139673 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 2057371 # number of overall misses +system.cpu0.dcache.overall_miss_rate::0 0.139673 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.dcache.overall_misses::0 2057371 # number of overall misses +system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::total 2057371 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -83,10 +121,13 @@ system.cpu0.dtb.write_accesses 189050 # DT system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_hits 5936899 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.icache.ReadReq_accesses 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 885000 # number of ReadReq misses +system.cpu0.icache.ReadReq_accesses::0 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_hits::0 56345132 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_rate::0 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 885000 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. @@ -95,31 +136,57 @@ system.cpu0.icache.blocked::no_targets 0 # nu system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.demand_accesses::0 57230132 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.demand_hits 56345132 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::0 56345132 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_misses 885000 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate::0 0.015464 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.icache.demand_misses::0 885000 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu0.icache.occ_%::0 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 511.244754 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 57230132 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 56345132 # number of overall hits +system.cpu0.icache.overall_hits::0 56345132 # number of overall hits +system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::total 56345132 # number of overall hits system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_misses 885000 # number of overall misses +system.cpu0.icache.overall_miss_rate::0 0.015464 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.icache.overall_misses::0 885000 # number of overall misses +system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::total 885000 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -240,22 +307,34 @@ system.cpu0.not_idle_fraction 0.015300 # Pe system.cpu0.numCycles 3740670933 # number of cpu cycles simulated system.cpu0.num_insts 57222076 # Number of instructions executed system.cpu0.num_refs 15330887 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses -system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses -system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses -system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses +system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses +system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_hits::0 13438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 13438 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.177853 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 2907 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2907 # number of StoreCondReq misses +system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_hits::0 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 702803 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_rate::0 0.041595 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 30502 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 30502 # number of WriteReq misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. @@ -264,31 +343,57 @@ system.cpu1.dcache.blocked::no_targets 0 # nu system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1812118 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1812118 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate::0 0.038292 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.dcache.demand_misses::0 72152 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 72152 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.dcache.occ_%::0 0.765530 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::0 1812118 # number of overall hits +system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::total 1812118 # number of overall hits system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 72152 # number of overall misses +system.cpu1.dcache.overall_miss_rate::0 0.038292 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.dcache.overall_misses::0 72152 # number of overall misses +system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::total 72152 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -315,10 +420,13 @@ system.cpu1.dtb.write_accesses 103280 # DT system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_hits 751446 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses +system.cpu1.icache.ReadReq_accesses::0 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_hits::0 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_rate::0 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 103630 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. @@ -327,31 +435,57 @@ system.cpu1.icache.blocked::no_targets 0 # nu system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.demand_accesses::0 5935766 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::0 5832136 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate::0 0.017459 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.icache.demand_misses::0 103630 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu1.icache.occ_%::0 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 427.126317 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 5935766 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5832136 # number of overall hits +system.cpu1.icache.overall_hits::0 5832136 # number of overall hits +system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::total 5832136 # number of overall hits system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_misses 103630 # number of overall misses +system.cpu1.icache.overall_miss_rate::0 0.017459 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.icache.overall_misses::0 103630 # number of overall misses +system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::total 103630 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -467,12 +601,16 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 175 # number of ReadReq misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. @@ -481,31 +619,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41727 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 0 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41727 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41727 # number of demand (read+write) misses +system.iocache.demand_misses::total 41727 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41727 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 0 # average overall miss latency +system.iocache.occ_%::1 0.027215 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41727 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41727 # number of overall misses +system.iocache.overall_misses::total 41727 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -516,18 +680,37 @@ system.iocache.tagsinuse 0.435437 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306247 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306247 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2724267 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1759731 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.354053 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 964536 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 125007 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 125007 # number of UpgradeReq misses -system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 427641 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 282023 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 24224 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306247 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 282023 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 24224 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 306247 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2581928 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 142339 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2724267 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1623113 # number of ReadReq hits +system.l2c.ReadReq_hits::1 136618 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1759731 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.371356 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.040193 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 958815 # number of ReadReq misses +system.l2c.ReadReq_misses::1 5721 # number of ReadReq misses +system.l2c.ReadReq_misses::total 964536 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 117429 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 7578 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 125007 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 117429 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 7578 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 125007 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 427641 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 427641 # number of Writeback hits +system.l2c.Writeback_hits::total 427641 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 1.788900 # Average number of references to valid blocks. @@ -536,31 +719,73 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 3030514 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 2863951 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 166563 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3030514 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency +system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 1759731 # number of demand (read+write) hits +system.l2c.demand_hits::0 1623113 # number of demand (read+write) hits +system.l2c.demand_hits::1 136618 # number of demand (read+write) hits +system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1759731 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.419329 # miss rate for demand accesses -system.l2c.demand_misses 1270783 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.433261 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.179782 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 1240838 # number of demand (read+write) misses +system.l2c.demand_misses::1 29945 # number of demand (read+write) misses +system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 1270783 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 no_value # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 3030514 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.079636 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.003863 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.382298 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5219.016701 # Average occupied blocks per context +system.l2c.occ_blocks::1 253.146931 # Average occupied blocks per context +system.l2c.occ_blocks::2 25054.312004 # Average occupied blocks per context +system.l2c.overall_accesses::0 2863951 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 166563 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3030514 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency +system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1759731 # number of overall hits +system.l2c.overall_hits::0 1623113 # number of overall hits +system.l2c.overall_hits::1 136618 # number of overall hits +system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::total 1759731 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.419329 # miss rate for overall accesses -system.l2c.overall_misses 1270783 # number of overall misses +system.l2c.overall_miss_rate::0 0.433261 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.179782 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 1240838 # number of overall misses +system.l2c.overall_misses::1 29945 # number of overall misses +system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::total 1270783 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 no_value # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index d098a0440..5eca545be 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -74,7 +74,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -109,7 +109,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -157,7 +157,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -177,7 +177,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -205,7 +205,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -236,7 +236,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -303,7 +303,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index ee81c2844..a264b4253 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:46 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:11 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 0982d41b4..8a27a93dd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,29 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4370209 # Simulator instruction rate (inst/s) -host_mem_usage 276044 # Number of bytes of host memory used -host_seconds 13.74 # Real time elapsed on the host -host_tick_rate 133154437863 # Simulator tick rate (ticks/s) +host_inst_rate 2156504 # Simulator instruction rate (inst/s) +host_mem_usage 277176 # Number of bytes of host memory used +host_seconds 27.84 # Real time elapsed on the host +host_tick_rate 65706739181 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated sim_ticks 1829332258000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses -system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 29867 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 29867 # number of StoreCondReq misses +system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5753150 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.064920 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 399424 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 399424 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. @@ -32,31 +44,57 @@ system.cpu.dcache.blocked::no_targets 0 # nu system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13560932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13560932 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate::0 0.135258 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 2121129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2121129 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.dcache.occ_%::0 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13560932 # number of overall hits +system.cpu.dcache.overall_hits::0 13560932 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 13560932 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2121129 # number of overall misses +system.cpu.dcache.overall_miss_rate::0 0.135258 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 2121129 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 2121129 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -83,10 +121,13 @@ system.cpu.dtb.write_accesses 291931 # DT system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6352498 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. @@ -95,31 +136,57 @@ system.cpu.icache.blocked::no_targets 0 # nu system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses -system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency +system.cpu.icache.occ_%::0 0.998467 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 59129922 # number of overall hits +system.cpu.icache.overall_hits::0 59129922 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 59129922 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses -system.cpu.icache.overall_misses 920221 # number of overall misses +system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 920221 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 920221 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -247,12 +314,16 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 174 # number of ReadReq misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. @@ -261,31 +332,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41726 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 0 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency +system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41726 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41726 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 0 # average overall miss latency +system.iocache.occ_%::1 0.076598 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency +system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency +system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41726 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 0 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -296,18 +393,27 @@ system.iocache.tagsinuse 1.225570 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses -system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits 1696652 # number of ReadReq hits -system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 962419 # number of ReadReq misses -system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses -system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 428893 # number of Writeback hits +system.l2c.ReadExReq_accesses::0 304346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 304346 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 304346 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659071 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 1696652 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1696652 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses +system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 124945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 124945 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 124945 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 428893 # number of Writeback hits +system.l2c.Writeback_hits::total 428893 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. @@ -316,31 +422,59 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 0 # average overall miss latency +system.l2c.demand_accesses::0 2963417 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963417 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses -system.l2c.demand_misses 1266765 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 0 # average overall miss latency +system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context +system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context +system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency +system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits 1696652 # number of overall hits +system.l2c.overall_hits::0 1696652 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1696652 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses -system.l2c.overall_misses 1266765 # number of overall misses +system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 1266765 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 1266765 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 85ee22259..9ac931352 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -71,7 +71,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -106,7 +106,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -175,7 +175,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -210,7 +210,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -258,7 +258,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -278,7 +278,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -306,7 +306,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -337,7 +337,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=2 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -404,7 +404,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index a32910fc6..e1106068b 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:47 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:33:27 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1972135461000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index cacc7d9bd..2f0d6d26e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,55 +1,83 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1978894 # Simulator instruction rate (inst/s) -host_mem_usage 274156 # Number of bytes of host memory used -host_seconds 30.03 # Real time elapsed on the host -host_tick_rate 65677834484 # Simulator tick rate (ticks/s) +host_inst_rate 561145 # Simulator instruction rate (inst/s) +host_mem_usage 275328 # Number of bytes of host memory used +host_seconds 105.89 # Real time elapsed on the host +host_tick_rate 18624028525 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59420593 # Number of instructions simulated sim_seconds 1.972135 # Number of seconds simulated sim_ticks 1972135461000 # Number of ticks simulated -system.cpu0.dcache.LoadLockedReq_accesses 192630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency 14259.465279 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_accesses::0 192630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14259.465279 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits 175911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::0 175911 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 175911 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate 0.086793 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses 16719 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.086793 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 16719 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16719 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.086793 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses 8488393 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_accesses::0 8488393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8488393 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 25694.266311 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits 7449690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::0 7449690 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7449690 # number of ReadReq hits system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.122367 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 1038703 # number of ReadReq misses +system.cpu0.dcache.ReadReq_miss_rate::0 0.122367 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1038703 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1038703 # number of ReadReq misses system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122367 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses 191666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_accesses::0 191666 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191666 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55344.484086 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits 163357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::0 163357 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 163357 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate 0.147700 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses 28309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.147700 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 28309 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 28309 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.147700 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 5847430 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_accesses::0 5847430 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5847430 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 55891.373878 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits 5468175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::0 5468175 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5468175 # number of WriteReq hits system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.064858 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 379255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_miss_rate::0 0.064858 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 379255 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 379255 # number of WriteReq misses system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064858 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -60,31 +88,57 @@ system.cpu0.dcache.blocked::no_targets 0 # nu system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 14335823 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_accesses::0 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14335823 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::0 12917865 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12917865 # number of demand (read+write) hits system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.098910 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_miss_rate::0 0.098910 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.dcache.demand_misses::0 1417958 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1417958 # number of demand (read+write) misses system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_miss_latency 43631879500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.098910 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_misses 1417958 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.overall_accesses 14335823 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 33770.954076 # average overall miss latency +system.cpu0.dcache.occ_%::0 0.983612 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 503.609177 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses::0 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14335823 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 33770.954076 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 12917865 # number of overall hits +system.cpu0.dcache.overall_hits::0 12917865 # number of overall hits +system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::total 12917865 # number of overall hits system.cpu0.dcache.overall_miss_latency 47885794500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.098910 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 1417958 # number of overall misses +system.cpu0.dcache.overall_miss_rate::0 0.098910 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.dcache.overall_misses::0 1417958 # number of overall misses +system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::total 1417958 # number of overall misses system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_miss_latency 43631879500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.098910 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_misses 1417958 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 2124474000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -111,15 +165,22 @@ system.cpu0.dtb.write_accesses 195659 # DT system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_hits 6040102 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses -system.cpu0.icache.ReadReq_accesses 54164416 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_accesses::0 54164416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54164416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 14681.637172 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11680.885800 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 53248092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::0 53248092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53248092 # number of ReadReq hits system.cpu0.icache.ReadReq_miss_latency 13453136500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.016917 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 916324 # number of ReadReq misses +system.cpu0.icache.ReadReq_miss_rate::0 0.016917 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 916324 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916324 # number of ReadReq misses system.cpu0.icache.ReadReq_mshr_miss_latency 10703476000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.016917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_misses 916324 # number of ReadReq MSHR misses system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -129,31 +190,57 @@ system.cpu0.icache.blocked::no_targets 0 # nu system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 54164416 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.demand_accesses::0 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54164416 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.demand_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency -system.cpu0.icache.demand_hits 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::0 53248092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53248092 # number of demand (read+write) hits system.cpu0.icache.demand_miss_latency 13453136500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.016917 # miss rate for demand accesses -system.cpu0.icache.demand_misses 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_miss_rate::0 0.016917 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu0.icache.demand_misses::0 916324 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916324 # number of demand (read+write) misses system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_miss_latency 10703476000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::0 0.016917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_misses 916324 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.overall_accesses 54164416 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14681.637172 # average overall miss latency +system.cpu0.icache.occ_%::0 0.993443 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 508.642782 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 54164416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54164416 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 14681.637172 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu0.icache.overall_avg_mshr_miss_latency 11680.885800 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 53248092 # number of overall hits +system.cpu0.icache.overall_hits::0 53248092 # number of overall hits +system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::total 53248092 # number of overall hits system.cpu0.icache.overall_miss_latency 13453136500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.016917 # miss rate for overall accesses -system.cpu0.icache.overall_misses 916324 # number of overall misses +system.cpu0.icache.overall_miss_rate::0 0.016917 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu0.icache.overall_misses::0 916324 # number of overall misses +system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::total 916324 # number of overall misses system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu0.icache.overall_mshr_miss_latency 10703476000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::0 0.016917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_misses 916324 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -274,48 +361,76 @@ system.cpu0.not_idle_fraction 0.066840 # Pe system.cpu0.numCycles 3944270922 # number of cpu cycles simulated system.cpu0.num_insts 54155641 # Number of instructions executed system.cpu0.num_refs 14946215 # Number of memory references -system.cpu1.dcache.LoadLockedReq_accesses 12334 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency 13303.501946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_accesses::0 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 12334 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13303.501946 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits 11306 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 11306 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 11306 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate 0.083347 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses 1028 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.083347 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 1028 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1028 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.083347 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses 1020543 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_accesses::0 1020543 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1020543 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15771.782317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits 984803 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::0 984803 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 984803 # number of ReadReq hits system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.035021 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 35740 # number of ReadReq misses +system.cpu1.dcache.ReadReq_miss_rate::0 0.035021 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 35740 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 35740 # number of ReadReq misses system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035021 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses 12270 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_accesses::0 12270 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 12270 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 46841.453344 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_hits 9848 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::0 9848 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 9848 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate 0.197392 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses 2422 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.197392 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 2422 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2422 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.197392 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 650008 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_accesses::0 650008 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 650008 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 54644.846691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits 623656 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::0 623656 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 623656 # number of WriteReq hits system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.040541 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 26352 # number of WriteReq misses +system.cpu1.dcache.WriteReq_miss_rate::0 0.040541 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 26352 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 26352 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.040541 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -326,31 +441,57 @@ system.cpu1.dcache.blocked::no_targets 0 # nu system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 1670551 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_accesses::0 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1670551 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::0 1608459 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1608459 # number of demand (read+write) hits system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.037169 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_miss_rate::0 0.037169 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.dcache.demand_misses::0 62092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 62092 # number of demand (read+write) misses system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.037169 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.overall_accesses 1670551 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 32269.608001 # average overall miss latency +system.cpu1.dcache.occ_%::0 0.759529 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 388.878897 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1670551 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 32269.608001 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 1608459 # number of overall hits +system.cpu1.dcache.overall_hits::0 1608459 # number of overall hits +system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::total 1608459 # number of overall hits system.cpu1.dcache.overall_miss_latency 2003684500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.037169 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 62092 # number of overall misses +system.cpu1.dcache.overall_miss_rate::0 0.037169 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.dcache.overall_misses::0 62092 # number of overall misses +system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::total 62092 # number of overall misses system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_miss_latency 1817405000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.037169 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_misses 62092 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 315545000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -377,15 +518,22 @@ system.cpu1.dtb.write_accesses 97040 # DT system.cpu1.dtb.write_acv 48 # DTB write access violations system.cpu1.dtb.write_hits 664141 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses -system.cpu1.icache.ReadReq_accesses 5268142 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_accesses::0 5268142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5268142 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.211446 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11616.771124 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 5180706 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::0 5180706 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5180706 # number of ReadReq hits system.cpu1.icache.ReadReq_miss_latency 1278070500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.016597 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 87436 # number of ReadReq misses +system.cpu1.icache.ReadReq_miss_rate::0 0.016597 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 87436 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 87436 # number of ReadReq misses system.cpu1.icache.ReadReq_mshr_miss_latency 1015724000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_misses 87436 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -395,31 +543,57 @@ system.cpu1.icache.blocked::no_targets 0 # nu system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 5268142 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.demand_accesses::0 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5268142 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.demand_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency -system.cpu1.icache.demand_hits 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::0 5180706 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5180706 # number of demand (read+write) hits system.cpu1.icache.demand_miss_latency 1278070500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.016597 # miss rate for demand accesses -system.cpu1.icache.demand_misses 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_miss_rate::0 0.016597 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu1.icache.demand_misses::0 87436 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 87436 # number of demand (read+write) misses system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu1.icache.demand_mshr_miss_latency 1015724000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.016597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_misses 87436 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.overall_accesses 5268142 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 14617.211446 # average overall miss latency +system.cpu1.icache.occ_%::0 0.819152 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 419.405627 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 5268142 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5268142 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14617.211446 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu1.icache.overall_avg_mshr_miss_latency 11616.771124 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 5180706 # number of overall hits +system.cpu1.icache.overall_hits::0 5180706 # number of overall hits +system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::total 5180706 # number of overall hits system.cpu1.icache.overall_miss_latency 1278070500 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.016597 # miss rate for overall accesses -system.cpu1.icache.overall_misses 87436 # number of overall misses +system.cpu1.icache.overall_miss_rate::0 0.016597 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu1.icache.overall_misses::0 87436 # number of overall misses +system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::total 87436 # number of overall misses system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu1.icache.overall_mshr_miss_latency 1015724000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.016597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_misses 87436 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -539,23 +713,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_accesses::1 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115196.617978 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 178 # number of ReadReq misses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137902.310503 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses system.iocache.avg_blocked_cycles::no_mshrs 6169.706090 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -565,31 +751,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 64528956 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41730 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41730 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41730 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137805.458998 # average overall miss latency +system.iocache.occ_%::1 0.036380 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.582075 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137805.458998 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41730 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -600,41 +812,78 @@ system.iocache.tagsinuse 0.582075 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses 306814 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52002.656333 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 285538 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 21276 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306814 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55877.476903 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 749912.718556 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 306814 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 285538 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 21276 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 306814 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1.074512 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 14.420662 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2090305 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.275832 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 1969770 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 120535 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2090305 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52549.257150 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 5128541.212316 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1782886 # number of ReadReq hits +system.l2c.ReadReq_hits::0 1665469 # number of ReadReq hits +system.l2c.ReadReq_hits::1 117417 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1782886 # number of ReadReq hits system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.147069 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307419 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.154486 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.025868 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304301 # number of ReadReq misses +system.l2c.ReadReq_misses::1 3118 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307419 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.147064 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.156063 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.550363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 127238 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 50741.170091 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 120870 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 6368 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 127238 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 53414.453545 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 1013851.287688 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.242145 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 6456205000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 127238 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 120870 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 6368 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 127238 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 5090187000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.052685 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 19.980842 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 127238 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430351 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430351 # number of Writeback hits +system.l2c.Writeback_accesses::0 430351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430351 # number of Writeback hits +system.l2c.Writeback_hits::total 430351 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.554189 # Average number of references to valid blocks. @@ -643,31 +892,73 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2397119 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.demand_accesses::0 2255308 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 141811 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2397119 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 54160.431067 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency -system.l2c.demand_hits 1782886 # number of demand (read+write) hits +system.l2c.demand_hits::0 1665469 # number of demand (read+write) hits +system.l2c.demand_hits::1 117417 # number of demand (read+write) hits +system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1782886 # number of demand (read+write) hits system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.256238 # miss rate for demand accesses -system.l2c.demand_misses 614233 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.261534 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.172018 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 589839 # number of demand (read+write) misses +system.l2c.demand_misses::1 24394 # number of demand (read+write) misses +system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 614233 # number of demand (read+write) misses system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.256233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.272345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 4.331272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2397119 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.472790 # average overall miss latency +system.l2c.occ_%::0 0.090499 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.002713 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.377667 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5930.966720 # Average occupied blocks per context +system.l2c.occ_blocks::1 177.784506 # Average occupied blocks per context +system.l2c.occ_blocks::2 24750.754224 # Average occupied blocks per context +system.l2c.overall_accesses::0 2255308 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 141811 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2397119 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 54160.431067 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1309581.638928 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1782886 # number of overall hits +system.l2c.overall_hits::0 1665469 # number of overall hits +system.l2c.overall_hits::1 117417 # number of overall hits +system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::total 1782886 # number of overall hits system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.256238 # miss rate for overall accesses -system.l2c.overall_misses 614233 # number of overall misses +system.l2c.overall_miss_rate::0 0.261534 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.172018 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 589839 # number of overall misses +system.l2c.overall_misses::1 24394 # number of overall misses +system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::total 614233 # number of overall misses system.l2c.overall_mshr_hits 11 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.256233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.272345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 4.331272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 64bcede47..e4db07faf 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -71,7 +71,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -106,7 +106,7 @@ hash_delay=1 latency=1000 max_miss_count=0 mshrs=4 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 @@ -154,7 +154,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.disk2] @@ -174,7 +174,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -202,7 +202,7 @@ hash_delay=1 latency=50000 max_miss_count=0 mshrs=20 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=500000 @@ -233,7 +233,7 @@ hash_delay=1 latency=10000 max_miss_count=0 mshrs=92 -prefetch_cache_check_push=true +num_cpus=1 prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 @@ -300,7 +300,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 5109c8767..36f5fe7a9 100755 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:02:48 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:10:46 -M5 executing on maize +M5 compiled Feb 24 2010 23:13:04 +M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip +M5 started Feb 24 2010 23:13:12 +M5 executing on SC2B0619 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /proj/aatl_perfmod_arch/m5_system_files/m5_system_2.0b3/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1930164593000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 3dedbe829..fafd614fd 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,55 +1,83 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1870819 # Simulator instruction rate (inst/s) -host_mem_usage 272832 # Number of bytes of host memory used -host_seconds 30.04 # Real time elapsed on the host -host_tick_rate 64245310717 # Simulator tick rate (ticks/s) +host_inst_rate 828053 # Simulator instruction rate (inst/s) +host_mem_usage 274124 # Number of bytes of host memory used +host_seconds 67.88 # Real time elapsed on the host +host_tick_rate 28436098912 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56205703 # Number of instructions simulated sim_seconds 1.930165 # Number of seconds simulated sim_ticks 1930164593000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses 200404 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency 14361.546017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits 183095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate 0.086371 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses 17309 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 8888653 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 25452.354477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits 7818479 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.120398 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1070174 # number of ReadReq misses +system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1070174 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses 199383 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_avg_miss_latency 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits 169379 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate 0.150484 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses 30004 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.150484 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses 6160337 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56004.022652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_accesses::0 6160337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits 5759482 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.065070 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate::0 0.065070 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1201243500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -60,31 +88,57 @@ system.cpu.dcache.blocked::no_targets 0 # nu system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 15048990 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.demand_accesses::0 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15048990 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency -system.cpu.dcache.demand_hits 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 13577961 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13577961 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 49687940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.097749 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_miss_rate::0 0.097749 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.dcache.demand_misses::0 1471029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1471029 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.097749 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 1471029 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 15048990 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33777.675695 # average overall miss latency +system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.984142 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15048990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15048990 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 33777.675695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 13577961 # number of overall hits +system.cpu.dcache.overall_hits::0 13577961 # number of overall hits +system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::total 13577961 # number of overall hits system.cpu.dcache.overall_miss_latency 49687940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.097749 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1471029 # number of overall misses +system.cpu.dcache.overall_miss_rate::0 0.097749 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.dcache.overall_misses::0 1471029 # number of overall misses +system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::total 1471029 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 45274807500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.097749 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 1471029 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 2064006500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -111,15 +165,22 @@ system.cpu.dtb.write_accesses 291931 # DT system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_hits 6360093 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.icache.ReadReq_accesses 56217537 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_accesses::0 56217537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56217537 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14711.221983 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 55286436 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::0 55286436 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55286436 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.016562 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 931101 # number of ReadReq misses +system.cpu.icache.ReadReq_miss_rate::0 0.016562 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 931101 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 931101 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016562 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 931101 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -129,31 +190,57 @@ system.cpu.icache.blocked::no_targets 0 # nu system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 56217537 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.demand_accesses::0 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56217537 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency -system.cpu.icache.demand_hits 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 55286436 # number of demand (read+write) hits +system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55286436 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 13697633500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.016562 # miss rate for demand accesses -system.cpu.icache.demand_misses 931101 # number of demand (read+write) misses +system.cpu.icache.demand_miss_rate::0 0.016562 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses +system.cpu.icache.demand_misses::0 931101 # number of demand (read+write) misses +system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 931101 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 10903650500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.016562 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 931101 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 56217537 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 14711.221983 # average overall miss latency +system.cpu.icache.occ_%::0 0.993281 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 508.559728 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 56217537 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56217537 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14711.221983 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 55286436 # number of overall hits +system.cpu.icache.overall_hits::0 55286436 # number of overall hits +system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::total 55286436 # number of overall hits system.cpu.icache.overall_miss_latency 13697633500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.016562 # miss rate for overall accesses -system.cpu.icache.overall_misses 931101 # number of overall misses +system.cpu.icache.overall_miss_rate::0 0.016562 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses +system.cpu.icache.overall_misses::0 931101 # number of overall misses +system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::total 931101 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 10903650500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.016562 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -281,23 +368,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_avg_miss_latency 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115254.323699 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_misses 173 # number of ReadReq misses +system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_avg_miss_latency 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137876.559636 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_misses 41552 # number of WriteReq misses +system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked @@ -307,31 +406,57 @@ system.iocache.blocked::no_targets 0 # nu system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.demand_accesses 41725 # number of demand (read+write) accesses -system.iocache.demand_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses +system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses +system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.demand_avg_miss_latency::total inf # average overall miss latency system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency -system.iocache.demand_hits 0 # number of demand (read+write) hits +system.iocache.demand_hits::0 0 # number of demand (read+write) hits +system.iocache.demand_hits::1 0 # number of demand (read+write) hits +system.iocache.demand_hits::total 0 # number of demand (read+write) hits system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_rate 1 # miss rate for demand accesses -system.iocache.demand_misses 41725 # number of demand (read+write) misses +system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses +system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses +system.iocache.demand_misses::0 0 # number of demand (read+write) misses +system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.overall_accesses 41725 # number of overall (read+write) accesses -system.iocache.overall_avg_miss_latency 137782.763427 # average overall miss latency +system.iocache.occ_%::1 0.084587 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.353399 # Average occupied blocks per context +system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses +system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses +system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137782.763427 # average overall miss latency +system.iocache.overall_avg_miss_latency::total inf # average overall miss latency system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.overall_hits 0 # number of overall hits +system.iocache.overall_hits::0 0 # number of overall hits +system.iocache.overall_hits::1 0 # number of overall hits +system.iocache.overall_hits::total 0 # number of overall hits system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles -system.iocache.overall_miss_rate 1 # miss rate for overall accesses -system.iocache.overall_misses 41725 # number of overall misses +system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses +system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses +system.iocache.overall_misses::0 0 # number of overall misses +system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -342,40 +467,61 @@ system.iocache.tagsinuse 1.353399 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses 304636 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 304636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304636 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52003.289171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 304636 # number of ReadExReq misses +system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 2018564 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 52016.377161 # average ReadReq miss latency +system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 1710971 # number of ReadReq hits +system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.152382 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 307593 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 126223 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 52001.810288 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::0 126223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 126223 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 52001.810288 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.910175 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 6563824500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 126223 # number of UpgradeReq misses +system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 126223 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 126223 # number of UpgradeReq misses system.l2c.UpgradeReq_mshr_miss_latency 5049666000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_misses 126223 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 430459 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits 430459 # number of Writeback hits +system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 430459 # number of Writeback hits +system.l2c.Writeback_hits::total 430459 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.avg_refs 4.436562 # Average number of references to valid blocks. @@ -384,31 +530,59 @@ system.l2c.blocked::no_targets 0 # nu system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 2323200 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency +system.l2c.demand_avg_miss_latency::total inf # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency -system.l2c.demand_hits 1710971 # number of demand (read+write) hits +system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits +system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.263528 # miss rate for demand accesses -system.l2c.demand_misses 612229 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses +system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses +system.l2c.demand_misses::0 612229 # number of demand (read+write) misses +system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::total 612229 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 2323200 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 52009.864773 # average overall miss latency +system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context +system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context +system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency +system.l2c.overall_avg_miss_latency::total inf # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 1710971 # number of overall hits +system.l2c.overall_hits::0 1710971 # number of overall hits +system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::total 1710971 # number of overall hits system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles -system.l2c.overall_miss_rate 0.263528 # miss rate for overall accesses -system.l2c.overall_misses 612229 # number of overall misses +system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses +system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses +system.l2c.overall_misses::0 612229 # number of overall misses +system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::total 612229 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |