Update refs.

--HG--
extra : convert_revision : 61d298fb0d9a66a76209a6bfcdb7c14f2efca947

1 files changed, 7 insertions, 7 deletions

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index a786f3201..d8d06877e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  66568                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 179344                       # Number of bytes of host memory used
-host_seconds                                     7.51                       # Real time elapsed on the host
-host_tick_rate                                 530155                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 542626                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 178896                       # Number of bytes of host memory used
+host_seconds                                     0.92                       # Real time elapsed on the host
+host_tick_rate                                4319791                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000004                       # Number of seconds simulated
@@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.overall_accesses             180775                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency  3743.121145                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  2743.121145                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                 180321                       # number of overall hits
 system.cpu.dcache.overall_miss_latency        1699377                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.002511                       # miss rate for overall accesses
@@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses             500000                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  3977.722084                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  2977.722084                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                 499597                       # number of overall hits
 system.cpu.icache.overall_miss_latency        1603022                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000806                       # miss rate for overall accesses
@@ -177,7 +177,7 @@ system.cpu.l2cache.no_allocate_misses               0                       # Nu
 system.cpu.l2cache.overall_accesses               857                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency  2853.441074                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency  1852.441074                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     0                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency       2445399                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses