Update reference outputs

--HG--
extra : convert_revision : 110a6c51cc1c562d115492b7360bfdbbded8eefd

8 files changed, 457 insertions, 21 deletions

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index d322a7a40..4f9d886f0 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -84,6 +84,7 @@ bus_id=0
 type=PhysicalMemory
 file=
 latency=1
+range=0:134217727
 
 [trace]
 bufsize=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
index 32bafae43..8f236d9cc 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
@@ -8,7 +8,7 @@ output_file=cout
 [system.physmem]
 type=PhysicalMemory
 file=
-// range not specified
+range=[0,134217727]
 latency=1
 
 [system]
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index e91773070..508b7b1e3 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1501109                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 146480                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
-host_tick_rate                                1499216                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1431500                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 146556                       # Number of bytes of host memory used
+host_seconds                                     0.35                       # Real time elapsed on the host
+host_tick_rate                                1429839                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 2fa2166aa..20413a23c 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 16 2006 13:05:10
-M5 started Wed Aug 16 14:41:54 2006
+M5 compiled Aug 18 2006 00:06:43
+M5 started Fri Aug 18 00:12:49 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
 Exiting @ tick 499999 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 5a34fde5e..0352c1b88 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -54,7 +54,7 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=workload
+children=dcache icache l2cache toL2Bus workload
 clock=1
 defer_registration=false
 function_trace=false
@@ -63,10 +63,128 @@ max_insts_all_threads=0
 max_insts_any_thread=500000
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.physmem
+mem=system.cpu.dcache
 system=system
 workload=system.cpu.workload
 
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
 [system.cpu.workload]
 type=EioProcess
 chkpt=
@@ -82,6 +200,7 @@ bus_id=0
 type=PhysicalMemory
 file=
 latency=1
+range=0:134217727
 
 [trace]
 bufsize=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
index 7032b9607..ba6875a7b 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
@@ -8,7 +8,7 @@ output_file=cout
 [system.physmem]
 type=PhysicalMemory
 file=
-// range not specified
+range=[0,134217727]
 latency=1
 
 [system]
@@ -20,6 +20,45 @@ mem_mode=atomic
 type=Bus
 bus_id=0
 
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
 [system.cpu.workload]
 type=EioProcess
 file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
@@ -33,7 +72,7 @@ max_insts_any_thread=500000
 max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
-mem=system.physmem
+mem=system.cpu.dcache
 system=system
 workload=system.cpu.workload
 clock=1
@@ -43,6 +82,88 @@ function_trace=false
 function_trace_start=0
 // simulate_stalls not specified
 
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
 [trace]
 flags=
 start=0
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index 51ee5923a..1de3f9376 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,14 +1,209 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 833953                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 146496                       # Number of bytes of host memory used
-host_seconds                                     0.60                       # Real time elapsed on the host
-host_tick_rate                                1134676                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 619761                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 158236                       # Number of bytes of host memory used
+host_seconds                                     0.81                       # Real time elapsed on the host
+host_tick_rate                                 845354                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
-sim_ticks                                      680774                       # Number of ticks simulated
+sim_ticks                                      682354                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses             124564                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency -2174448991928520960                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency            2                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits                 124315                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency   -541437798990201749504                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.001999                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                  249                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency          496                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001991                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses             248                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses             56744                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency -6113309131580347                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency            2                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits                 56412                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency  -2029618631684675072                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.005851                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses                 332                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency          278                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.002450                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses            139                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                 311.061962                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses              181308                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency -935400030330269184                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency            2                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                  180727                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency    -543467417621886402560                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.003204                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                   581                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency          774                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002134                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses              387                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses             181308                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency -935400030330269184                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits                 180727                       # number of overall hits
+system.cpu.dcache.overall_miss_latency   -543467417621886402560                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.003204                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses                  581                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency          774                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002134                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses             387                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                      0                       # number of replacements
+system.cpu.dcache.sampled_refs                    581                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse                347.118131                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                   180727                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                        0                       # number of writebacks
+system.cpu.icache.ReadReq_accesses             500000                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency -561967136127090496                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency            2                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits                 499597                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency   -226472755859217481728                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000806                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                  403                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency          806                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000806                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses             403                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                1239.694789                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses              500000                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency -561967136127090496                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency            2                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                  499597                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency    -226472755859217481728                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000806                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                   403                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency          806                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000806                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses              403                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses             500000                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency -561967136127090496                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency            2                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits                 499597                       # number of overall hits
+system.cpu.icache.overall_miss_latency   -226472755859217481728                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000806                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                  403                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency          806                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000806                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses             403                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                      0                       # number of replacements
+system.cpu.icache.sampled_refs                    403                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse                268.434590                       # Cycle average of tags in use
+system.cpu.icache.total_refs                   499597                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses               984                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency     1.605691                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency            1                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency          1580                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses                 984                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency          790                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.802846                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses            790                       # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses                984                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency     1.605691                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency            1                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency           1580                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses                  984                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency          790                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.802846                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses             790                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses               984                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency     1.605691                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency            1                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                     0                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency          1580                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses                 984                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency          790                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.802846                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses            790                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements                     0                       # number of replacements
+system.cpu.l2cache.sampled_refs                   984                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse               615.553879                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                                0                       # number of cpu cycles simulated
 system.cpu.num_insts                           500000                       # Number of instructions executed
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 2157d4af6..d400bd509 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 16 2006 17:47:32
-M5 started Wed Aug 16 18:40:03 2006
+M5 compiled Aug 18 2006 00:06:43
+M5 started Fri Aug 18 00:12:49 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
-Exiting @ tick 680774 because a thread reached the max instruction count
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+Exiting @ tick 682354 because a thread reached the max instruction count