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authorAli Saidi <saidi@eecs.umich.edu>2007-05-15 19:25:35 -0400
committerAli Saidi <saidi@eecs.umich.edu>2007-05-15 19:25:35 -0400
commitb85690e239616b703881b7734b0559f61f9eb75e (patch)
treef144325bc982177a8ff0d87ba87cc9e840bfb301 /tests/quick/20.eio-short/ref/alpha
parentc30e615689148c6e5ecd06e86069cba716dec5e0 (diff)
downloadgem5-b85690e239616b703881b7734b0559f61f9eb75e.tar.xz
update all the regresstion tests for release
--HG-- extra : convert_revision : 47e420b5b27e196a6e7a6424540923623bb3c4d2
Diffstat (limited to 'tests/quick/20.eio-short/ref/alpha')
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini1
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out1
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt8
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout6
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini11
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out11
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt100
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout8
8 files changed, 73 insertions, 73 deletions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 0c1dbb0ba..0431dd3db 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -39,6 +39,7 @@ system=system
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
index 5e988f3f9..73c363bc4 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
@@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.workload]
type=EioProcess
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index bc0a96087..7380e419f 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 689098 # Simulator instruction rate (inst/s)
-host_mem_usage 147724 # Number of bytes of host memory used
-host_seconds 0.73 # Real time elapsed on the host
-host_tick_rate 344128671 # Simulator tick rate (ticks/s)
+host_inst_rate 819297 # Simulator instruction rate (inst/s)
+host_mem_usage 147636 # Number of bytes of host memory used
+host_seconds 0.61 # Real time elapsed on the host
+host_tick_rate 409362131 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 47ee09274..c8bcb5723 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 21 2007 21:50:58
-M5 started Sat Apr 21 21:51:12 2007
-M5 executing on zamp.eecs.umich.edu
+M5 compiled May 14 2007 16:35:50
+M5 started Tue May 15 12:18:43 2007
+M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 249999500 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index eef4c0a1a..c05a66f9d 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -36,8 +36,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -75,8 +74,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=1000
lifo=false
max_miss_count=0
mshrs=10
@@ -114,8 +112,7 @@ block_size=64
compressed_bus=false
compression_latency=0
hash_delay=1
-hit_latency=1
-latency=1
+latency=10000
lifo=false
max_miss_count=0
mshrs=10
@@ -147,6 +144,7 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
@@ -162,6 +160,7 @@ system=system
[system.membus]
type=Bus
+block_size=64
bus_id=0
clock=1000
responder_set=false
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
index e897b733f..570ef7de8 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
@@ -20,6 +20,7 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.workload]
type=EioProcess
@@ -52,13 +53,14 @@ bus_id=0
clock=1000
width=64
responder_set=false
+block_size=64
[system.cpu.icache]
type=BaseCache
size=131072
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -89,14 +91,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.dcache]
type=BaseCache
size=262144
assoc=2
block_size=64
-latency=1
+latency=1000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -127,14 +128,13 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
[system.cpu.l2cache]
type=BaseCache
size=2097152
assoc=2
block_size=64
-latency=1
+latency=10000
mshrs=10
tgts_per_mshr=5
write_buffers=8
@@ -165,5 +165,4 @@ prefetch_policy=none
prefetch_cache_check_push=true
prefetch_use_cpu_id=true
prefetch_data_accesses_only=false
-hit_latency=1
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index a6caa5891..be87d3617 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 518674 # Simulator instruction rate (inst/s)
-host_mem_usage 153108 # Number of bytes of host memory used
-host_seconds 0.96 # Real time elapsed on the host
-host_tick_rate 355827019 # Simulator tick rate (ticks/s)
+host_inst_rate 392036 # Simulator instruction rate (inst/s)
+host_mem_usage 153128 # Number of bytes of host memory used
+host_seconds 1.28 # Real time elapsed on the host
+host_tick_rate 542334315 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
-sim_seconds 0.000343 # Number of seconds simulated
-sim_ticks 343161000 # Number of ticks simulated
+sim_seconds 0.000692 # Number of seconds simulated
+sim_ticks 691915000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3793.650794 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2793.650794 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1195000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4410000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 880000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 4095000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3600.719424 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2600.719424 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 14000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 500500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 1946000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 361500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 1807000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3734.581498 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 14000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1695500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 6356000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1241500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 5902000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3734.581498 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2734.581498 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 14000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 180321 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1695500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 6356000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
system.cpu.dcache.overall_misses 454 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1241500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 5902000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 291.533202 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 290.922203 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3739.454094 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2739.454094 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 14000 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13000 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1507000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 5642000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 1104000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 5239000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3739.454094 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 14000 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1507000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 5642000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1104000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 5239000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3739.454094 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2739.454094 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 14000 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 499597 # number of overall hits
-system.cpu.icache.overall_miss_latency 1507000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 5642000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_misses 403 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1104000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 5239000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 268.106513 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 267.665433 # Cycle average of tags in use
system.cpu.icache.total_refs 499597 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2736.872812 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1735.872812 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 2345500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 13000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 11141000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1487643 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 9427000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2736.872812 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2345500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 11141000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1487643 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 9427000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2736.872812 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1735.872812 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 13000 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2345500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 11141000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 857 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1487643 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 9427000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 559.642213 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 558.588875 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 343161000 # number of cpu cycles simulated
+system.cpu.numCycles 691915000 # number of cpu cycles simulated
system.cpu.num_insts 500000 # Number of instructions executed
system.cpu.num_refs 182203 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 8126fb0fb..83f216de6 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Apr 21 2007 21:50:58
-M5 started Sat Apr 21 21:51:14 2007
-M5 executing on zamp.eecs.umich.edu
+M5 compiled May 14 2007 16:35:50
+M5 started Tue May 15 12:18:44 2007
+M5 executing on zizzer.eecs.umich.edu
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 343161000 because a thread reached the max instruction count
+Exiting @ tick 691915000 because a thread reached the max instruction count