Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

--HG--
extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a

8 files changed, 60 insertions, 60 deletions

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 95cccfbf2..8fd60d527 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -64,7 +64,6 @@ max_insts_all_threads=0
 max_insts_any_thread=500000
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.physmem
 progress_interval=0
 simulate_stalls=false
 system=system
@@ -83,6 +82,9 @@ system=system
 [system.membus]
 type=Bus
 bus_id=0
+clock=1000
+responder_set=false
+width=64
 port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
index 1138f2dbe..fe1ff652e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out
@@ -19,6 +19,9 @@ mem_mode=atomic
 [system.membus]
 type=Bus
 bus_id=0
+clock=1000
+width=64
+responder_set=false
 
 [system.cpu.workload]
 type=EioProcess
@@ -34,7 +37,6 @@ max_insts_all_threads=0
 max_loads_any_thread=0
 max_loads_all_threads=0
 progress_interval=0
-mem=system.physmem
 system=system
 cpu_id=0
 workload=system.cpu.workload
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index bbc6e55b5..50d3a76c7 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1432213                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 147652                       # Number of bytes of host memory used
-host_seconds                                     0.35                       # Real time elapsed on the host
-host_tick_rate                                1430432                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1281059                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 147756                       # Number of bytes of host memory used
+host_seconds                                     0.39                       # Real time elapsed on the host
+host_tick_rate                                1279755                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000000                       # Number of seconds simulated
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index de2559c1c..18a78c936 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct  8 2006 14:00:39
-M5 started Sun Oct  8 14:00:58 2006
+M5 compiled Nov  3 2006 17:10:27
+M5 started Fri Nov  3 17:10:57 2006
 M5 executing on zizzer.eecs.umich.edu
 command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
 Exiting @ tick 499999 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index a3e69e540..ed47bcbe5 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -64,7 +64,6 @@ max_insts_all_threads=0
 max_insts_any_thread=500000
 max_loads_all_threads=0
 max_loads_any_thread=0
-mem=system.cpu.dcache
 progress_interval=0
 system=system
 workload=system.cpu.workload
@@ -78,7 +77,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -118,7 +116,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -158,7 +155,6 @@ assoc=2
 block_size=64
 compressed_bus=false
 compression_latency=0
-do_copy=false
 hash_delay=1
 hit_latency=1
 latency=1
@@ -195,6 +191,7 @@ mem_side=system.membus.port[1]
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
 
@@ -209,6 +206,7 @@ system=system
 type=Bus
 bus_id=0
 clock=1000
+responder_set=false
 width=64
 port=system.physmem.port system.cpu.l2cache.mem_side
 
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
index 3d64b3547..2dc04ff04 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
@@ -21,10 +21,42 @@ type=Bus
 bus_id=0
 clock=1000
 width=64
+responder_set=false
 
-[system.cpu.dcache]
+[system.cpu.workload]
+type=EioProcess
+file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+chkpt=
+output=cout
+system=system
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=500000
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
 type=BaseCache
-size=262144
+size=131072
 assoc=2
 block_size=64
 latency=1
@@ -32,7 +64,6 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
 protocol=null
 trace_addr=0
 hash_delay=1
@@ -61,40 +92,9 @@ prefetch_use_cpu_id=true
 prefetch_data_accesses_only=false
 hit_latency=1
 
-[system.cpu.workload]
-type=EioProcess
-file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
-chkpt=
-output=cout
-system=system
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=500000
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-mem=system.cpu.dcache
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-
-[system.cpu.icache]
+[system.cpu.dcache]
 type=BaseCache
-size=131072
+size=262144
 assoc=2
 block_size=64
 latency=1
@@ -102,7 +102,6 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
 protocol=null
 trace_addr=0
 hash_delay=1
@@ -141,7 +140,6 @@ mshrs=10
 tgts_per_mshr=5
 write_buffers=8
 prioritizeRequests=false
-do_copy=false
 protocol=null
 trace_addr=0
 hash_delay=1
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index a786f3201..d8d06877e 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  66568                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 179344                       # Number of bytes of host memory used
-host_seconds                                     7.51                       # Real time elapsed on the host
-host_tick_rate                                 530155                       # Simulator tick rate (ticks/s)
+host_inst_rate                                 542626                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 178896                       # Number of bytes of host memory used
+host_seconds                                     0.92                       # Real time elapsed on the host
+host_tick_rate                                4319791                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      500000                       # Number of instructions simulated
 sim_seconds                                  0.000004                       # Number of seconds simulated
@@ -53,7 +53,7 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.dcache.overall_accesses             180775                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_avg_miss_latency  3743.121145                       # average overall miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency  2743.121145                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_hits                 180321                       # number of overall hits
 system.cpu.dcache.overall_miss_latency        1699377                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_rate          0.002511                       # miss rate for overall accesses
@@ -115,7 +115,7 @@ system.cpu.icache.no_allocate_misses                0                       # Nu
 system.cpu.icache.overall_accesses             500000                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency  3977.722084                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency  2977.722084                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_hits                 499597                       # number of overall hits
 system.cpu.icache.overall_miss_latency        1603022                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000806                       # miss rate for overall accesses
@@ -177,7 +177,7 @@ system.cpu.l2cache.no_allocate_misses               0                       # Nu
 system.cpu.l2cache.overall_accesses               857                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_avg_miss_latency  2853.441074                       # average overall miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency  1852.441074                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_hits                     0                       # number of overall hits
 system.cpu.l2cache.overall_miss_latency       2445399                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 2f704cddb..787ea041d 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Oct 13 2006 16:07:10
-M5 started Fri Oct 13 16:09:55 2006
+M5 compiled Nov  3 2006 17:10:27
+M5 started Fri Nov  3 17:10:58 2006
 M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
 Exiting @ tick 3982316 because a thread reached the max instruction count