Stats: Update the stats.

--HG--
extra : convert_revision : 888b6e3bcd432a9318d4b8741a8b274c6f37f1a8

6 files changed, 97 insertions, 40 deletions

diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index a89c6ef26..9db92d8dc 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -11,12 +11,14 @@ physmem=system.physmem
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=workload
+children=dtb itb tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
+dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=500000
 max_loads_all_threads=0
@@ -25,15 +27,27 @@ phase=0
 progress_interval=0
 simulate_stalls=false
 system=system
+tracer=system.cpu.tracer
 width=1
 workload=system.cpu.workload
 dcache_port=system.membus.port[2]
 icache_port=system.membus.port[1]
 
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
 [system.cpu.workload]
 type=EioProcess
 chkpt=
-file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
 output=cout
 system=system
 
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
index 5747db5c2..a82f45966 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt
@@ -1,17 +1,34 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 188118                       # Simulator instruction rate (inst/s)
-host_seconds                                     2.66                       # Real time elapsed on the host
-host_tick_rate                               94046824                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2121237                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 171724                       # Number of bytes of host memory used
+host_seconds                                     0.24                       # Real time elapsed on the host
+host_tick_rate                             1058992833                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                      500000                       # Number of instructions simulated
+sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000250                       # Number of seconds simulated
-sim_ticks                                   249999500                       # Number of ticks simulated
+sim_ticks                                   250015500                       # Number of ticks simulated
+system.cpu.dtb.accesses                        180793                       # DTB accesses
+system.cpu.dtb.acv                                  0                       # DTB access violations
+system.cpu.dtb.hits                            180775                       # DTB hits
+system.cpu.dtb.misses                              18                       # DTB misses
+system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_hits                       124435                       # DTB read hits
+system.cpu.dtb.read_misses                          8                       # DTB read misses
+system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_hits                       56340                       # DTB write hits
+system.cpu.dtb.write_misses                        10                       # DTB write misses
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.itb.accesses                        500032                       # ITB accesses
+system.cpu.itb.acv                                  0                       # ITB acv
+system.cpu.itb.hits                            500019                       # ITB hits
+system.cpu.itb.misses                              13                       # ITB misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                           500000                       # number of cpu cycles simulated
-system.cpu.num_insts                           500000                       # Number of instructions executed
-system.cpu.num_refs                            182204                       # Number of memory references
+system.cpu.numCycles                           500032                       # number of cpu cycles simulated
+system.cpu.num_insts                           500001                       # Number of instructions executed
+system.cpu.num_refs                            182222                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
index 01450bbce..fee99ba99 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jun 10 2007 14:06:20
-M5 started Sun Jun 10 14:22:41 2007
-M5 executing on iceaxe
-command line: /Users/nate/build/outgoing/build/ALPHA_SE/m5.debug -d /Users/nate/build/outgoing/build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
+M5 compiled Aug 14 2007 17:58:14
+M5 started Tue Aug 14 17:58:32 2007
+M5 executing on nacho
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 249999500 because a thread reached the max instruction count
+Exiting @ tick 250015500 because a thread reached the max instruction count
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index aa9f81e79..f967fc1b8 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -11,12 +11,14 @@ physmem=system.physmem
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus tracer workload
+children=dcache dtb icache itb l2cache toL2Bus tracer workload
 clock=500
 cpu_id=0
 defer_registration=false
+dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=500000
 max_loads_all_threads=0
@@ -65,6 +67,10 @@ write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.port[1]
 
+[system.cpu.dtb]
+type=AlphaDTB
+size=64
+
 [system.cpu.icache]
 type=BaseCache
 addr_range=0:18446744073709551615
@@ -101,6 +107,10 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.itb]
+type=AlphaITB
+size=48
+
 [system.cpu.l2cache]
 type=BaseCache
 addr_range=0:18446744073709551615
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index d9f2463fd..62a259095 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,13 +1,13 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1380632                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 195668                       # Number of bytes of host memory used
-host_seconds                                     0.36                       # Real time elapsed on the host
-host_tick_rate                             1946559093                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1285667                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 179016                       # Number of bytes of host memory used
+host_seconds                                     0.39                       # Real time elapsed on the host
+host_tick_rate                             1812257249                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                      500000                       # Number of instructions simulated
+sim_insts                                      500001                       # Number of instructions simulated
 sim_seconds                                  0.000705                       # Number of seconds simulated
-sim_ticks                                   705470000                       # Number of ticks simulated
+sim_ticks                                   705490000                       # Number of ticks simulated
 system.cpu.dcache.ReadReq_accesses             124435                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
@@ -76,14 +76,26 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.sampled_refs                    454                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                289.564356                       # Cycle average of tags in use
+system.cpu.dcache.tagsinuse                289.561085                       # Cycle average of tags in use
 system.cpu.dcache.total_refs                   180321                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_accesses             500000                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb.accesses                        180793                       # DTB accesses
+system.cpu.dtb.acv                                  0                       # DTB access violations
+system.cpu.dtb.hits                            180775                       # DTB hits
+system.cpu.dtb.misses                              18                       # DTB misses
+system.cpu.dtb.read_accesses                   124443                       # DTB read accesses
+system.cpu.dtb.read_acv                             0                       # DTB read access violations
+system.cpu.dtb.read_hits                       124435                       # DTB read hits
+system.cpu.dtb.read_misses                          8                       # DTB read misses
+system.cpu.dtb.write_accesses                   56350                       # DTB write accesses
+system.cpu.dtb.write_acv                            0                       # DTB write access violations
+system.cpu.dtb.write_hits                       56340                       # DTB write hits
+system.cpu.dtb.write_misses                        10                       # DTB write misses
+system.cpu.icache.ReadReq_accesses             500020                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_avg_miss_latency        25000                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency        23000                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits                 499597                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits                 499617                       # number of ReadReq hits
 system.cpu.icache.ReadReq_miss_latency       10075000                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_rate          0.000806                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_misses                  403                       # number of ReadReq misses
@@ -92,16 +104,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate     0.000806                       # ms
 system.cpu.icache.ReadReq_mshr_misses             403                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                1239.694789                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                1239.744417                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses              500000                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses              500020                       # number of demand (read+write) accesses
 system.cpu.icache.demand_avg_miss_latency        25000                       # average overall miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                  499597                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits                  499617                       # number of demand (read+write) hits
 system.cpu.icache.demand_miss_latency        10075000                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_rate           0.000806                       # miss rate for demand accesses
 system.cpu.icache.demand_misses                   403                       # number of demand (read+write) misses
@@ -112,11 +124,11 @@ system.cpu.icache.demand_mshr_misses              403                       # nu
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses             500000                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses             500020                       # number of overall (read+write) accesses
 system.cpu.icache.overall_avg_miss_latency        25000                       # average overall miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency        23000                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits                 499597                       # number of overall hits
+system.cpu.icache.overall_hits                 499617                       # number of overall hits
 system.cpu.icache.overall_miss_latency       10075000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_rate          0.000806                       # miss rate for overall accesses
 system.cpu.icache.overall_misses                  403                       # number of overall misses
@@ -138,11 +150,15 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.icache.replacements                      0                       # number of replacements
 system.cpu.icache.sampled_refs                    403                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                266.632904                       # Cycle average of tags in use
-system.cpu.icache.total_refs                   499597                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                266.630553                       # Cycle average of tags in use
+system.cpu.icache.total_refs                   499617                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.itb.accesses                        500033                       # ITB accesses
+system.cpu.itb.acv                                  0                       # ITB acv
+system.cpu.itb.hits                            500020                       # ITB hits
+system.cpu.itb.misses                              13                       # ITB misses
 system.cpu.l2cache.ReadExReq_accesses             139                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_avg_miss_latency        22000                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        11000                       # average ReadExReq mshr miss latency
@@ -218,14 +234,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.sampled_refs                   546                       # Sample count of references to valid blocks.
 system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse               373.548776                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               373.545251                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       0                       # Total number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.writebacks                       0                       # number of writebacks
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                        705470000                       # number of cpu cycles simulated
-system.cpu.num_insts                           500000                       # Number of instructions executed
-system.cpu.num_refs                            182203                       # Number of memory references
+system.cpu.numCycles                        705490000                       # number of cpu cycles simulated
+system.cpu.num_insts                           500001                       # Number of instructions executed
+system.cpu.num_refs                            182222                       # Number of memory references
 system.cpu.workload.PROG:num_syscalls              18                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index c055fe4ae..0de340a66 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,9 +7,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 14 2007 13:54:58
-M5 started Tue Aug 14 13:57:54 2007
-M5 executing on zeep
+M5 compiled Aug 14 2007 17:58:14
+M5 started Tue Aug 14 17:58:16 2007
+M5 executing on nacho
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 705470000 because a thread reached the max instruction count
+Exiting @ tick 705490000 because a thread reached the max instruction count