summaryrefslogtreecommitdiff
path: root/tests/quick/20.eio-short
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-10-13 18:59:29 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-13 18:59:29 -0400
commitd83ccdfe5d2f22669fd65a90e2f8005cf1ffc5cc (patch)
tree6b1bf3497e68f5e3eebc217a01b506b4e62811c5 /tests/quick/20.eio-short
parentca4063ac00202b80e11312be62abbe4283cfae7b (diff)
downloadgem5-d83ccdfe5d2f22669fd65a90e2f8005cf1ffc5cc.tar.xz
Fix stats for new bus model
--HG-- extra : convert_revision : c081754c8eb8fa5b8e7336deb3fefb545789b8ac
Diffstat (limited to 'tests/quick/20.eio-short')
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini4
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out4
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt106
-rw-r--r--tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout8
4 files changed, 65 insertions, 57 deletions
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index 72ea32994..a3e69e540 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -194,6 +194,8 @@ mem_side=system.membus.port[1]
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
[system.cpu.workload]
@@ -206,6 +208,8 @@ system=system
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
port=system.physmem.port system.cpu.l2cache.mem_side
[system.physmem]
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
index 14eb07351..3d64b3547 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out
@@ -19,6 +19,8 @@ mem_mode=atomic
[system.membus]
type=Bus
bus_id=0
+clock=1000
+width=64
[system.cpu.dcache]
type=BaseCache
@@ -87,6 +89,8 @@ function_trace_start=0
[system.cpu.toL2Bus]
type=Bus
bus_id=0
+clock=1000
+width=64
[system.cpu.icache]
type=BaseCache
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
index ebc70e1f0..a786f3201 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt
@@ -1,31 +1,31 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 620088 # Simulator instruction rate (inst/s)
-host_mem_usage 159272 # Number of bytes of host memory used
-host_seconds 0.81 # Real time elapsed on the host
-host_tick_rate 845969 # Simulator tick rate (ticks/s)
+host_inst_rate 66568 # Simulator instruction rate (inst/s)
+host_mem_usage 179344 # Number of bytes of host memory used
+host_seconds 7.51 # Real time elapsed on the host
+host_tick_rate 530155 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
-sim_seconds 0.000001 # Number of seconds simulated
-sim_ticks 682488 # Number of ticks simulated
+sim_seconds 0.000004 # Number of seconds simulated
+sim_ticks 3982316 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 3670.641270 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2670.641270 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 945 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1156252 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 630 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 841252 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 3907.374101 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2907.374101 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 543125 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 404125 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency 3743.121145 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency
system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 1362 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency 1699377 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 908 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 1245377 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_miss_latency 3743.121145 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2743.121145 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits 180321 # number of overall hits
-system.cpu.dcache.overall_miss_latency 1362 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency 1699377 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
system.cpu.dcache.overall_misses 454 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 908 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 1245377 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 291.968600 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 227.376906 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 3977.722084 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2977.722084 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1209 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 1603022 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 806 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 1200022 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 3977.722084 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency
system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1209 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 1603022 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 806 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1200022 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_miss_latency 3977.722084 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2977.722084 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 499597 # number of overall hits
-system.cpu.icache.overall_miss_latency 1209 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 1603022 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
system.cpu.icache.overall_misses 403 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 806 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1200022 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -138,18 +138,18 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 268.423238 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 221.721362 # Cycle average of tags in use
system.cpu.icache.total_refs 499597 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 1714 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 2853.441074 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1852.441074 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 2445399 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1587542 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
@@ -161,29 +161,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 2853.441074 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 2445399 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 1587542 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_miss_latency 2853.441074 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1852.441074 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 2445399 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 857 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 1587542 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -200,12 +200,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 449.313470 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 0 # number of cpu cycles simulated
+system.cpu.numCycles 3982316 # number of cpu cycles simulated
system.cpu.num_insts 500000 # Number of instructions executed
system.cpu.num_refs 182203 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
index 076cf0a5a..2f704cddb 100644
--- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
+++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout
@@ -7,8 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Oct 8 2006 20:54:51
-M5 started Sun Oct 8 20:55:29 2006
+M5 compiled Oct 13 2006 16:07:10
+M5 started Fri Oct 13 16:09:55 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
-Exiting @ tick 682488 because a thread reached the max instruction count
+command line: build/ALPHA_SE/m5.debug -d build/ALPHA_SE/tests/debug/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+Exiting @ tick 3982316 because a thread reached the max instruction count