diff options
author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini | |
parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz |
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini')
-rw-r--r-- | tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 2d269877c..e871dcaff 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -68,7 +68,7 @@ cpu_side=system.cpu0.dcache_port mem_side=system.toL2Bus.port[2] [system.cpu0.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu0.icache] @@ -104,7 +104,7 @@ cpu_side=system.cpu0.icache_port mem_side=system.toL2Bus.port[1] [system.cpu0.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu0.tracer] @@ -179,7 +179,7 @@ cpu_side=system.cpu1.dcache_port mem_side=system.toL2Bus.port[4] [system.cpu1.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu1.icache] @@ -215,7 +215,7 @@ cpu_side=system.cpu1.icache_port mem_side=system.toL2Bus.port[3] [system.cpu1.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu1.tracer] @@ -290,7 +290,7 @@ cpu_side=system.cpu2.dcache_port mem_side=system.toL2Bus.port[6] [system.cpu2.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu2.icache] @@ -326,7 +326,7 @@ cpu_side=system.cpu2.icache_port mem_side=system.toL2Bus.port[5] [system.cpu2.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu2.tracer] @@ -401,7 +401,7 @@ cpu_side=system.cpu3.dcache_port mem_side=system.toL2Bus.port[8] [system.cpu3.dtb] -type=AlphaDTB +type=AlphaTLB size=64 [system.cpu3.icache] @@ -437,7 +437,7 @@ cpu_side=system.cpu3.icache_port mem_side=system.toL2Bus.port[7] [system.cpu3.itb] -type=AlphaITB +type=AlphaTLB size=48 [system.cpu3.tracer] |