diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:06:22 -0700 |
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committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:06:22 -0700 |
commit | 0f8b5afd7ad82fda05c3ad42cda4f9046992428d (patch) | |
tree | 794e8480ec916aa1b7da4c756f71ae1f6b1ffec7 /tests/quick/30.eio-mp/ref/alpha | |
parent | 0685ae7a2dbceaa2b9b264a57c9d5f82868e777e (diff) | |
download | gem5-0f8b5afd7ad82fda05c3ad42cda4f9046992428d.tar.xz |
tests: update reference config.ini files for previous cset
Rename 'responder_set' to 'use_default_range'.
Diffstat (limited to 'tests/quick/30.eio-mp/ref/alpha')
-rw-r--r-- | tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini | 4 | ||||
-rw-r--r-- | tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini index a6af5d880..0a51ea28f 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini @@ -494,7 +494,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.mem_side system.physmem.port[0] @@ -514,7 +514,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini index 29d69ea29..786aa64a8 100644 --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini @@ -482,7 +482,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.mem_side system.physmem.port[0] @@ -502,7 +502,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side |