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authorSteve Reinhardt <stever@gmail.com>2010-09-09 14:40:19 -0400
committerSteve Reinhardt <stever@gmail.com>2010-09-09 14:40:19 -0400
commit9e45ada1718b6df9310757fdc7cd78db4695516f (patch)
treec5cc9f2173f36e38addd8ca08e32ac010e56ef73 /tests/quick/30.eio-mp/ref
parent12497284949cb5418e6bc403723c034aee655666 (diff)
downloadgem5-9e45ada1718b6df9310757fdc7cd78db4695516f.tar.xz
stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches has changed, stats are affected for any non-ruby config with caches, even uniprocessor simple CPU.
Diffstat (limited to 'tests/quick/30.eio-mp/ref')
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini8
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr4
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout10
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt123
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini8
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout10
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt657
7 files changed, 390 insertions, 430 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 0a51ea28f..f95ff0355 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -115,7 +115,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
@@ -227,7 +227,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
@@ -339,7 +339,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
@@ -451,7 +451,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 1abe4a9de..75c83d350 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -5,3 +5,7 @@ hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 6a26281d0..97f8bb1e7 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:22:16
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
+M5 compiled Aug 26 2010 19:15:13
+M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
+M5 started Aug 26 2010 19:20:56
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 94c888d5d..390fcd6e5 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1651065 # Simulator instruction rate (inst/s)
-host_mem_usage 1114084 # Number of bytes of host memory used
-host_seconds 1.21 # Real time elapsed on the host
-host_tick_rate 206342663 # Simulator tick rate (ticks/s)
+host_inst_rate 3552670 # Simulator instruction rate (inst/s)
+host_mem_usage 1128260 # Number of bytes of host memory used
+host_seconds 0.56 # Real time elapsed on the host
+host_tick_rate 443935332 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2000004 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
@@ -13,9 +13,9 @@ system.cpu0.dcache.ReadReq_hits 124111 # nu
system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
@@ -27,10 +27,10 @@ system.cpu0.dcache.cache_copies 0 # nu
system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -44,10 +44,10 @@ system.cpu0.dcache.overall_accesses 180775 # nu
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180140 # number of overall hits
+system.cpu0.dcache.overall_hits 180312 # number of overall hits
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 635 # number of overall misses
+system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 463 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -153,9 +153,9 @@ system.cpu1.dcache.ReadReq_hits 124111 # nu
system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_hits 56201 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
@@ -167,10 +167,10 @@ system.cpu1.dcache.cache_copies 0 # nu
system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
+system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -184,10 +184,10 @@ system.cpu1.dcache.overall_accesses 180775 # nu
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 180140 # number of overall hits
+system.cpu1.dcache.overall_hits 180312 # number of overall hits
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 635 # number of overall misses
+system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
+system.cpu1.dcache.overall_misses 463 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -293,9 +293,9 @@ system.cpu2.dcache.ReadReq_hits 124111 # nu
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu2.dcache.WriteReq_hits 56201 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
@@ -307,10 +307,10 @@ system.cpu2.dcache.cache_copies 0 # nu
system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
+system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -324,10 +324,10 @@ system.cpu2.dcache.overall_accesses 180775 # nu
system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 180140 # number of overall hits
+system.cpu2.dcache.overall_hits 180312 # number of overall hits
system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu2.dcache.overall_misses 635 # number of overall misses
+system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
+system.cpu2.dcache.overall_misses 463 # number of overall misses
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -433,9 +433,9 @@ system.cpu3.dcache.ReadReq_hits 124111 # nu
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu3.dcache.WriteReq_hits 56201 # number of WriteReq hits
+system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
@@ -447,10 +447,10 @@ system.cpu3.dcache.cache_copies 0 # nu
system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
+system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
@@ -464,10 +464,10 @@ system.cpu3.dcache.overall_accesses 180775 # nu
system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 180140 # number of overall hits
+system.cpu3.dcache.overall_hits 180312 # number of overall hits
system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu3.dcache.overall_misses 635 # number of overall misses
+system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
+system.cpu3.dcache.overall_misses 463 # number of overall misses
system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
@@ -603,28 +603,13 @@ system.l2c.ReadReq_misses::1 718 # nu
system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses
system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 116 # number of Writeback hits
system.l2c.Writeback_hits::total 116 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
+system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -668,16 +653,16 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::3 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::4 0.000475 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::1 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::2 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::3 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::4 31.139534 # Average occupied blocks per context
+system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
@@ -717,10 +702,10 @@ system.l2c.overall_mshr_misses 0 # nu
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use
-system.l2c.total_refs 276 # Total number of references to valid blocks.
+system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use
+system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 786aa64a8..a23113a37 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -112,7 +112,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
@@ -221,7 +221,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
@@ -330,7 +330,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
@@ -439,7 +439,7 @@ type=ExeTracer
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index eb2ca2ce0..7e841f3da 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Jul 1 2010 14:37:40
-M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
-M5 started Jul 1 2010 14:37:50
-M5 executing on phenom
+M5 compiled Aug 26 2010 19:15:13
+M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
+M5 started Aug 26 2010 19:20:56
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -20,4 +20,4 @@ main dictionary has 1245 entries
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
->>>>Exiting @ tick 738387000 because a thread reached the max instruction count
+>>>>Exiting @ tick 728920000 because a thread reached the max instruction count
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 78c1b80b2..cc069962f 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,33 +1,33 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1240283 # Simulator instruction rate (inst/s)
-host_mem_usage 197852 # Number of bytes of host memory used
-host_seconds 1.61 # Real time elapsed on the host
-host_tick_rate 457858198 # Simulator tick rate (ticks/s)
+host_inst_rate 1077320 # Simulator instruction rate (inst/s)
+host_mem_usage 210756 # Number of bytes of host memory used
+host_seconds 1.86 # Real time elapsed on the host
+host_tick_rate 392590905 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1999941 # Number of instructions simulated
-sim_seconds 0.000738 # Number of seconds simulated
-sim_ticks 738387000 # Number of ticks simulated
+sim_insts 1999954 # Number of instructions simulated
+sim_seconds 0.000729 # Number of seconds simulated
+sim_ticks 728920000 # Number of ticks simulated
system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 7793000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency 7376000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
@@ -37,39 +37,39 @@ system.cpu0.dcache.blocked_cycles::no_mshrs 0 #
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_miss_latency 24189000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context
+system.cpu0.dcache.occ_%::0 0.534216 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context
system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180140 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 35212000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 635 # number of overall misses
+system.cpu0.dcache.overall_hits 180312 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 25578000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 463 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_miss_latency 24189000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements 61 # number of replacements
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 272.921161 # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use
system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 29 # number of writebacks
@@ -90,13 +90,13 @@ system.cpu0.dtb.write_acv 0 # DT
system.cpu0.dtb.write_hits 56340 # DTB write hits
system.cpu0.dtb.write_misses 10 # DTB write misses
system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency 23474000 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency 22085000 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
@@ -108,31 +108,31 @@ system.cpu0.icache.blocked_cycles::no_mshrs 0 #
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_miss_latency 50699.784017 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency 23474000 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency 22085000 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.421796 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 215.959580 # Average occupied blocks per context
+system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context
system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits 499557 # number of overall hits
-system.cpu0.icache.overall_miss_latency 23479000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency 23474000 # number of overall miss cycles
system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu0.icache.overall_misses 463 # number of overall misses
system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 22090000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency 22085000 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -140,7 +140,7 @@ system.cpu0.icache.overall_mshr_uncacheable_misses 0
system.cpu0.icache.replacements 152 # number of replacements
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 215.959580 # Cycle average of tags in use
+system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
@@ -162,135 +162,135 @@ system.cpu0.itb.write_acv 0 # DT
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.numCycles 1476774 # number of cpu cycles simulated
+system.cpu0.numCycles 1457840 # number of cpu cycles simulated
system.cpu0.num_insts 500001 # Number of instructions executed
system.cpu0.num_refs 182222 # Number of memory references
system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu1.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_hits 124109 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 56061.093248 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53061.093248 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_hits 56028 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 17435000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 16502000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_hits 56200 # number of WriteReq hits
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
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system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -298,8 +298,8 @@ system.cpu1.icache.overall_mshr_uncacheable_misses 0
system.cpu1.icache.replacements 152 # number of replacements
system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
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system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
system.cpu1.idle_fraction 0 # Percentage of idle cycles
@@ -307,9 +307,9 @@ system.cpu1.itb.data_accesses 0 # DT
system.cpu1.itb.data_acv 0 # DTB access violations
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system.cpu1.itb.read_acv 0 # DTB read access violations
@@ -320,135 +320,135 @@ system.cpu1.itb.write_acv 0 # DT
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system.cpu1.itb.write_misses 0 # DTB write misses
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system.cpu2.dcache.replacements 61 # number of replacements
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system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks 29 # number of writebacks
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system.cpu2.dtb.read_acv 0 # DTB read access violations
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system.cpu2.dtb.write_hits 56339 # DTB write hits
system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
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system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
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system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
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system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
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system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
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+system.cpu2.icache.overall_mshr_miss_latency 22094000 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
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system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -456,8 +456,8 @@ system.cpu2.icache.overall_mshr_uncacheable_misses 0
system.cpu2.icache.replacements 152 # number of replacements
system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks 0 # number of writebacks
system.cpu2.idle_fraction 0 # Percentage of idle cycles
@@ -465,9 +465,9 @@ system.cpu2.itb.data_accesses 0 # DT
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_hits 0 # DTB hits
system.cpu2.itb.data_misses 0 # DTB misses
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system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_hits 500000 # ITB hits
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system.cpu2.itb.fetch_misses 13 # ITB misses
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.read_acv 0 # DTB read access violations
@@ -478,14 +478,14 @@ system.cpu2.itb.write_acv 0 # DT
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu2.num_refs 182218 # Number of memory references
system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
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system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
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system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
@@ -493,120 +493,120 @@ system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000
system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
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system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.421779 # Average percentage of cache occupancy
-system.cpu3.icache.occ_blocks::0 215.951034 # Average occupied blocks per context
-system.cpu3.icache.overall_accesses 499994 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 50764.578834 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 47764.578834 # average overall mshr miss latency
+system.cpu3.icache.occ_%::0 0.422621 # Average percentage of cache occupancy
+system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context
+system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses
+system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 499531 # number of overall hits
-system.cpu3.icache.overall_miss_latency 23504000 # number of overall miss cycles
+system.cpu3.icache.overall_hits 499534 # number of overall hits
+system.cpu3.icache.overall_miss_latency 23492000 # number of overall miss cycles
system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
system.cpu3.icache.overall_misses 463 # number of overall misses
system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_miss_latency 22115000 # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency 22103000 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
@@ -614,8 +614,8 @@ system.cpu3.icache.overall_mshr_uncacheable_misses 0
system.cpu3.icache.replacements 152 # number of replacements
system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 215.951034 # Cycle average of tags in use
-system.cpu3.icache.total_refs 499531 # Total number of references to valid blocks.
+system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use
+system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks 0 # number of writebacks
system.cpu3.idle_fraction 0 # Percentage of idle cycles
@@ -623,9 +623,9 @@ system.cpu3.itb.data_accesses 0 # DT
system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_hits 0 # DTB hits
system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.fetch_accesses 500007 # ITB accesses
+system.cpu3.itb.fetch_accesses 500010 # ITB accesses
system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_hits 499994 # ITB hits
+system.cpu3.itb.fetch_hits 499997 # ITB hits
system.cpu3.itb.fetch_misses 13 # ITB misses
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.read_acv 0 # DTB read access violations
@@ -636,22 +636,22 @@ system.cpu3.itb.write_acv 0 # DT
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.numCycles 1476774 # number of cpu cycles simulated
-system.cpu3.num_insts 499975 # Number of instructions executed
-system.cpu3.num_refs 182214 # Number of memory references
+system.cpu3.numCycles 1457840 # number of cpu cycles simulated
+system.cpu3.num_insts 499978 # Number of instructions executed
+system.cpu3.num_refs 182216 # Number of memory references
system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 208035.971223 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 208035.971223 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 208035.971223 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 208035.971223 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 832143.884892 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40008.992806 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 28917000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_avg_miss_latency::0 208021.582734 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 208021.582734 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 208021.582734 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3 208021.582734 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 832086.330935 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 28915000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
@@ -662,7 +662,7 @@ system.l2c.ReadExReq_misses::1 139 # nu
system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 22245000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 22243000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses
@@ -674,18 +674,18 @@ system.l2c.ReadReq_accesses::1 787 # nu
system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 208032.033426 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 208032.033426 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 208032.033426 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3 208032.033426 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 832128.133705 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40008.008357 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_miss_latency::0 208043.175487 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 208043.175487 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2 208043.175487 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3 208043.175487 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 832172.701950 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872 # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0 69 # number of ReadReq hits
system.l2c.ReadReq_hits::1 69 # number of ReadReq hits
system.l2c.ReadReq_hits::2 69 # number of ReadReq hits
system.l2c.ReadReq_hits::3 69 # number of ReadReq hits
system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 149367000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency 149375000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses
@@ -696,49 +696,20 @@ system.l2c.ReadReq_misses::1 718 # nu
system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 114903000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency 114911000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::0 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::3 3.649301 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 14.597205 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 208005.813953 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 208005.813953 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 208005.813953 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3 208005.813953 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 832023.255814 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40001.453488 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 35777000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 27521000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 4 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 4 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2 4 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3 4 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 16 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 688 # number of UpgradeReq MSHR misses
system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 116 # number of Writeback hits
system.l2c.Writeback_hits::total 116 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
+system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
@@ -749,18 +720,18 @@ system.l2c.demand_accesses::1 926 # nu
system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 208032.672112 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 208032.672112 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 208032.672112 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 208032.672112 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 832130.688448 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency
+system.l2c.demand_avg_miss_latency::0 208039.673279 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 208039.673279 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 208039.673279 # average overall miss latency
+system.l2c.demand_avg_miss_latency::3 208039.673279 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 832158.693116 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
system.l2c.demand_hits::0 69 # number of demand (read+write) hits
system.l2c.demand_hits::1 69 # number of demand (read+write) hits
system.l2c.demand_hits::2 69 # number of demand (read+write) hits
system.l2c.demand_hits::3 69 # number of demand (read+write) hits
system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 178284000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency 178290000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses
@@ -772,7 +743,7 @@ system.l2c.demand_misses::2 857 # nu
system.l2c.demand_misses::3 857 # number of demand (read+write) misses
system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 137148000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 137154000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 3.701944 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 3.701944 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 3.701944 # mshr miss rate for demand accesses
@@ -782,34 +753,34 @@ system.l2c.demand_mshr_misses 3428 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.005650 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.005650 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.005650 # Average percentage of cache occupancy
-system.l2c.occ_%::3 0.005650 # Average percentage of cache occupancy
-system.l2c.occ_%::4 0.000464 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 370.305065 # Average occupied blocks per context
-system.l2c.occ_blocks::1 370.297695 # Average occupied blocks per context
-system.l2c.occ_blocks::2 370.294638 # Average occupied blocks per context
-system.l2c.occ_blocks::3 370.290796 # Average occupied blocks per context
-system.l2c.occ_blocks::4 30.383926 # Average occupied blocks per context
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+system.l2c.occ_%::2 0.007347 # Average percentage of cache occupancy
+system.l2c.occ_%::3 0.007347 # Average percentage of cache occupancy
+system.l2c.occ_%::4 0.000263 # Average percentage of cache occupancy
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+system.l2c.occ_blocks::1 481.519672 # Average occupied blocks per context
+system.l2c.occ_blocks::2 481.512310 # Average occupied blocks per context
+system.l2c.occ_blocks::3 481.507730 # Average occupied blocks per context
+system.l2c.occ_blocks::4 17.228456 # Average occupied blocks per context
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 208032.672112 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 208032.672112 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 208032.672112 # average overall miss latency
-system.l2c.overall_avg_miss_latency::3 208032.672112 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 832130.688448 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40008.168028 # average overall mshr miss latency
+system.l2c.overall_avg_miss_latency::0 208039.673279 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 208039.673279 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 208039.673279 # average overall miss latency
+system.l2c.overall_avg_miss_latency::3 208039.673279 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 832158.693116 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits::0 69 # number of overall hits
system.l2c.overall_hits::1 69 # number of overall hits
system.l2c.overall_hits::2 69 # number of overall hits
system.l2c.overall_hits::3 69 # number of overall hits
system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.overall_miss_latency 178284000 # number of overall miss cycles
+system.l2c.overall_miss_latency 178290000 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
@@ -821,7 +792,7 @@ system.l2c.overall_misses::2 857 # nu
system.l2c.overall_misses::3 857 # number of overall misses
system.l2c.overall_misses::total 3428 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses
@@ -831,10 +802,10 @@ system.l2c.overall_mshr_misses 3428 # nu
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use
-system.l2c.total_refs 276 # Total number of references to valid blocks.
+system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use
+system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks