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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:24 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:24 -0600
commitb4b6a2338aab3224baec7add32da31300f6e4082 (patch)
treef2e9cbda3578c8ddc1fca5f419a8e3a0ed2d89a1 /tests/quick/30.eio-mp/ref
parentcdacbe734a9e6e0f20e0a37ef694995373b83f66 (diff)
downloadgem5-b4b6a2338aab3224baec7add32da31300f6e4082.tar.xz
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
Diffstat (limited to 'tests/quick/30.eio-mp/ref')
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr20
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout23
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt712
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr20
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout23
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt812
6 files changed, 32 insertions, 1578 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 75c83d350..d8859d544 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -1,11 +1,9 @@
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+Traceback (most recent call last):
+ File "<string>", line 1, in <module>
+ File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main
+ exec filecode in scope
+ File "tests/run.py", line 78, in <module>
+ execfile(joinpath(tests_root, category, name, 'test.py'))
+ File "tests/quick/30.eio-mp/test.py", line 29, in <module>
+ process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
+NameError: name 'EioProcess' is not defined
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 97f8bb1e7..4794eacba 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simout
+Redirecting stderr to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,19 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 26 2010 19:15:13
-M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
-M5 started Aug 26 2010 19:20:56
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 250015500 because a thread reached the max instruction count
+M5 compiled Nov 2 2010 21:30:55
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov 2 2010 21:31:02
+M5 executing on aus-bc2-b15
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 390fcd6e5..e69de29bb 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,712 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 3552670 # Simulator instruction rate (inst/s)
-host_mem_usage 1128260 # Number of bytes of host memory used
-host_seconds 0.56 # Real time elapsed on the host
-host_tick_rate 443935332 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 2000004 # Number of instructions simulated
-sim_seconds 0.000250 # Number of seconds simulated
-sim_ticks 250015500 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180312 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 463 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 29 # number of writebacks
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_hits 124435 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_hits 56340 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
-system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 499556 # number of overall hits
-system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 463 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.fetch_accesses 500032 # ITB accesses
-system.cpu0.itb.fetch_acv 0 # ITB acv
-system.cpu0.itb.fetch_hits 500019 # ITB hits
-system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.numCycles 500032 # number of cpu cycles simulated
-system.cpu0.num_insts 500001 # Number of instructions executed
-system.cpu0.num_refs 182222 # Number of memory references
-system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 180312 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 180312 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 463 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements 61 # number of replacements
-system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 29 # number of writebacks
-system.cpu1.dtb.data_accesses 180793 # DTB accesses
-system.cpu1.dtb.data_acv 0 # DTB access violations
-system.cpu1.dtb.data_hits 180775 # DTB hits
-system.cpu1.dtb.data_misses 18 # DTB misses
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_hits 124435 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.write_accesses 56350 # DTB write accesses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_hits 56340 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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-system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
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-system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 499556 # number of overall hits
-system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 463 # number of overall misses
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-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements 152 # number of replacements
-system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks.
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-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.fetch_accesses 500032 # ITB accesses
-system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_hits 500019 # ITB hits
-system.cpu1.itb.fetch_misses 13 # ITB misses
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.numCycles 500032 # number of cpu cycles simulated
-system.cpu1.num_insts 500001 # Number of instructions executed
-system.cpu1.num_refs 182222 # Number of memory references
-system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
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-system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 180312 # number of demand (read+write) hits
-system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
-system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 180312 # number of overall hits
-system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.overall_misses 463 # number of overall misses
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-system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
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-system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.dcache.replacements 61 # number of replacements
-system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
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-system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use
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-system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.dtb.data_accesses 180793 # DTB accesses
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-system.cpu2.dtb.fetch_hits 0 # ITB hits
-system.cpu2.dtb.fetch_misses 0 # ITB misses
-system.cpu2.dtb.read_accesses 124443 # DTB read accesses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_hits 124435 # DTB read hits
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-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_hits 56340 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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-system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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-system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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-system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
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-system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.icache.overall_hits 499556 # number of overall hits
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-system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
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-system.cpu2.icache.replacements 152 # number of replacements
-system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
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-system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks.
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-system.cpu2.itb.data_misses 0 # DTB misses
-system.cpu2.itb.fetch_accesses 500032 # ITB accesses
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-system.cpu2.numCycles 500032 # number of cpu cycles simulated
-system.cpu2.num_insts 500001 # Number of instructions executed
-system.cpu2.num_refs 182222 # Number of memory references
-system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
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-system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
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-system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 180312 # number of demand (read+write) hits
-system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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-system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
-system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 180312 # number of overall hits
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-system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.overall_misses 463 # number of overall misses
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-system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
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-system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.dcache.replacements 61 # number of replacements
-system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.writebacks 29 # number of writebacks
-system.cpu3.dtb.data_accesses 180793 # DTB accesses
-system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_hits 180775 # DTB hits
-system.cpu3.dtb.data_misses 18 # DTB misses
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-system.cpu3.dtb.fetch_hits 0 # ITB hits
-system.cpu3.dtb.fetch_misses 0 # ITB misses
-system.cpu3.dtb.read_accesses 124443 # DTB read accesses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_hits 124435 # DTB read hits
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-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_hits 56340 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits
-system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks.
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-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
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-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits
-system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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-system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
-system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
-system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 499556 # number of overall hits
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-system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_misses 463 # number of overall misses
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-system.cpu3.icache.replacements 152 # number of replacements
-system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use
-system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks.
-system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.itb.data_accesses 0 # DTB accesses
-system.cpu3.itb.data_acv 0 # DTB access violations
-system.cpu3.itb.data_hits 0 # DTB hits
-system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.fetch_accesses 500032 # ITB accesses
-system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_hits 500019 # ITB hits
-system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.read_acv 0 # DTB read access violations
-system.cpu3.itb.read_hits 0 # DTB read hits
-system.cpu3.itb.read_misses 0 # DTB read misses
-system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.write_acv 0 # DTB write access violations
-system.cpu3.itb.write_hits 0 # DTB write hits
-system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.numCycles 500032 # number of cpu cycles simulated
-system.cpu3.num_insts 500001 # Number of instructions executed
-system.cpu3.num_refs 182222 # Number of memory references
-system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
-system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::3 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 116 # number of Writeback hits
-system.l2c.Writeback_hits::total 116 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 69 # number of demand (read+write) hits
-system.l2c.demand_hits::1 69 # number of demand (read+write) hits
-system.l2c.demand_hits::2 69 # number of demand (read+write) hits
-system.l2c.demand_hits::3 69 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses
-system.l2c.demand_misses::0 857 # number of demand (read+write) misses
-system.l2c.demand_misses::1 857 # number of demand (read+write) misses
-system.l2c.demand_misses::2 857 # number of demand (read+write) misses
-system.l2c.demand_misses::3 857 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context
-system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context
-system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 69 # number of overall hits
-system.l2c.overall_hits::1 69 # number of overall hits
-system.l2c.overall_hits::2 69 # number of overall hits
-system.l2c.overall_hits::3 69 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses
-system.l2c.overall_misses::0 857 # number of overall misses
-system.l2c.overall_misses::1 857 # number of overall misses
-system.l2c.overall_misses::2 857 # number of overall misses
-system.l2c.overall_misses::3 857 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use
-system.l2c.total_refs 332 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 0 # number of writebacks
-
----------- End Simulation Statistics ----------
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 75c83d350..d8859d544 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -1,11 +1,9 @@
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-hack: be nice to actually delete the event here
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+Traceback (most recent call last):
+ File "<string>", line 1, in <module>
+ File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main
+ exec filecode in scope
+ File "tests/run.py", line 78, in <module>
+ execfile(joinpath(tests_root, category, name, 'test.py'))
+ File "tests/quick/30.eio-mp/test.py", line 29, in <module>
+ process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz'))
+NameError: name 'EioProcess' is not defined
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index 7e841f3da..538553f99 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp/simout
+Redirecting stderr to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,19 +7,8 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Aug 26 2010 19:15:13
-M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
-M5 started Aug 26 2010 19:20:56
-M5 executing on zizzer
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp
-Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-main dictionary has 1245 entries
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
-49508 bytes wasted
->>>>Exiting @ tick 728920000 because a thread reached the max instruction count
+M5 compiled Nov 2 2010 21:30:55
+M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip
+M5 started Nov 2 2010 21:33:05
+M5 executing on aus-bc2-b15
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index cc069962f..e69de29bb 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,812 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate 1077320 # Simulator instruction rate (inst/s)
-host_mem_usage 210756 # Number of bytes of host memory used
-host_seconds 1.86 # Real time elapsed on the host
-host_tick_rate 392590905 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1999954 # Number of instructions simulated
-sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 728920000 # Number of ticks simulated
-system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 7793000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 7376000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 24189000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.534216 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180312 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 25578000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 463 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 24189000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements 61 # number of replacements
-system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 29 # number of writebacks
-system.cpu0.dtb.data_accesses 180793 # DTB accesses
-system.cpu0.dtb.data_acv 0 # DTB access violations
-system.cpu0.dtb.data_hits 180775 # DTB hits
-system.cpu0.dtb.data_misses 18 # DTB misses
-system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.fetch_acv 0 # ITB acv
-system.cpu0.dtb.fetch_hits 0 # ITB hits
-system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.read_accesses 124443 # DTB read accesses
-system.cpu0.dtb.read_acv 0 # DTB read access violations
-system.cpu0.dtb.read_hits 124435 # DTB read hits
-system.cpu0.dtb.read_misses 8 # DTB read misses
-system.cpu0.dtb.write_accesses 56350 # DTB write accesses
-system.cpu0.dtb.write_acv 0 # DTB write access violations
-system.cpu0.dtb.write_hits 56340 # DTB write hits
-system.cpu0.dtb.write_misses 10 # DTB write misses
-system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 23474000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 22085000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 50699.784017 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 23474000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 22085000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context
-system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 499557 # number of overall hits
-system.cpu0.icache.overall_miss_latency 23474000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu0.icache.overall_misses 463 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 22085000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use
-system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idle_fraction 0 # Percentage of idle cycles
-system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.itb.data_acv 0 # DTB access violations
-system.cpu0.itb.data_hits 0 # DTB hits
-system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.fetch_accesses 500033 # ITB accesses
-system.cpu0.itb.fetch_acv 0 # ITB acv
-system.cpu0.itb.fetch_hits 500020 # ITB hits
-system.cpu0.itb.fetch_misses 13 # ITB misses
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.read_acv 0 # DTB read access violations
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.write_acv 0 # DTB write access violations
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu0.numCycles 1457840 # number of cpu cycles simulated
-system.cpu0.num_insts 500001 # Number of instructions executed
-system.cpu0.num_refs 182222 # Number of memory references
-system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_hits 56200 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 7803000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 7386000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses 180774 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 180311 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.534204 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 273.512548 # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses 180774 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 180311 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 25588000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 463 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements 61 # number of replacements
-system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 273.512548 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 29 # number of writebacks
-system.cpu1.dtb.data_accesses 180792 # DTB accesses
-system.cpu1.dtb.data_acv 0 # DTB access violations
-system.cpu1.dtb.data_hits 180774 # DTB hits
-system.cpu1.dtb.data_misses 18 # DTB misses
-system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.fetch_acv 0 # ITB acv
-system.cpu1.dtb.fetch_hits 0 # ITB hits
-system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.read_accesses 124443 # DTB read accesses
-system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_hits 124435 # DTB read hits
-system.cpu1.dtb.read_misses 8 # DTB read misses
-system.cpu1.dtb.write_accesses 56349 # DTB write accesses
-system.cpu1.dtb.write_acv 0 # DTB write access violations
-system.cpu1.dtb.write_hits 56339 # DTB write hits
-system.cpu1.dtb.write_misses 10 # DTB write misses
-system.cpu1.icache.ReadReq_accesses 500012 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 50697.624190 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47697.624190 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits 499549 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 23473000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 22084000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks.
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-system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses 500012 # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 50697.624190 # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency
-system.cpu1.icache.demand_hits 499549 # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency 23473000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 22084000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu1.icache.fast_writes 0 # number of fast writes performed
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.422630 # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0 216.386658 # Average occupied blocks per context
-system.cpu1.icache.overall_accesses 500012 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 50697.624190 # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits 499549 # number of overall hits
-system.cpu1.icache.overall_miss_latency 23473000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu1.icache.overall_misses 463 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency 22084000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements 152 # number of replacements
-system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 216.386658 # Cycle average of tags in use
-system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0 # Percentage of idle cycles
-system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.itb.data_acv 0 # DTB access violations
-system.cpu1.itb.data_hits 0 # DTB hits
-system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.fetch_accesses 500025 # ITB accesses
-system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_hits 500012 # ITB hits
-system.cpu1.itb.fetch_misses 13 # ITB misses
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.read_acv 0 # DTB read access violations
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.write_acv 0 # DTB write access violations
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu1.numCycles 1457840 # number of cpu cycles simulated
-system.cpu1.num_insts 499993 # Number of instructions executed
-system.cpu1.num_refs 182221 # Number of memory references
-system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_hits 124109 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_hits 56200 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
-system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks.
-system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.demand_accesses 180772 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_avg_miss_latency 55272.138229 # average overall miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 180309 # number of demand (read+write) hits
-system.cpu2.dcache.demand_miss_latency 25591000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_miss_latency 24202000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.fast_writes 0 # number of fast writes performed
-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0 0.534196 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_blocks::0 273.508588 # Average occupied blocks per context
-system.cpu2.dcache.overall_accesses 180772 # number of overall (read+write) accesses
-system.cpu2.dcache.overall_avg_miss_latency 55272.138229 # average overall miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 180309 # number of overall hits
-system.cpu2.dcache.overall_miss_latency 25591000 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu2.dcache.overall_misses 463 # number of overall misses
-system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_miss_latency 24202000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.dcache.replacements 61 # number of replacements
-system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.dcache.tagsinuse 273.508588 # Cycle average of tags in use
-system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks.
-system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.writebacks 29 # number of writebacks
-system.cpu2.dtb.data_accesses 180790 # DTB accesses
-system.cpu2.dtb.data_acv 0 # DTB access violations
-system.cpu2.dtb.data_hits 180772 # DTB hits
-system.cpu2.dtb.data_misses 18 # DTB misses
-system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.fetch_acv 0 # ITB acv
-system.cpu2.dtb.fetch_hits 0 # ITB hits
-system.cpu2.dtb.fetch_misses 0 # ITB misses
-system.cpu2.dtb.read_accesses 124441 # DTB read accesses
-system.cpu2.dtb.read_acv 0 # DTB read access violations
-system.cpu2.dtb.read_hits 124433 # DTB read hits
-system.cpu2.dtb.read_misses 8 # DTB read misses
-system.cpu2.dtb.write_accesses 56349 # DTB write accesses
-system.cpu2.dtb.write_acv 0 # DTB write access violations
-system.cpu2.dtb.write_hits 56339 # DTB write hits
-system.cpu2.dtb.write_misses 10 # DTB write misses
-system.cpu2.icache.ReadReq_accesses 500001 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_avg_miss_latency 50719.222462 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47719.222462 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_hits 499538 # number of ReadReq hits
-system.cpu2.icache.ReadReq_miss_latency 23483000 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu2.icache.ReadReq_mshr_miss_latency 22094000 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu2.icache.avg_refs 1078.915767 # Average number of references to valid blocks.
-system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.demand_accesses 500001 # number of demand (read+write) accesses
-system.cpu2.icache.demand_avg_miss_latency 50719.222462 # average overall miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
-system.cpu2.icache.demand_hits 499538 # number of demand (read+write) hits
-system.cpu2.icache.demand_miss_latency 23483000 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_miss_latency 22094000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu2.icache.fast_writes 0 # number of fast writes performed
-system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0 0.422624 # Average percentage of cache occupancy
-system.cpu2.icache.occ_blocks::0 216.383557 # Average occupied blocks per context
-system.cpu2.icache.overall_accesses 500001 # number of overall (read+write) accesses
-system.cpu2.icache.overall_avg_miss_latency 50719.222462 # average overall miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.icache.overall_hits 499538 # number of overall hits
-system.cpu2.icache.overall_miss_latency 23483000 # number of overall miss cycles
-system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu2.icache.overall_misses 463 # number of overall misses
-system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_miss_latency 22094000 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.icache.replacements 152 # number of replacements
-system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.icache.tagsinuse 216.383557 # Cycle average of tags in use
-system.cpu2.icache.total_refs 499538 # Total number of references to valid blocks.
-system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.writebacks 0 # number of writebacks
-system.cpu2.idle_fraction 0 # Percentage of idle cycles
-system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.itb.data_acv 0 # DTB access violations
-system.cpu2.itb.data_hits 0 # DTB hits
-system.cpu2.itb.data_misses 0 # DTB misses
-system.cpu2.itb.fetch_accesses 500014 # ITB accesses
-system.cpu2.itb.fetch_acv 0 # ITB acv
-system.cpu2.itb.fetch_hits 500001 # ITB hits
-system.cpu2.itb.fetch_misses 13 # ITB misses
-system.cpu2.itb.read_accesses 0 # DTB read accesses
-system.cpu2.itb.read_acv 0 # DTB read access violations
-system.cpu2.itb.read_hits 0 # DTB read hits
-system.cpu2.itb.read_misses 0 # DTB read misses
-system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.write_acv 0 # DTB write access violations
-system.cpu2.itb.write_hits 0 # DTB write hits
-system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu2.numCycles 1457840 # number of cpu cycles simulated
-system.cpu2.num_insts 499982 # Number of instructions executed
-system.cpu2.num_refs 182218 # Number of memory references
-system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
-system.cpu3.dcache.ReadReq_accesses 124431 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_hits 124107 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_hits 56200 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
-system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks.
-system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.demand_accesses 180770 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 180307 # number of demand (read+write) hits
-system.cpu3.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
-system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses
-system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.fast_writes 0 # number of fast writes performed
-system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0 0.534191 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_blocks::0 273.505617 # Average occupied blocks per context
-system.cpu3.dcache.overall_accesses 180770 # number of overall (read+write) accesses
-system.cpu3.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 180307 # number of overall hits
-system.cpu3.dcache.overall_miss_latency 25588000 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
-system.cpu3.dcache.overall_misses 463 # number of overall misses
-system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.dcache.replacements 61 # number of replacements
-system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.dcache.tagsinuse 273.505617 # Cycle average of tags in use
-system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks.
-system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.writebacks 29 # number of writebacks
-system.cpu3.dtb.data_accesses 180788 # DTB accesses
-system.cpu3.dtb.data_acv 0 # DTB access violations
-system.cpu3.dtb.data_hits 180770 # DTB hits
-system.cpu3.dtb.data_misses 18 # DTB misses
-system.cpu3.dtb.fetch_accesses 0 # ITB accesses
-system.cpu3.dtb.fetch_acv 0 # ITB acv
-system.cpu3.dtb.fetch_hits 0 # ITB hits
-system.cpu3.dtb.fetch_misses 0 # ITB misses
-system.cpu3.dtb.read_accesses 124439 # DTB read accesses
-system.cpu3.dtb.read_acv 0 # DTB read access violations
-system.cpu3.dtb.read_hits 124431 # DTB read hits
-system.cpu3.dtb.read_misses 8 # DTB read misses
-system.cpu3.dtb.write_accesses 56349 # DTB write accesses
-system.cpu3.dtb.write_acv 0 # DTB write access violations
-system.cpu3.dtb.write_hits 56339 # DTB write hits
-system.cpu3.dtb.write_misses 10 # DTB write misses
-system.cpu3.icache.ReadReq_accesses 499997 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_avg_miss_latency 50738.660907 # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47738.660907 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_hits 499534 # number of ReadReq hits
-system.cpu3.icache.ReadReq_miss_latency 23492000 # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu3.icache.ReadReq_mshr_miss_latency 22103000 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
-system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks.
-system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.icache.cache_copies 0 # number of cache copies performed
-system.cpu3.icache.demand_accesses 499997 # number of demand (read+write) accesses
-system.cpu3.icache.demand_avg_miss_latency 50738.660907 # average overall miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
-system.cpu3.icache.demand_hits 499534 # number of demand (read+write) hits
-system.cpu3.icache.demand_miss_latency 23492000 # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
-system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses
-system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_miss_latency 22103000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
-system.cpu3.icache.fast_writes 0 # number of fast writes performed
-system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.422621 # Average percentage of cache occupancy
-system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context
-system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses
-system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.icache.overall_hits 499534 # number of overall hits
-system.cpu3.icache.overall_miss_latency 23492000 # number of overall miss cycles
-system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses
-system.cpu3.icache.overall_misses 463 # number of overall misses
-system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_miss_latency 22103000 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu3.icache.replacements 152 # number of replacements
-system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks.
-system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use
-system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks.
-system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.writebacks 0 # number of writebacks
-system.cpu3.idle_fraction 0 # Percentage of idle cycles
-system.cpu3.itb.data_accesses 0 # DTB accesses
-system.cpu3.itb.data_acv 0 # DTB access violations
-system.cpu3.itb.data_hits 0 # DTB hits
-system.cpu3.itb.data_misses 0 # DTB misses
-system.cpu3.itb.fetch_accesses 500010 # ITB accesses
-system.cpu3.itb.fetch_acv 0 # ITB acv
-system.cpu3.itb.fetch_hits 499997 # ITB hits
-system.cpu3.itb.fetch_misses 13 # ITB misses
-system.cpu3.itb.read_accesses 0 # DTB read accesses
-system.cpu3.itb.read_acv 0 # DTB read access violations
-system.cpu3.itb.read_hits 0 # DTB read hits
-system.cpu3.itb.read_misses 0 # DTB read misses
-system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.write_acv 0 # DTB write access violations
-system.cpu3.itb.write_hits 0 # DTB write hits
-system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu3.numCycles 1457840 # number of cpu cycles simulated
-system.cpu3.num_insts 499978 # Number of instructions executed
-system.cpu3.num_refs 182216 # Number of memory references
-system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
-system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 208021.582734 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 832086.330935 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 28915000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 22243000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3 4 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 16 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3 208043.175487 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 832172.701950 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872 # average ReadReq mshr miss latency
-system.l2c.ReadReq_hits::0 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::3 69 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 276 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 149375000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 114911000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 3.649301 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 3.649301 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2 3.649301 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3 3.649301 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 14.597205 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses
-system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 116 # number of Writeback hits
-system.l2c.Writeback_hits::total 116 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 208039.673279 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 208039.673279 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 208039.673279 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 208039.673279 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 832158.693116 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
-system.l2c.demand_hits::0 69 # number of demand (read+write) hits
-system.l2c.demand_hits::1 69 # number of demand (read+write) hits
-system.l2c.demand_hits::2 69 # number of demand (read+write) hits
-system.l2c.demand_hits::3 69 # number of demand (read+write) hits
-system.l2c.demand_hits::total 276 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 178290000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses
-system.l2c.demand_misses::0 857 # number of demand (read+write) misses
-system.l2c.demand_misses::1 857 # number of demand (read+write) misses
-system.l2c.demand_misses::2 857 # number of demand (read+write) misses
-system.l2c.demand_misses::3 857 # number of demand (read+write) misses
-system.l2c.demand_misses::total 3428 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 137154000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 3.701944 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 3.701944 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 3.701944 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 3.701944 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 14.807775 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.007348 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.007347 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.007347 # Average percentage of cache occupancy
-system.l2c.occ_%::3 0.007347 # Average percentage of cache occupancy
-system.l2c.occ_%::4 0.000263 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 481.530369 # Average occupied blocks per context
-system.l2c.occ_blocks::1 481.519672 # Average occupied blocks per context
-system.l2c.occ_blocks::2 481.512310 # Average occupied blocks per context
-system.l2c.occ_blocks::3 481.507730 # Average occupied blocks per context
-system.l2c.occ_blocks::4 17.228456 # Average occupied blocks per context
-system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 208039.673279 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 208039.673279 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 208039.673279 # average overall miss latency
-system.l2c.overall_avg_miss_latency::3 208039.673279 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 832158.693116 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 69 # number of overall hits
-system.l2c.overall_hits::1 69 # number of overall hits
-system.l2c.overall_hits::2 69 # number of overall hits
-system.l2c.overall_hits::3 69 # number of overall hits
-system.l2c.overall_hits::total 276 # number of overall hits
-system.l2c.overall_miss_latency 178290000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses
-system.l2c.overall_misses::0 857 # number of overall misses
-system.l2c.overall_misses::1 857 # number of overall misses
-system.l2c.overall_misses::2 857 # number of overall misses
-system.l2c.overall_misses::3 857 # number of overall misses
-system.l2c.overall_misses::total 3428 # number of overall misses
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 3.701944 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 14.807775 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use
-system.l2c.total_refs 332 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 0 # number of writebacks
-
----------- End Simulation Statistics ----------