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authorNathan Binkert <nate@binkert.org>2011-04-19 18:45:23 -0700
committerNathan Binkert <nate@binkert.org>2011-04-19 18:45:23 -0700
commit8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b (patch)
tree8caf62f25cfd5047cd4f2c0f357267be9d79d7c4 /tests/quick/30.eio-mp
parent63371c86648ed65a453a95aec80f326f15a9666d (diff)
downloadgem5-8c1563096c5aaf4123bf9ce5116aff3ce44dfd3b.tar.xz
tests: update stats for name changes
Diffstat (limited to 'tests/quick/30.eio-mp')
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini9
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr5
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout7
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt42
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini9
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr4
-rwxr-xr-xtests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout7
-rw-r--r--tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt42
8 files changed, 69 insertions, 56 deletions
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 9f134009a..63867abf6 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -54,6 +54,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -89,6 +90,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -166,6 +168,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -201,6 +204,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -278,6 +282,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -313,6 +318,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -390,6 +396,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -425,6 +432,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -473,6 +481,7 @@ assoc=8
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index 98d9eda34..c3b5cc937 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -7,9 +7,6 @@ For more information see: http://www.m5sim.org/warn/3e0eccba
hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+stdout: Broken pipe
gzip: stdout: Broken pipe
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 174fa89ad..6bbd017e9 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:47:48
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 11:58:24
+M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 9f848a332..f73f5744f 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1366260 # Simulator instruction rate (inst/s)
-host_mem_usage 1147168 # Number of bytes of host memory used
-host_seconds 1.46 # Real time elapsed on the host
-host_tick_rate 170760827 # Simulator tick rate (ticks/s)
+host_inst_rate 5241411 # Simulator instruction rate (inst/s)
+host_mem_usage 1126944 # Number of bytes of host memory used
+host_seconds 0.38 # Real time elapsed on the host
+host_tick_rate 654880397 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2000004 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
@@ -38,8 +38,8 @@ system.cpu0.dcache.demand_mshr_misses 0 # nu
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy
system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -103,8 +103,8 @@ system.cpu0.icache.demand_mshr_misses 0 # nu
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy
system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -163,7 +163,7 @@ system.cpu0.num_int_register_writes 371542 # nu
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_mem_refs 180793 # number of memory refs
system.cpu0.num_store_insts 56350 # Number of store instructions
-system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu0.workload.num_syscalls 18 # Number of system calls
system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
@@ -194,8 +194,8 @@ system.cpu1.dcache.demand_mshr_misses 0 # nu
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy
system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -259,8 +259,8 @@ system.cpu1.icache.demand_mshr_misses 0 # nu
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy
system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -319,7 +319,7 @@ system.cpu1.num_int_register_writes 371542 # nu
system.cpu1.num_load_insts 124443 # Number of load instructions
system.cpu1.num_mem_refs 180793 # number of memory refs
system.cpu1.num_store_insts 56350 # Number of store instructions
-system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu1.workload.num_syscalls 18 # Number of system calls
system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
@@ -350,8 +350,8 @@ system.cpu2.dcache.demand_mshr_misses 0 # nu
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy
system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -415,8 +415,8 @@ system.cpu2.icache.demand_mshr_misses 0 # nu
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy
system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -475,7 +475,7 @@ system.cpu2.num_int_register_writes 371542 # nu
system.cpu2.num_load_insts 124443 # Number of load instructions
system.cpu2.num_mem_refs 180793 # number of memory refs
system.cpu2.num_store_insts 56350 # Number of store instructions
-system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu2.workload.num_syscalls 18 # Number of system calls
system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
@@ -506,8 +506,8 @@ system.cpu3.dcache.demand_mshr_misses 0 # nu
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0 0.540766 # Average percentage of cache occupancy
system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -571,8 +571,8 @@ system.cpu3.icache.demand_mshr_misses 0 # nu
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0 0.425950 # Average percentage of cache occupancy
system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
@@ -631,7 +631,7 @@ system.cpu3.num_int_register_writes 371542 # nu
system.cpu3.num_load_insts 124443 # Number of load instructions
system.cpu3.num_mem_refs 180793 # number of memory refs
system.cpu3.num_store_insts 56350 # Number of store instructions
-system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu3.workload.num_syscalls 18 # Number of system calls
system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
@@ -717,16 +717,16 @@ system.l2c.demand_mshr_misses 0 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy
-system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context
system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_percent::3 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_percent::4 0.000267 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 9ec264236..fcea1bc67 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -51,6 +51,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -86,6 +87,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -160,6 +162,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -195,6 +198,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -269,6 +273,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -304,6 +309,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -378,6 +384,7 @@ assoc=4
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -413,6 +420,7 @@ assoc=1
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -461,6 +469,7 @@ assoc=8
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index fa3024167..98d9eda34 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -8,8 +8,8 @@ hack: be nice to actually delete the event here
gzip: stdout: Broken pipe
-gzip:
gzip: stdout: Broken pipe
-stdout: Broken pipe
+
+gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index af5204214..7540f8e27 100755
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:47:37
-M5 executing on burrito
+M5 compiled Apr 19 2011 11:52:53
+M5 started Apr 19 2011 12:04:57
+M5 executing on maize
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
index 9dfa01a0d..16349cad5 100644
--- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 730494 # Simulator instruction rate (inst/s)
-host_mem_usage 229664 # Number of bytes of host memory used
-host_seconds 2.74 # Real time elapsed on the host
-host_tick_rate 266213751 # Simulator tick rate (ticks/s)
+host_inst_rate 2200513 # Simulator instruction rate (inst/s)
+host_mem_usage 209452 # Number of bytes of host memory used
+host_seconds 0.91 # Real time elapsed on the host
+host_tick_rate 801856981 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1999954 # Number of instructions simulated
sim_seconds 0.000729 # Number of seconds simulated
@@ -50,8 +50,8 @@ system.cpu0.dcache.demand_mshr_misses 463 # nu
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.534216 # Average percentage of cache occupancy
system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context
+system.cpu0.dcache.occ_percent::0 0.534216 # Average percentage of cache occupancy
system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
@@ -121,8 +121,8 @@ system.cpu0.icache.demand_mshr_misses 463 # nu
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy
system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context
+system.cpu0.icache.occ_percent::0 0.422639 # Average percentage of cache occupancy
system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency
@@ -181,7 +181,7 @@ system.cpu0.num_int_register_writes 371542 # nu
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_mem_refs 180793 # number of memory refs
system.cpu0.num_store_insts 56350 # Number of store instructions
-system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu0.workload.num_syscalls 18 # Number of system calls
system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
@@ -224,8 +224,8 @@ system.cpu1.dcache.demand_mshr_misses 463 # nu
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.534204 # Average percentage of cache occupancy
system.cpu1.dcache.occ_blocks::0 273.512548 # Average occupied blocks per context
+system.cpu1.dcache.occ_percent::0 0.534204 # Average percentage of cache occupancy
system.cpu1.dcache.overall_accesses 180774 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
@@ -295,8 +295,8 @@ system.cpu1.icache.demand_mshr_misses 463 # nu
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.422630 # Average percentage of cache occupancy
system.cpu1.icache.occ_blocks::0 216.386658 # Average occupied blocks per context
+system.cpu1.icache.occ_percent::0 0.422630 # Average percentage of cache occupancy
system.cpu1.icache.overall_accesses 500012 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 50697.624190 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency
@@ -355,7 +355,7 @@ system.cpu1.num_int_register_writes 371536 # nu
system.cpu1.num_load_insts 124443 # Number of load instructions
system.cpu1.num_mem_refs 180792 # number of memory refs
system.cpu1.num_store_insts 56349 # Number of store instructions
-system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu1.workload.num_syscalls 18 # Number of system calls
system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency
@@ -398,8 +398,8 @@ system.cpu2.dcache.demand_mshr_misses 463 # nu
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0 0.534196 # Average percentage of cache occupancy
system.cpu2.dcache.occ_blocks::0 273.508588 # Average occupied blocks per context
+system.cpu2.dcache.occ_percent::0 0.534196 # Average percentage of cache occupancy
system.cpu2.dcache.overall_accesses 180772 # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 55272.138229 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency
@@ -469,8 +469,8 @@ system.cpu2.icache.demand_mshr_misses 463 # nu
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0 0.422624 # Average percentage of cache occupancy
system.cpu2.icache.occ_blocks::0 216.383557 # Average occupied blocks per context
+system.cpu2.icache.occ_percent::0 0.422624 # Average percentage of cache occupancy
system.cpu2.icache.overall_accesses 500001 # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 50719.222462 # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency
@@ -529,7 +529,7 @@ system.cpu2.num_int_register_writes 371526 # nu
system.cpu2.num_load_insts 124440 # Number of load instructions
system.cpu2.num_mem_refs 180789 # number of memory refs
system.cpu2.num_store_insts 56349 # Number of store instructions
-system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu2.workload.num_syscalls 18 # Number of system calls
system.cpu3.dcache.ReadReq_accesses 124431 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency
@@ -572,8 +572,8 @@ system.cpu3.dcache.demand_mshr_misses 463 # nu
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0 0.534191 # Average percentage of cache occupancy
system.cpu3.dcache.occ_blocks::0 273.505617 # Average occupied blocks per context
+system.cpu3.dcache.occ_percent::0 0.534191 # Average percentage of cache occupancy
system.cpu3.dcache.overall_accesses 180770 # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency
@@ -643,8 +643,8 @@ system.cpu3.icache.demand_mshr_misses 463 # nu
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.422621 # Average percentage of cache occupancy
system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context
+system.cpu3.icache.occ_percent::0 0.422621 # Average percentage of cache occupancy
system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency
@@ -703,7 +703,7 @@ system.cpu3.num_int_register_writes 371523 # nu
system.cpu3.num_load_insts 124438 # Number of load instructions
system.cpu3.num_mem_refs 180787 # number of memory refs
system.cpu3.num_store_insts 56349 # Number of store instructions
-system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls
+system.cpu3.workload.num_syscalls 18 # Number of system calls
system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses)
@@ -817,16 +817,16 @@ system.l2c.demand_mshr_misses 3428 # nu
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.007348 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.007347 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.007347 # Average percentage of cache occupancy
-system.l2c.occ_%::3 0.007347 # Average percentage of cache occupancy
-system.l2c.occ_%::4 0.000263 # Average percentage of cache occupancy
system.l2c.occ_blocks::0 481.530369 # Average occupied blocks per context
system.l2c.occ_blocks::1 481.519672 # Average occupied blocks per context
system.l2c.occ_blocks::2 481.512310 # Average occupied blocks per context
system.l2c.occ_blocks::3 481.507730 # Average occupied blocks per context
system.l2c.occ_blocks::4 17.228456 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.007348 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.007347 # Average percentage of cache occupancy
+system.l2c.occ_percent::2 0.007347 # Average percentage of cache occupancy
+system.l2c.occ_percent::3 0.007347 # Average percentage of cache occupancy
+system.l2c.occ_percent::4 0.000263 # Average percentage of cache occupancy
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses