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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-09-09 14:40:19 -0400
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-09-09 14:40:19 -0400
commit12497284949cb5418e6bc403723c034aee655666 (patch)
tree425830586f5c32fe2674a3eb998678ef633d2d6e /tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp
parent6dc599ea9bae9cb56ca81094b37009f5a14ebdff (diff)
downloadgem5-12497284949cb5418e6bc403723c034aee655666.tar.xz
cache: fail SC when invalidated while waiting for bus
Corrects an oversight in cset f97b62be544f. The fix there only failed queued SCUpgradeReq packets that encountered an invalidation, which meant that the upgrade had to reach the L2 cache. To handle pending requests in the L1 we must similarly fail StoreCondReq packets too.
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp')
0 files changed, 0 insertions, 0 deletions