Update stats for new single bad-address responder.

Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.

3 files changed, 17 insertions, 26 deletions

diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index b1c2caacb..28f0771b6 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -104,11 +104,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -277,11 +276,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -425,11 +423,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -598,11 +595,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -727,11 +723,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -900,11 +895,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -1029,11 +1023,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -1202,11 +1195,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=1000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=4
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
@@ -1241,11 +1233,10 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
-cpu_side_filter_ranges=
+forward_snoops=true
 hash_delay=1
 latency=10000
 max_miss_count=0
-mem_side_filter_ranges=
 mshrs=92
 prefetch_cache_check_push=true
 prefetch_data_accesses_only=false
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index fca385548..3245c7a36 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Apr 17 2009 00:22:56
-M5 revision 35b1dc26772f 6041 default qtip tip m5threads-base-regressions.diff
-M5 started Apr 17 2009 00:29:37
+M5 compiled Apr 21 2009 18:04:32
+M5 revision e6dd09514462 6117 default qtip tip stats-update
+M5 started Apr 21 2009 18:04:58
 M5 executing on zizzer
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 0689a00e0..df75bec2d 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  28911                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 217084                       # Number of bytes of host memory used
-host_seconds                                    15.18                       # Real time elapsed on the host
-host_tick_rate                               14522493                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  52497                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 211604                       # Number of bytes of host memory used
+host_seconds                                     8.36                       # Real time elapsed on the host
+host_tick_rate                               26370227                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                      438923                       # Number of instructions simulated
 sim_seconds                                  0.000220                       # Number of seconds simulated