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authorSteve Reinhardt <stever@gmail.com>2009-04-22 01:55:52 -0400
committerSteve Reinhardt <stever@gmail.com>2009-04-22 01:55:52 -0400
commit7b40c36fbd1c348e5ef43231325923aae1cd0809 (patch)
treeb1d142d10229a7ca68eff864aa9aae672230e41a /tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
parent6629d9b2bc58a885bfebce1517fd12483497b6e4 (diff)
downloadgem5-7b40c36fbd1c348e5ef43231325923aae1cd0809.tar.xz
Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt')
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 1e2146668..36df0b10e 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 675702 # Simulator instruction rate (inst/s)
-host_mem_usage 214956 # Number of bytes of host memory used
-host_seconds 0.96 # Real time elapsed on the host
-host_tick_rate 273465785 # Simulator tick rate (ticks/s)
+host_inst_rate 700731 # Simulator instruction rate (inst/s)
+host_mem_usage 209476 # Number of bytes of host memory used
+host_seconds 0.93 # Real time elapsed on the host
+host_tick_rate 283592249 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 650423 # Number of instructions simulated
sim_seconds 0.000263 # Number of seconds simulated