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authorGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:11 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-07 19:23:11 -0800
commit1b64bfa933745294667158d0ce22180780b2a22e (patch)
tree11822ba69a5ec4c1c4b7ad72fcf08c87e143e4fe /tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp
parent44e5e7e0533ba2544f2d37f8e051a0422966bd9b (diff)
downloadgem5-1b64bfa933745294667158d0ce22180780b2a22e.tar.xz
Stats: Back out broken update.
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp')
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini13
-rwxr-xr-xtests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout12
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt80
3 files changed, 17 insertions, 88 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index 2a4e57f6c..276044213 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -1,22 +1,13 @@
[root]
type=Root
children=system
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
+dummy=0
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
mem_mode=timing
physmem=system.physmem
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
[system.cpu0]
type=TimingSimpleCPU
@@ -125,7 +116,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index a6189c8f0..cae225db3 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -1,3 +1,5 @@
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
M5 Simulator System
Copyright (c) 2001-2008
@@ -5,11 +7,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Feb 6 2011 15:23:54
-M5 revision b885adc82ab4+ 7924+ default tip qtip brad/regress_updates
-M5 started Feb 6 2011 20:47:32
-M5 executing on SC2B0617
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:45
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 7703b45f1..a2bed5a68 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 1041704 # Simulator instruction rate (inst/s)
-host_mem_usage 213476 # Number of bytes of host memory used
-host_seconds 0.62 # Real time elapsed on the host
-host_tick_rate 419868162 # Simulator tick rate (ticks/s)
+host_inst_rate 583465 # Simulator instruction rate (inst/s)
+host_mem_usage 215700 # Number of bytes of host memory used
+host_seconds 1.12 # Real time elapsed on the host
+host_tick_rate 235218525 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 650423 # Number of instructions simulated
sim_seconds 0.000262 # Number of seconds simulated
@@ -141,24 +141,8 @@ system.cpu0.icache.writebacks 0 # nu
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.numCycles 524590 # number of cpu cycles simulated
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.num_busy_cycles 524590 # Number of busy cycles
-system.cpu0.num_conditional_control_insts 0 # number of instructions that are conditional controls
-system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_func_calls 0 # number of times a function call or return occured
-system.cpu0.num_idle_cycles 0 # Number of idle cycles
system.cpu0.num_insts 158353 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses
-system.cpu0.num_int_insts 109064 # number of integer instructions
-system.cpu0.num_int_register_reads 315336 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110671 # number of times the integer registers were written
-system.cpu0.num_load_insts 48930 # Number of load instructions
-system.cpu0.num_mem_refs 73905 # number of memory refs
-system.cpu0.num_store_insts 24975 # Number of store instructions
+system.cpu0.num_refs 73905 # Number of memory references
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
system.cpu1.dcache.ReadReq_accesses 38632 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 20316.666667 # average ReadReq miss latency
@@ -295,24 +279,8 @@ system.cpu1.icache.writebacks 0 # nu
system.cpu1.idle_fraction 0.130715 # Percentage of idle cycles
system.cpu1.not_idle_fraction 0.869285 # Percentage of non-idle cycles
system.cpu1.numCycles 513666 # number of cpu cycles simulated
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.num_busy_cycles 446521.933500 # Number of busy cycles
-system.cpu1.num_conditional_control_insts 0 # number of instructions that are conditional controls
-system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_func_calls 0 # number of times a function call or return occured
-system.cpu1.num_idle_cycles 67144.066500 # Number of idle cycles
system.cpu1.num_insts 168364 # Number of instructions executed
-system.cpu1.num_int_alu_accesses 105930 # Number of integer alu accesses
-system.cpu1.num_int_insts 105930 # number of integer instructions
-system.cpu1.num_int_register_reads 244134 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 89763 # number of times the integer registers were written
-system.cpu1.num_load_insts 38640 # Number of load instructions
-system.cpu1.num_mem_refs 46919 # number of memory refs
-system.cpu1.num_store_insts 8279 # Number of store instructions
+system.cpu1.num_refs 46919 # Number of memory references
system.cpu2.dcache.ReadReq_accesses 40867 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 15941.935484 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 12941.935484 # average ReadReq mshr miss latency
@@ -448,24 +416,8 @@ system.cpu2.icache.writebacks 0 # nu
system.cpu2.idle_fraction 0.131215 # Percentage of idle cycles
system.cpu2.not_idle_fraction 0.868785 # Percentage of non-idle cycles
system.cpu2.numCycles 513662 # number of cpu cycles simulated
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.num_busy_cycles 446261.914218 # Number of busy cycles
-system.cpu2.num_conditional_control_insts 0 # number of instructions that are conditional controls
-system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu2.num_fp_insts 0 # number of float instructions
-system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu2.num_func_calls 0 # number of times a function call or return occured
-system.cpu2.num_idle_cycles 67400.085782 # Number of idle cycles
system.cpu2.num_insts 161536 # Number of instructions executed
-system.cpu2.num_int_alu_accesses 110351 # Number of integer alu accesses
-system.cpu2.num_int_insts 110351 # number of integer instructions
-system.cpu2.num_int_register_reads 284309 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 107647 # number of times the integer registers were written
-system.cpu2.num_load_insts 40875 # Number of load instructions
-system.cpu2.num_mem_refs 56961 # number of memory refs
-system.cpu2.num_store_insts 16086 # Number of store instructions
+system.cpu2.num_refs 56961 # Number of memory references
system.cpu3.dcache.ReadReq_accesses 40736 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 16115.384615 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13115.384615 # average ReadReq mshr miss latency
@@ -601,24 +553,8 @@ system.cpu3.icache.writebacks 0 # nu
system.cpu3.idle_fraction 0.131691 # Percentage of idle cycles
system.cpu3.not_idle_fraction 0.868309 # Percentage of non-idle cycles
system.cpu3.numCycles 513670 # number of cpu cycles simulated
-system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu3.num_busy_cycles 446024.068564 # Number of busy cycles
-system.cpu3.num_conditional_control_insts 0 # number of instructions that are conditional controls
-system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu3.num_fp_insts 0 # number of float instructions
-system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu3.num_func_calls 0 # number of times a function call or return occured
-system.cpu3.num_idle_cycles 67645.931436 # Number of idle cycles
system.cpu3.num_insts 162170 # Number of instructions executed
-system.cpu3.num_int_alu_accesses 110096 # Number of integer alu accesses
-system.cpu3.num_int_insts 110096 # number of integer instructions
-system.cpu3.num_int_register_reads 281520 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 106379 # number of times the integer registers were written
-system.cpu3.num_load_insts 40744 # Number of load instructions
-system.cpu3.num_mem_refs 56264 # number of memory refs
-system.cpu3.num_store_insts 15520 # Number of store instructions
+system.cpu3.num_refs 56264 # Number of memory references
system.l2c.ReadExReq_accesses::0 99 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::2 12 # number of ReadExReq accesses(hits+misses)