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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:06:22 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-08-17 05:06:22 -0700 |
| commit | 0f8b5afd7ad82fda05c3ad42cda4f9046992428d (patch) | |
| tree | 794e8480ec916aa1b7da4c756f71ae1f6b1ffec7 /tests/quick/40.m5threads-test-atomic/ref/sparc/linux | |
| parent | 0685ae7a2dbceaa2b9b264a57c9d5f82868e777e (diff) | |
| download | gem5-0f8b5afd7ad82fda05c3ad42cda4f9046992428d.tar.xz | |
tests: update reference config.ini files for previous cset
Rename 'responder_set' to 'use_default_range'.
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref/sparc/linux')
4 files changed, 7 insertions, 7 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index e7279bca8..c3c2d2e0e 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1265,7 +1265,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.mem_side system.physmem.port[0] @@ -1285,7 +1285,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini index fb5bbcb94..a92224734 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini @@ -473,7 +473,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.mem_side system.physmem.port[0] @@ -493,7 +493,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini index bbd5c6af7..a2a28909c 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini @@ -182,7 +182,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0] diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index f3434ec9b..ca866c925 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -461,7 +461,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.mem_side system.physmem.port[0] @@ -481,7 +481,7 @@ block_size=64 bus_id=0 clock=1000 header_cycles=1 -responder_set=false +use_default_range=false width=64 port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side |