summaryrefslogtreecommitdiff
path: root/tests/quick/40.m5threads-test-atomic/ref
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:05 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:05 -0600
commit371110fb0a8b5c687682c8ce1e1445eee1d3a7bc (patch)
tree9610ca973c18ed1270fba72f8040c8edf140d62d /tests/quick/40.m5threads-test-atomic/ref
parent005892719047c3b4b383d9aeeeb481039518f661 (diff)
downloadgem5-371110fb0a8b5c687682c8ce1e1445eee1d3a7bc.tar.xz
Regressions: Update regressions for SIMD opclass changes
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic/ref')
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini592
-rwxr-xr-xtests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout10
-rw-r--r--tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt168
3 files changed, 717 insertions, 53 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index c3c2d2e0e..17847f641 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -136,8 +136,8 @@ size=64
[system.cpu0.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
[system.cpu0.fuPool.FUList0]
type=FUDesc
@@ -231,41 +231,167 @@ opLat=1
[system.cpu0.fuPool.FUList5]
type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
+
+[system.cpu0.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu0.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu0.fuPool.FUList6]
+type=FUDesc
children=opList
count=0
-opList=system.cpu0.fuPool.FUList5.opList
+opList=system.cpu0.fuPool.FUList6.opList
-[system.cpu0.fuPool.FUList5.opList]
+[system.cpu0.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu0.fuPool.FUList6]
+[system.cpu0.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
-opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1
+opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
-[system.cpu0.fuPool.FUList6.opList0]
+[system.cpu0.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
-[system.cpu0.fuPool.FUList6.opList1]
+[system.cpu0.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu0.fuPool.FUList7]
+[system.cpu0.fuPool.FUList8]
type=FUDesc
children=opList
count=1
-opList=system.cpu0.fuPool.FUList7.opList
+opList=system.cpu0.fuPool.FUList8.opList
-[system.cpu0.fuPool.FUList7.opList]
+[system.cpu0.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@@ -455,8 +581,8 @@ size=64
[system.cpu1.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
[system.cpu1.fuPool.FUList0]
type=FUDesc
@@ -550,41 +676,167 @@ opLat=1
[system.cpu1.fuPool.FUList5]
type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
+
+[system.cpu1.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu1.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu1.fuPool.FUList6]
+type=FUDesc
children=opList
count=0
-opList=system.cpu1.fuPool.FUList5.opList
+opList=system.cpu1.fuPool.FUList6.opList
-[system.cpu1.fuPool.FUList5.opList]
+[system.cpu1.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu1.fuPool.FUList6]
+[system.cpu1.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
-opList=system.cpu1.fuPool.FUList6.opList0 system.cpu1.fuPool.FUList6.opList1
+opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
-[system.cpu1.fuPool.FUList6.opList0]
+[system.cpu1.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
-[system.cpu1.fuPool.FUList6.opList1]
+[system.cpu1.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu1.fuPool.FUList7]
+[system.cpu1.fuPool.FUList8]
type=FUDesc
children=opList
count=1
-opList=system.cpu1.fuPool.FUList7.opList
+opList=system.cpu1.fuPool.FUList8.opList
-[system.cpu1.fuPool.FUList7.opList]
+[system.cpu1.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@@ -755,8 +1007,8 @@ size=64
[system.cpu2.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
[system.cpu2.fuPool.FUList0]
type=FUDesc
@@ -850,41 +1102,167 @@ opLat=1
[system.cpu2.fuPool.FUList5]
type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
+
+[system.cpu2.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu2.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu2.fuPool.FUList6]
+type=FUDesc
children=opList
count=0
-opList=system.cpu2.fuPool.FUList5.opList
+opList=system.cpu2.fuPool.FUList6.opList
-[system.cpu2.fuPool.FUList5.opList]
+[system.cpu2.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu2.fuPool.FUList6]
+[system.cpu2.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
-opList=system.cpu2.fuPool.FUList6.opList0 system.cpu2.fuPool.FUList6.opList1
+opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
-[system.cpu2.fuPool.FUList6.opList0]
+[system.cpu2.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
-[system.cpu2.fuPool.FUList6.opList1]
+[system.cpu2.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu2.fuPool.FUList7]
+[system.cpu2.fuPool.FUList8]
type=FUDesc
children=opList
count=1
-opList=system.cpu2.fuPool.FUList7.opList
+opList=system.cpu2.fuPool.FUList8.opList
-[system.cpu2.fuPool.FUList7.opList]
+[system.cpu2.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
@@ -1055,8 +1433,8 @@ size=64
[system.cpu3.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
-FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
+FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8
[system.cpu3.fuPool.FUList0]
type=FUDesc
@@ -1150,41 +1528,167 @@ opLat=1
[system.cpu3.fuPool.FUList5]
type=FUDesc
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
+count=4
+opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19
+
+[system.cpu3.fuPool.FUList5.opList00]
+type=OpDesc
+issueLat=1
+opClass=SimdAdd
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList01]
+type=OpDesc
+issueLat=1
+opClass=SimdAddAcc
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList02]
+type=OpDesc
+issueLat=1
+opClass=SimdAlu
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList03]
+type=OpDesc
+issueLat=1
+opClass=SimdCmp
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList04]
+type=OpDesc
+issueLat=1
+opClass=SimdCvt
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList05]
+type=OpDesc
+issueLat=1
+opClass=SimdMisc
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList06]
+type=OpDesc
+issueLat=1
+opClass=SimdMult
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList07]
+type=OpDesc
+issueLat=1
+opClass=SimdMultAcc
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList08]
+type=OpDesc
+issueLat=1
+opClass=SimdShift
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList09]
+type=OpDesc
+issueLat=1
+opClass=SimdShiftAcc
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList10]
+type=OpDesc
+issueLat=1
+opClass=SimdSqrt
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList11]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAdd
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList12]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatAlu
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList13]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCmp
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList14]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatCvt
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList15]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatDiv
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList16]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMisc
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList17]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMult
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList18]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatMultAcc
+opLat=1
+
+[system.cpu3.fuPool.FUList5.opList19]
+type=OpDesc
+issueLat=1
+opClass=SimdFloatSqrt
+opLat=1
+
+[system.cpu3.fuPool.FUList6]
+type=FUDesc
children=opList
count=0
-opList=system.cpu3.fuPool.FUList5.opList
+opList=system.cpu3.fuPool.FUList6.opList
-[system.cpu3.fuPool.FUList5.opList]
+[system.cpu3.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu3.fuPool.FUList6]
+[system.cpu3.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
-opList=system.cpu3.fuPool.FUList6.opList0 system.cpu3.fuPool.FUList6.opList1
+opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1
-[system.cpu3.fuPool.FUList6.opList0]
+[system.cpu3.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
-[system.cpu3.fuPool.FUList6.opList1]
+[system.cpu3.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
-[system.cpu3.fuPool.FUList7]
+[system.cpu3.fuPool.FUList8]
type=FUDesc
children=opList
count=1
-opList=system.cpu3.fuPool.FUList7.opList
+opList=system.cpu3.fuPool.FUList8.opList
-[system.cpu3.fuPool.FUList7.opList]
+[system.cpu3.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 890ebb6d8..3330dd3da 100755
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -5,11 +5,11 @@ The Regents of The University of Michigan
All Rights Reserved
-M5 compiled Sep 26 2010 21:00:10
-M5 revision eb8d8f78ca15 7689 default qtip tip pctype.patch qbase
-M5 started Sep 26 2010 21:00:16
-M5 executing on burrito
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+M5 compiled Nov 15 2010 00:04:22
+M5 revision f440cdaf1c2d+ 7743+ default tip
+M5 started Nov 15 2010 00:06:46
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 8e653945f..eea552a2f 100644
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,9 +1,9 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 45662 # Simulator instruction rate (inst/s)
-host_mem_usage 235748 # Number of bytes of host memory used
-host_seconds 25.27 # Real time elapsed on the host
-host_tick_rate 4652764 # Simulator tick rate (ticks/s)
+host_inst_rate 225525 # Simulator instruction rate (inst/s)
+host_mem_usage 214280 # Number of bytes of host memory used
+host_seconds 5.12 # Real time elapsed on the host
+host_tick_rate 22978978 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1153797 # Number of instructions simulated
sim_seconds 0.000118 # Number of seconds simulated
@@ -272,6 +272,26 @@ system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 41.97% # Ty
system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 41.97% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 41.97% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemRead 175866 38.63% 80.61% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::MemWrite 88274 19.39% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
@@ -289,6 +309,26 @@ system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 15.76% # at
system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAdd 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdAlu 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdCmp 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdCvt 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMisc 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMult 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdShift 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 15.76% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 15.76% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemRead 75 40.76% 56.52% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::MemWrite 80 43.48% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
@@ -605,6 +645,26 @@ system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 47.51% # Ty
system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 47.51% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemRead 95884 36.40% 83.91% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::MemWrite 42396 16.09% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
@@ -622,6 +682,26 @@ system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.18% # at
system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.18% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.18% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemRead 55 28.50% 33.68% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::MemWrite 128 66.32% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
@@ -937,6 +1017,26 @@ system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.50% # Ty
system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.50% # Type of FU issued
+system.cpu2.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.50% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemRead 83455 36.32% 84.81% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::MemWrite 34899 15.19% 100.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
@@ -954,6 +1054,26 @@ system.cpu2.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.88% # at
system.cpu2.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.88% # attempts to use FU when none available
+system.cpu2.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.88% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemRead 48 25.67% 31.55% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::MemWrite 128 68.45% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
@@ -1268,6 +1388,26 @@ system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 48.00% # Ty
system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 48.00% # Type of FU issued
+system.cpu3.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 48.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemRead 89212 36.40% 84.40% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::MemWrite 38247 15.60% 100.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
@@ -1285,6 +1425,26 @@ system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.21% # at
system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdAdd 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdAlu 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdCmp 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdCvt 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdMisc 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdMult 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdShift 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 5.21% # attempts to use FU when none available
+system.cpu3.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 5.21% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemRead 54 28.12% 33.33% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::MemWrite 128 66.67% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available