m5: Regression Tester Update

This patch includes the necessary regression updates to test the new ruby
configuration system.  The patch includes support for multiple ruby protocols
and adds the ruby random tester.  The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses.  These tests can be
added back in when ruby supports atomic mode for real.

--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py

5 files changed, 0 insertions, 1310 deletions

diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/config.ini
deleted file mode 100644
index 2c754d8d5..000000000
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/config.ini
+++ /dev/null
@@ -1,218 +0,0 @@
-[root]
-type=Root
-children=system
-dummy=0
-
-[system]
-type=System
-children=cpu0 cpu1 cpu2 cpu3 membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu0]
-type=AtomicSimpleCPU
-children=dtb itb tracer workload
-checker=Null
-clock=500
-cpu_id=0
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu0.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[1]
-icache_port=system.membus.port[0]
-
-[system.cpu0.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu0.itb]
-type=SparcTLB
-size=64
-
-[system.cpu0.tracer]
-type=ExeTracer
-
-[system.cpu0.workload]
-type=LiveProcess
-cmd=test_atomic 4
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.cpu1]
-type=AtomicSimpleCPU
-children=dtb itb tracer
-checker=Null
-clock=500
-cpu_id=1
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu1.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[3]
-icache_port=system.membus.port[2]
-
-[system.cpu1.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu1.itb]
-type=SparcTLB
-size=64
-
-[system.cpu1.tracer]
-type=ExeTracer
-
-[system.cpu2]
-type=AtomicSimpleCPU
-children=dtb itb tracer
-checker=Null
-clock=500
-cpu_id=2
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu2.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu2.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu2.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[5]
-icache_port=system.membus.port[4]
-
-[system.cpu2.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu2.itb]
-type=SparcTLB
-size=64
-
-[system.cpu2.tracer]
-type=ExeTracer
-
-[system.cpu3]
-type=AtomicSimpleCPU
-children=dtb itb tracer
-checker=Null
-clock=500
-cpu_id=3
-defer_registration=false
-do_checkpoint_insts=true
-do_statistics_insts=true
-dtb=system.cpu3.dtb
-function_trace=false
-function_trace_start=0
-itb=system.cpu3.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-phase=0
-progress_interval=0
-simulate_data_stalls=false
-simulate_inst_stalls=false
-system=system
-tracer=system.cpu3.tracer
-width=1
-workload=system.cpu0.workload
-dcache_port=system.membus.port[7]
-icache_port=system.membus.port[6]
-
-[system.cpu3.dtb]
-type=SparcTLB
-size=64
-
-[system.cpu3.itb]
-type=SparcTLB
-size=64
-
-[system.cpu3.tracer]
-type=ExeTracer
-
-[system.membus]
-type=Bus
-block_size=64
-bus_id=0
-clock=1000
-header_cycles=1
-responder_set=false
-width=64
-port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0]
-
-[system.physmem]
-type=RubyMemory
-clock=1
-config_file=
-config_options=
-debug=false
-debug_file=
-file=
-latency=30000
-latency_var=0
-null=false
-num_cpus=4
-phase=0
-range=0:134217727
-stats_file=ruby.stats
-zero=false
-port=system.membus.port[8]
-
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/ruby.stats b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/ruby.stats
deleted file mode 100644
index 2f903fa47..000000000
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/ruby.stats
+++ /dev/null
@@ -1,930 +0,0 @@
-
-================ Begin RubySystem Configuration Print ================
-
-Ruby Configuration
-------------------
-protocol: MOSI_SMP_bcast
-compiled_at: 22:54:24, May  4 2009
-RUBY_DEBUG: false
-hostname: piton
-g_RANDOM_SEED: 1
-g_DEADLOCK_THRESHOLD: 500000
-RANDOMIZATION: false
-g_SYNTHETIC_DRIVER: false
-g_DETERMINISTIC_DRIVER: false
-g_FILTERING_ENABLED: false
-g_DISTRIBUTED_PERSISTENT_ENABLED: true
-g_DYNAMIC_TIMEOUT_ENABLED: true
-g_RETRY_THRESHOLD: 1
-g_FIXED_TIMEOUT_LATENCY: 300
-g_trace_warmup_length: 1000000
-g_bash_bandwidth_adaptive_threshold: 0.75
-g_tester_length: 0
-g_synthetic_locks: 2048
-g_deterministic_addrs: 1
-g_SpecifiedGenerator: DetermInvGenerator
-g_callback_counter: 0
-g_NUM_COMPLETIONS_BEFORE_PASS: 0
-g_NUM_SMT_THREADS: 1
-g_think_time: 5
-g_hold_time: 5
-g_wait_time: 5
-PROTOCOL_DEBUG_TRACE: true
-DEBUG_FILTER_STRING: none
-DEBUG_VERBOSITY_STRING: none
-DEBUG_START_TIME: 0
-DEBUG_OUTPUT_FILENAME: none
-SIMICS_RUBY_MULTIPLIER: 4
-OPAL_RUBY_MULTIPLIER: 1
-TRANSACTION_TRACE_ENABLED: false
-USER_MODE_DATA_ONLY: false
-PROFILE_HOT_LINES: false
-PROFILE_ALL_INSTRUCTIONS: false
-PRINT_INSTRUCTION_TRACE: false
-g_DEBUG_CYCLE: 0
-BLOCK_STC: false
-PERFECT_MEMORY_SYSTEM: false
-PERFECT_MEMORY_SYSTEM_LATENCY: 0
-DATA_BLOCK: false
-REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
-L1_CACHE_ASSOC: 4
-L1_CACHE_NUM_SETS_BITS: 8
-L2_CACHE_ASSOC: 4
-L2_CACHE_NUM_SETS_BITS: 16
-g_MEMORY_SIZE_BYTES: 4294967296
-g_DATA_BLOCK_BYTES: 64
-g_PAGE_SIZE_BYTES: 4096
-g_REPLACEMENT_POLICY: PSEDUO_LRU
-g_NUM_PROCESSORS: 4
-g_NUM_L2_BANKS: 4
-g_NUM_MEMORIES: 4
-g_PROCS_PER_CHIP: 1
-g_NUM_CHIPS: 4
-g_NUM_CHIP_BITS: 2
-g_MEMORY_SIZE_BITS: 32
-g_DATA_BLOCK_BITS: 6
-g_PAGE_SIZE_BITS: 12
-g_NUM_PROCESSORS_BITS: 2
-g_PROCS_PER_CHIP_BITS: 0
-g_NUM_L2_BANKS_BITS: 2
-g_NUM_L2_BANKS_PER_CHIP_BITS: 0
-g_NUM_L2_BANKS_PER_CHIP: 1
-g_NUM_MEMORIES_BITS: 2
-g_NUM_MEMORIES_PER_CHIP: 1
-g_MEMORY_MODULE_BITS: 24
-g_MEMORY_MODULE_BLOCKS: 16777216
-MAP_L2BANKS_TO_LOWEST_BITS: false
-DIRECTORY_CACHE_LATENCY: 6
-NULL_LATENCY: 1
-ISSUE_LATENCY: 2
-CACHE_RESPONSE_LATENCY: 12
-L2_RESPONSE_LATENCY: 6
-L2_TAG_LATENCY: 6
-L1_RESPONSE_LATENCY: 3
-MEMORY_RESPONSE_LATENCY_MINUS_2: 158
-DIRECTORY_LATENCY: 80
-NETWORK_LINK_LATENCY: 1
-COPY_HEAD_LATENCY: 4
-ON_CHIP_LINK_LATENCY: 1
-RECYCLE_LATENCY: 10
-L2_RECYCLE_LATENCY: 5
-TIMER_LATENCY: 10000
-TBE_RESPONSE_LATENCY: 1
-PERIODIC_TIMER_WAKEUPS: true
-PROFILE_EXCEPTIONS: false
-PROFILE_XACT: true
-PROFILE_NONXACT: false
-XACT_DEBUG: true
-XACT_DEBUG_LEVEL: 1
-XACT_MEMORY: false
-XACT_ENABLE_TOURMALINE: false
-XACT_NUM_CURRENT: 0
-XACT_LAST_UPDATE: 0
-XACT_ISOLATION_CHECK: false
-PERFECT_FILTER: true
-READ_WRITE_FILTER: Perfect_
-PERFECT_VIRTUAL_FILTER: true
-VIRTUAL_READ_WRITE_FILTER: Perfect_
-PERFECT_SUMMARY_FILTER: true
-SUMMARY_READ_WRITE_FILTER: Perfect_
-XACT_EAGER_CD: true
-XACT_LAZY_VM: false
-XACT_CONFLICT_RES: BASE
-XACT_VISUALIZER: false
-XACT_COMMIT_TOKEN_LATENCY: 0
-XACT_NO_BACKOFF: false
-XACT_LOG_BUFFER_SIZE: 0
-XACT_STORE_PREDICTOR_HISTORY: 256
-XACT_STORE_PREDICTOR_ENTRIES: 256
-XACT_STORE_PREDICTOR_THRESHOLD: 4
-XACT_FIRST_ACCESS_COST: 0
-XACT_FIRST_PAGE_ACCESS_COST: 0
-ENABLE_MAGIC_WAITING: false
-ENABLE_WATCHPOINT: false
-XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
-ATMTP_ENABLED: false
-ATMTP_ABORT_ON_NON_XACT_INST: false
-ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
-ATMTP_XACT_MAX_STORES: 32
-ATMTP_DEBUG_LEVEL: 0
-L1_REQUEST_LATENCY: 2
-L2_REQUEST_LATENCY: 4
-SINGLE_ACCESS_L2_BANKS: true
-SEQUENCER_TO_CONTROLLER_LATENCY: 4
-L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
-L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
-DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
-g_SEQUENCER_OUTSTANDING_REQUESTS: 16
-NUMBER_OF_TBES: 128
-NUMBER_OF_L1_TBES: 32
-NUMBER_OF_L2_TBES: 32
-FINITE_BUFFERING: false
-FINITE_BUFFER_SIZE: 3
-PROCESSOR_BUFFER_SIZE: 10
-PROTOCOL_BUFFER_SIZE: 32
-TSO: false
-g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
-g_CACHE_DESIGN: NUCA
-g_endpoint_bandwidth: 10000
-g_adaptive_routing: true
-NUMBER_OF_VIRTUAL_NETWORKS: 4
-FAN_OUT_DEGREE: 4
-g_PRINT_TOPOLOGY: true
-XACT_LENGTH: 0
-XACT_SIZE: 0
-ABORT_RETRY_TIME: 0
-g_GARNET_NETWORK: false
-g_DETAIL_NETWORK: false
-g_NETWORK_TESTING: false
-g_FLIT_SIZE: 16
-g_NUM_PIPE_STAGES: 4
-g_VCS_PER_CLASS: 4
-g_BUFFER_SIZE: 4
-MEM_BUS_CYCLE_MULTIPLIER: 10
-BANKS_PER_RANK: 8
-RANKS_PER_DIMM: 2
-DIMMS_PER_CHANNEL: 2
-BANK_BIT_0: 8
-RANK_BIT_0: 11
-DIMM_BIT_0: 12
-BANK_QUEUE_SIZE: 12
-BANK_BUSY_TIME: 11
-RANK_RANK_DELAY: 1
-READ_WRITE_DELAY: 2
-BASIC_BUS_BUSY_TIME: 2
-MEM_CTL_LATENCY: 12
-REFRESH_PERIOD: 1560
-TFAW: 0
-MEM_RANDOM_ARBITRATE: 0
-MEM_FIXED_DELAY: 0
-
-Chip Config
------------
-Total_Chips: 4
-
-L1Cache_TBEs numberPerChip: 1
-TBEs_per_TBETable: 128
-
-L1Cache_L1IcacheMemory numberPerChip: 1
-Cache config: L1Cache_0_L1I
-  cache_associativity: 4
-  num_cache_sets_bits: 8
-  num_cache_sets: 256
-  cache_set_size_bytes: 16384
-  cache_set_size_Kbytes: 16
-  cache_set_size_Mbytes: 0.015625
-  cache_size_bytes: 65536
-  cache_size_Kbytes: 64
-  cache_size_Mbytes: 0.0625
-
-L1Cache_L1DcacheMemory numberPerChip: 1
-Cache config: L1Cache_0_L1D
-  cache_associativity: 4
-  num_cache_sets_bits: 8
-  num_cache_sets: 256
-  cache_set_size_bytes: 16384
-  cache_set_size_Kbytes: 16
-  cache_set_size_Mbytes: 0.015625
-  cache_size_bytes: 65536
-  cache_size_Kbytes: 64
-  cache_size_Mbytes: 0.0625
-
-L1Cache_L2cacheMemory numberPerChip: 1
-Cache config: L1Cache_0_L2
-  cache_associativity: 4
-  num_cache_sets_bits: 16
-  num_cache_sets: 65536
-  cache_set_size_bytes: 4194304
-  cache_set_size_Kbytes: 4096
-  cache_set_size_Mbytes: 4
-  cache_size_bytes: 16777216
-  cache_size_Kbytes: 16384
-  cache_size_Mbytes: 16
-
-L1Cache_mandatoryQueue numberPerChip: 1
-
-L1Cache_sequencer numberPerChip: 1
-sequencer: Sequencer - SC
-  max_outstanding_requests: 16
-
-L1Cache_storeBuffer numberPerChip: 1
-Store buffer entries: 128 (Only valid if TSO is enabled)
-
-Directory_directory numberPerChip: 1
-Memory config:
-  memory_bits: 32
-  memory_size_bytes: 4294967296
-  memory_size_Kbytes: 4.1943e+06
-  memory_size_Mbytes: 4096
-  memory_size_Gbytes: 4
-  module_bits: 24
-  module_size_lines: 16777216
-  module_size_bytes: 1073741824
-  module_size_Kbytes: 1.04858e+06
-  module_size_Mbytes: 1024
-
-
-Network Configuration
----------------------
-network: SIMPLE_NETWORK
-topology: HIERARCHICAL_SWITCH
-
-virtual_net_0: active, ordered
-virtual_net_1: active, unordered
-virtual_net_2: inactive
-virtual_net_3: inactive
-
---- Begin Topology Print ---
-
-Topology print ONLY indicates the _NETWORK_ latency between two machines
-It does NOT include the latency within the machines
-
-L1Cache-0 Network Latencies
-  L1Cache-0 -> L1Cache-1 net_lat: 9
-  L1Cache-0 -> L1Cache-2 net_lat: 9
-  L1Cache-0 -> L1Cache-3 net_lat: 9
-  L1Cache-0 -> Directory-0 net_lat: 9
-  L1Cache-0 -> Directory-1 net_lat: 9
-  L1Cache-0 -> Directory-2 net_lat: 9
-  L1Cache-0 -> Directory-3 net_lat: 9
-
-L1Cache-1 Network Latencies
-  L1Cache-1 -> L1Cache-0 net_lat: 9
-  L1Cache-1 -> L1Cache-2 net_lat: 9
-  L1Cache-1 -> L1Cache-3 net_lat: 9
-  L1Cache-1 -> Directory-0 net_lat: 9
-  L1Cache-1 -> Directory-1 net_lat: 9
-  L1Cache-1 -> Directory-2 net_lat: 9
-  L1Cache-1 -> Directory-3 net_lat: 9
-
-L1Cache-2 Network Latencies
-  L1Cache-2 -> L1Cache-0 net_lat: 9
-  L1Cache-2 -> L1Cache-1 net_lat: 9
-  L1Cache-2 -> L1Cache-3 net_lat: 9
-  L1Cache-2 -> Directory-0 net_lat: 9
-  L1Cache-2 -> Directory-1 net_lat: 9
-  L1Cache-2 -> Directory-2 net_lat: 9
-  L1Cache-2 -> Directory-3 net_lat: 9
-
-L1Cache-3 Network Latencies
-  L1Cache-3 -> L1Cache-0 net_lat: 9
-  L1Cache-3 -> L1Cache-1 net_lat: 9
-  L1Cache-3 -> L1Cache-2 net_lat: 9
-  L1Cache-3 -> Directory-0 net_lat: 9
-  L1Cache-3 -> Directory-1 net_lat: 9
-  L1Cache-3 -> Directory-2 net_lat: 9
-  L1Cache-3 -> Directory-3 net_lat: 9
-
-Directory-0 Network Latencies
-  Directory-0 -> L1Cache-0 net_lat: 9
-  Directory-0 -> L1Cache-1 net_lat: 9
-  Directory-0 -> L1Cache-2 net_lat: 9
-  Directory-0 -> L1Cache-3 net_lat: 9
-  Directory-0 -> Directory-1 net_lat: 9
-  Directory-0 -> Directory-2 net_lat: 9
-  Directory-0 -> Directory-3 net_lat: 9
-
-Directory-1 Network Latencies
-  Directory-1 -> L1Cache-0 net_lat: 9
-  Directory-1 -> L1Cache-1 net_lat: 9
-  Directory-1 -> L1Cache-2 net_lat: 9
-  Directory-1 -> L1Cache-3 net_lat: 9
-  Directory-1 -> Directory-0 net_lat: 9
-  Directory-1 -> Directory-2 net_lat: 9
-  Directory-1 -> Directory-3 net_lat: 9
-
-Directory-2 Network Latencies
-  Directory-2 -> L1Cache-0 net_lat: 9
-  Directory-2 -> L1Cache-1 net_lat: 9
-  Directory-2 -> L1Cache-2 net_lat: 9
-  Directory-2 -> L1Cache-3 net_lat: 9
-  Directory-2 -> Directory-0 net_lat: 9
-  Directory-2 -> Directory-1 net_lat: 9
-  Directory-2 -> Directory-3 net_lat: 9
-
-Directory-3 Network Latencies
-  Directory-3 -> L1Cache-0 net_lat: 9
-  Directory-3 -> L1Cache-1 net_lat: 9
-  Directory-3 -> L1Cache-2 net_lat: 9
-  Directory-3 -> L1Cache-3 net_lat: 9
-  Directory-3 -> Directory-0 net_lat: 9
-  Directory-3 -> Directory-1 net_lat: 9
-  Directory-3 -> Directory-2 net_lat: 9
-
---- End Topology Print ---
-
-Profiler Configuration
-----------------------
-periodic_stats_period: 1000000
-
-================ End RubySystem Configuration Print ================
-
-
-Real time: May/05/2009 07:34:05
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 3
-Elapsed_time_in_minutes: 0.05
-Elapsed_time_in_hours: 0.000833333
-Elapsed_time_in_days: 3.47222e-05
-
-Virtual_time_in_seconds: 1.88
-Virtual_time_in_minutes: 0.0313333
-Virtual_time_in_hours:   0.000522222
-Virtual_time_in_days:    0.000522222
-
-Ruby_current_time: 87713501
-Ruby_start_time: 1
-Ruby_cycles: 87713500
-
-mbytes_resident: 90.4062
-mbytes_total: 251.832
-resident_ratio: 0.35901
-
-Total_misses: 0
-total_misses: 0 [ 0 0 0 0 ]
-user_misses: 0 [ 0 0 0 0 ]
-supervisor_misses: 0 [ 0 0 0 0 ]
-
-instruction_executed: 4 [ 1 1 1 1 ]
-cycles_executed: 4 [ 1 1 1 1 ]
-cycles_per_instruction: 8.77135e+07 [ 8.77135e+07 8.77135e+07 8.77135e+07 8.77135e+07 ]
-misses_per_thousand_instructions: 0 [ 0 0 0 0 ]
-
-transactions_started: 0 [ 0 0 0 0 ]
-transactions_ended: 0 [ 0 0 0 0 ]
-instructions_per_transaction: 0 [ 0 0 0 0 ]
-cycles_per_transaction: 0 [ 0 0 0 0 ]
-misses_per_transaction: 0 [ 0 0 0 0 ]
-
-L1D_cache cache stats: 
-  L1D_cache_total_misses: 0
-  L1D_cache_total_demand_misses: 0
-  L1D_cache_total_prefetches: 0
-  L1D_cache_total_sw_prefetches: 0
-  L1D_cache_total_hw_prefetches: 0
-  L1D_cache_misses_per_transaction: 0
-  L1D_cache_misses_per_instruction: 0
-  L1D_cache_instructions_per_misses: NaN
-
-  L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L1I_cache cache stats: 
-  L1I_cache_total_misses: 0
-  L1I_cache_total_demand_misses: 0
-  L1I_cache_total_prefetches: 0
-  L1I_cache_total_sw_prefetches: 0
-  L1I_cache_total_hw_prefetches: 0
-  L1I_cache_misses_per_transaction: 0
-  L1I_cache_misses_per_instruction: 0
-  L1I_cache_instructions_per_misses: NaN
-
-  L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-L2_cache cache stats: 
-  L2_cache_total_misses: 0
-  L2_cache_total_demand_misses: 0
-  L2_cache_total_prefetches: 0
-  L2_cache_total_sw_prefetches: 0
-  L2_cache_total_hw_prefetches: 0
-  L2_cache_misses_per_transaction: 0
-  L2_cache_misses_per_instruction: 0
-  L2_cache_instructions_per_misses: NaN
-
-  L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-
-Busy Controller Counts:
-L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  
-Directory-0:0  Directory-1:0  Directory-2:0  Directory-3:0  
-
-Busy Bank Count:0
-
-L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-All Non-Zero Cycle SW Prefetch Requests
-------------------------------------
-prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
-
-Resource Usage
---------------
-page_size: 4096
-user_time: 1
-system_time: 0
-page_reclaims: 23338
-page_faults: 0
-swaps: 0
-block_inputs: 0
-block_outputs: 640
-MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
-
-Network Stats
--------------
-
-switch_0_inlinks: 1
-switch_0_outlinks: 1
-links_utilized_percent_switch_0: 0
-  links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_1_inlinks: 1
-switch_1_outlinks: 1
-links_utilized_percent_switch_1: 0
-  links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_2_inlinks: 1
-switch_2_outlinks: 1
-links_utilized_percent_switch_2: 0
-  links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_3_inlinks: 1
-switch_3_outlinks: 1
-links_utilized_percent_switch_3: 0
-  links_utilized_percent_switch_3_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_4_inlinks: 1
-switch_4_outlinks: 1
-links_utilized_percent_switch_4: 0
-  links_utilized_percent_switch_4_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_5_inlinks: 1
-switch_5_outlinks: 1
-links_utilized_percent_switch_5: 0
-  links_utilized_percent_switch_5_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_6_inlinks: 1
-switch_6_outlinks: 1
-links_utilized_percent_switch_6: 0
-  links_utilized_percent_switch_6_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_7_inlinks: 1
-switch_7_outlinks: 1
-links_utilized_percent_switch_7: 0
-  links_utilized_percent_switch_7_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_8_inlinks: 4
-switch_8_outlinks: 1
-links_utilized_percent_switch_8: 0
-  links_utilized_percent_switch_8_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_9_inlinks: 4
-switch_9_outlinks: 1
-links_utilized_percent_switch_9: 0
-  links_utilized_percent_switch_9_link_0: 0 bw: 10000 base_latency: 1
-
-
-switch_10_inlinks: 2
-switch_10_outlinks: 2
-links_utilized_percent_switch_10: 0
-  links_utilized_percent_switch_10_link_0: 0 bw: 10000 base_latency: 1
-  links_utilized_percent_switch_10_link_1: 0 bw: 10000 base_latency: 1
-
-
-switch_11_inlinks: 1
-switch_11_outlinks: 4
-links_utilized_percent_switch_11: 0
-  links_utilized_percent_switch_11_link_0: 0 bw: 10000 base_latency: 1
-  links_utilized_percent_switch_11_link_1: 0 bw: 10000 base_latency: 1
-  links_utilized_percent_switch_11_link_2: 0 bw: 10000 base_latency: 1
-  links_utilized_percent_switch_11_link_3: 0 bw: 10000 base_latency: 1
-
-
-switch_12_inlinks: 1
-switch_12_outlinks: 4
-links_utilized_percent_switch_12: 0
-  links_utilized_percent_switch_12_link_0: 0 bw: 10000 base_latency: 1
-  links_utilized_percent_switch_12_link_1: 0 bw: 10000 base_latency: 1
-  links_utilized_percent_switch_12_link_2: 0 bw: 10000 base_latency: 1
-  links_utilized_percent_switch_12_link_3: 0 bw: 10000 base_latency: 1
-
-
-
-Chip Stats
-----------
-
- --- L1Cache ---
- - Event Counts -
-Load  0
-Ifetch  0
-Store  0
-L1_to_L2  0
-L2_to_L1D  0
-L2_to_L1I  0
-L2_Replacement  0
-Own_GETS  0
-Own_GET_INSTR  0
-Own_GETX  0
-Own_PUTX  0
-Other_GETS  0
-Other_GET_INSTR  0
-Other_GETX  0
-Other_PUTX  0
-Data  0
-
- - Transitions -
-NP  Load  0 <-- 
-NP  Ifetch  0 <-- 
-NP  Store  0 <-- 
-NP  Other_GETS  0 <-- 
-NP  Other_GET_INSTR  0 <-- 
-NP  Other_GETX  0 <-- 
-NP  Other_PUTX  0 <-- 
-
-I  Load  0 <-- 
-I  Ifetch  0 <-- 
-I  Store  0 <-- 
-I  L1_to_L2  0 <-- 
-I  L2_to_L1D  0 <-- 
-I  L2_to_L1I  0 <-- 
-I  L2_Replacement  0 <-- 
-I  Other_GETS  0 <-- 
-I  Other_GET_INSTR  0 <-- 
-I  Other_GETX  0 <-- 
-I  Other_PUTX  0 <-- 
-
-S  Load  0 <-- 
-S  Ifetch  0 <-- 
-S  Store  0 <-- 
-S  L1_to_L2  0 <-- 
-S  L2_to_L1D  0 <-- 
-S  L2_to_L1I  0 <-- 
-S  L2_Replacement  0 <-- 
-S  Other_GETS  0 <-- 
-S  Other_GET_INSTR  0 <-- 
-S  Other_GETX  0 <-- 
-S  Other_PUTX  0 <-- 
-
-O  Load  0 <-- 
-O  Ifetch  0 <-- 
-O  Store  0 <-- 
-O  L1_to_L2  0 <-- 
-O  L2_to_L1D  0 <-- 
-O  L2_to_L1I  0 <-- 
-O  L2_Replacement  0 <-- 
-O  Other_GETS  0 <-- 
-O  Other_GET_INSTR  0 <-- 
-O  Other_GETX  0 <-- 
-O  Other_PUTX  0 <-- 
-
-M  Load  0 <-- 
-M  Ifetch  0 <-- 
-M  Store  0 <-- 
-M  L1_to_L2  0 <-- 
-M  L2_to_L1D  0 <-- 
-M  L2_to_L1I  0 <-- 
-M  L2_Replacement  0 <-- 
-M  Other_GETS  0 <-- 
-M  Other_GET_INSTR  0 <-- 
-M  Other_GETX  0 <-- 
-M  Other_PUTX  0 <-- 
-
-IS_AD  Load  0 <-- 
-IS_AD  Ifetch  0 <-- 
-IS_AD  Store  0 <-- 
-IS_AD  L1_to_L2  0 <-- 
-IS_AD  L2_to_L1D  0 <-- 
-IS_AD  L2_to_L1I  0 <-- 
-IS_AD  L2_Replacement  0 <-- 
-IS_AD  Own_GETS  0 <-- 
-IS_AD  Own_GET_INSTR  0 <-- 
-IS_AD  Other_GETS  0 <-- 
-IS_AD  Other_GET_INSTR  0 <-- 
-IS_AD  Other_GETX  0 <-- 
-IS_AD  Other_PUTX  0 <-- 
-IS_AD  Data  0 <-- 
-
-IM_AD  Load  0 <-- 
-IM_AD  Ifetch  0 <-- 
-IM_AD  Store  0 <-- 
-IM_AD  L1_to_L2  0 <-- 
-IM_AD  L2_to_L1D  0 <-- 
-IM_AD  L2_to_L1I  0 <-- 
-IM_AD  L2_Replacement  0 <-- 
-IM_AD  Own_GETX  0 <-- 
-IM_AD  Other_GETS  0 <-- 
-IM_AD  Other_GET_INSTR  0 <-- 
-IM_AD  Other_GETX  0 <-- 
-IM_AD  Other_PUTX  0 <-- 
-IM_AD  Data  0 <-- 
-
-SM_AD  Load  0 <-- 
-SM_AD  Ifetch  0 <-- 
-SM_AD  Store  0 <-- 
-SM_AD  L1_to_L2  0 <-- 
-SM_AD  L2_to_L1D  0 <-- 
-SM_AD  L2_to_L1I  0 <-- 
-SM_AD  L2_Replacement  0 <-- 
-SM_AD  Own_GETX  0 <-- 
-SM_AD  Other_GETS  0 <-- 
-SM_AD  Other_GET_INSTR  0 <-- 
-SM_AD  Other_GETX  0 <-- 
-SM_AD  Other_PUTX  0 <-- 
-SM_AD  Data  0 <-- 
-
-OM_A  Load  0 <-- 
-OM_A  Ifetch  0 <-- 
-OM_A  Store  0 <-- 
-OM_A  L1_to_L2  0 <-- 
-OM_A  L2_to_L1D  0 <-- 
-OM_A  L2_to_L1I  0 <-- 
-OM_A  L2_Replacement  0 <-- 
-OM_A  Own_GETX  0 <-- 
-OM_A  Other_GETS  0 <-- 
-OM_A  Other_GET_INSTR  0 <-- 
-OM_A  Other_GETX  0 <-- 
-OM_A  Other_PUTX  0 <-- 
-OM_A  Data  0 <-- 
-
-IS_A  Load  0 <-- 
-IS_A  Ifetch  0 <-- 
-IS_A  Store  0 <-- 
-IS_A  L1_to_L2  0 <-- 
-IS_A  L2_to_L1D  0 <-- 
-IS_A  L2_to_L1I  0 <-- 
-IS_A  L2_Replacement  0 <-- 
-IS_A  Own_GETS  0 <-- 
-IS_A  Own_GET_INSTR  0 <-- 
-IS_A  Other_GETS  0 <-- 
-IS_A  Other_GET_INSTR  0 <-- 
-IS_A  Other_GETX  0 <-- 
-IS_A  Other_PUTX  0 <-- 
-
-IM_A  Load  0 <-- 
-IM_A  Ifetch  0 <-- 
-IM_A  Store  0 <-- 
-IM_A  L1_to_L2  0 <-- 
-IM_A  L2_to_L1D  0 <-- 
-IM_A  L2_to_L1I  0 <-- 
-IM_A  L2_Replacement  0 <-- 
-IM_A  Own_GETX  0 <-- 
-IM_A  Other_GETS  0 <-- 
-IM_A  Other_GET_INSTR  0 <-- 
-IM_A  Other_GETX  0 <-- 
-IM_A  Other_PUTX  0 <-- 
-
-SM_A  Load  0 <-- 
-SM_A  Ifetch  0 <-- 
-SM_A  Store  0 <-- 
-SM_A  L1_to_L2  0 <-- 
-SM_A  L2_to_L1D  0 <-- 
-SM_A  L2_to_L1I  0 <-- 
-SM_A  L2_Replacement  0 <-- 
-SM_A  Own_GETX  0 <-- 
-SM_A  Other_GETS  0 <-- 
-SM_A  Other_GET_INSTR  0 <-- 
-SM_A  Other_GETX  0 <-- 
-SM_A  Other_PUTX  0 <-- 
-
-MI_A  Load  0 <-- 
-MI_A  Ifetch  0 <-- 
-MI_A  Store  0 <-- 
-MI_A  L1_to_L2  0 <-- 
-MI_A  L2_to_L1D  0 <-- 
-MI_A  L2_to_L1I  0 <-- 
-MI_A  L2_Replacement  0 <-- 
-MI_A  Own_PUTX  0 <-- 
-MI_A  Other_GETS  0 <-- 
-MI_A  Other_GET_INSTR  0 <-- 
-MI_A  Other_GETX  0 <-- 
-MI_A  Other_PUTX  0 <-- 
-
-OI_A  Load  0 <-- 
-OI_A  Ifetch  0 <-- 
-OI_A  Store  0 <-- 
-OI_A  L1_to_L2  0 <-- 
-OI_A  L2_to_L1D  0 <-- 
-OI_A  L2_to_L1I  0 <-- 
-OI_A  L2_Replacement  0 <-- 
-OI_A  Own_PUTX  0 <-- 
-OI_A  Other_GETS  0 <-- 
-OI_A  Other_GET_INSTR  0 <-- 
-OI_A  Other_GETX  0 <-- 
-OI_A  Other_PUTX  0 <-- 
-
-II_A  Load  0 <-- 
-II_A  Ifetch  0 <-- 
-II_A  Store  0 <-- 
-II_A  L1_to_L2  0 <-- 
-II_A  L2_to_L1D  0 <-- 
-II_A  L2_to_L1I  0 <-- 
-II_A  L2_Replacement  0 <-- 
-II_A  Own_PUTX  0 <-- 
-II_A  Other_GETS  0 <-- 
-II_A  Other_GET_INSTR  0 <-- 
-II_A  Other_GETX  0 <-- 
-II_A  Other_PUTX  0 <-- 
-
-IS_D  Load  0 <-- 
-IS_D  Ifetch  0 <-- 
-IS_D  Store  0 <-- 
-IS_D  L1_to_L2  0 <-- 
-IS_D  L2_to_L1D  0 <-- 
-IS_D  L2_to_L1I  0 <-- 
-IS_D  L2_Replacement  0 <-- 
-IS_D  Other_GETS  0 <-- 
-IS_D  Other_GET_INSTR  0 <-- 
-IS_D  Other_GETX  0 <-- 
-IS_D  Other_PUTX  0 <-- 
-IS_D  Data  0 <-- 
-
-IS_D_I  Load  0 <-- 
-IS_D_I  Ifetch  0 <-- 
-IS_D_I  Store  0 <-- 
-IS_D_I  L1_to_L2  0 <-- 
-IS_D_I  L2_to_L1D  0 <-- 
-IS_D_I  L2_to_L1I  0 <-- 
-IS_D_I  L2_Replacement  0 <-- 
-IS_D_I  Other_GETS  0 <-- 
-IS_D_I  Other_GET_INSTR  0 <-- 
-IS_D_I  Other_GETX  0 <-- 
-IS_D_I  Other_PUTX  0 <-- 
-IS_D_I  Data  0 <-- 
-
-IM_D  Load  0 <-- 
-IM_D  Ifetch  0 <-- 
-IM_D  Store  0 <-- 
-IM_D  L1_to_L2  0 <-- 
-IM_D  L2_to_L1D  0 <-- 
-IM_D  L2_to_L1I  0 <-- 
-IM_D  L2_Replacement  0 <-- 
-IM_D  Other_GETS  0 <-- 
-IM_D  Other_GET_INSTR  0 <-- 
-IM_D  Other_GETX  0 <-- 
-IM_D  Other_PUTX  0 <-- 
-IM_D  Data  0 <-- 
-
-IM_D_O  Load  0 <-- 
-IM_D_O  Ifetch  0 <-- 
-IM_D_O  Store  0 <-- 
-IM_D_O  L1_to_L2  0 <-- 
-IM_D_O  L2_to_L1D  0 <-- 
-IM_D_O  L2_to_L1I  0 <-- 
-IM_D_O  L2_Replacement  0 <-- 
-IM_D_O  Other_GETS  0 <-- 
-IM_D_O  Other_GET_INSTR  0 <-- 
-IM_D_O  Other_GETX  0 <-- 
-IM_D_O  Other_PUTX  0 <-- 
-IM_D_O  Data  0 <-- 
-
-IM_D_I  Load  0 <-- 
-IM_D_I  Ifetch  0 <-- 
-IM_D_I  Store  0 <-- 
-IM_D_I  L1_to_L2  0 <-- 
-IM_D_I  L2_to_L1D  0 <-- 
-IM_D_I  L2_to_L1I  0 <-- 
-IM_D_I  L2_Replacement  0 <-- 
-IM_D_I  Other_GETS  0 <-- 
-IM_D_I  Other_GET_INSTR  0 <-- 
-IM_D_I  Other_GETX  0 <-- 
-IM_D_I  Other_PUTX  0 <-- 
-IM_D_I  Data  0 <-- 
-
-IM_D_OI  Load  0 <-- 
-IM_D_OI  Ifetch  0 <-- 
-IM_D_OI  Store  0 <-- 
-IM_D_OI  L1_to_L2  0 <-- 
-IM_D_OI  L2_to_L1D  0 <-- 
-IM_D_OI  L2_to_L1I  0 <-- 
-IM_D_OI  L2_Replacement  0 <-- 
-IM_D_OI  Other_GETS  0 <-- 
-IM_D_OI  Other_GET_INSTR  0 <-- 
-IM_D_OI  Other_GETX  0 <-- 
-IM_D_OI  Other_PUTX  0 <-- 
-IM_D_OI  Data  0 <-- 
-
-SM_D  Load  0 <-- 
-SM_D  Ifetch  0 <-- 
-SM_D  Store  0 <-- 
-SM_D  L1_to_L2  0 <-- 
-SM_D  L2_to_L1D  0 <-- 
-SM_D  L2_to_L1I  0 <-- 
-SM_D  L2_Replacement  0 <-- 
-SM_D  Other_GETS  0 <-- 
-SM_D  Other_GET_INSTR  0 <-- 
-SM_D  Other_GETX  0 <-- 
-SM_D  Other_PUTX  0 <-- 
-SM_D  Data  0 <-- 
-
-SM_D_O  Load  0 <-- 
-SM_D_O  Ifetch  0 <-- 
-SM_D_O  Store  0 <-- 
-SM_D_O  L1_to_L2  0 <-- 
-SM_D_O  L2_to_L1D  0 <-- 
-SM_D_O  L2_to_L1I  0 <-- 
-SM_D_O  L2_Replacement  0 <-- 
-SM_D_O  Other_GETS  0 <-- 
-SM_D_O  Other_GET_INSTR  0 <-- 
-SM_D_O  Other_GETX  0 <-- 
-SM_D_O  Other_PUTX  0 <-- 
-SM_D_O  Data  0 <-- 
-
- --- Directory ---
- - Event Counts -
-OtherAddress  0
-GETS  0
-GET_INSTR  0
-GETX  0
-PUTX_Owner  0
-PUTX_NotOwner  0
-
- - Transitions -
-C  OtherAddress  0 <-- 
-C  GETS  0 <-- 
-C  GET_INSTR  0 <-- 
-C  GETX  0 <-- 
-
-I  GETS  0 <-- 
-I  GET_INSTR  0 <-- 
-I  GETX  0 <-- 
-I  PUTX_NotOwner  0 <-- 
-
-S  GETS  0 <-- 
-S  GET_INSTR  0 <-- 
-S  GETX  0 <-- 
-S  PUTX_NotOwner  0 <-- 
-
-SS  GETS  0 <-- 
-SS  GET_INSTR  0 <-- 
-SS  GETX  0 <-- 
-SS  PUTX_NotOwner  0 <-- 
-
-OS  GETS  0 <-- 
-OS  GET_INSTR  0 <-- 
-OS  GETX  0 <-- 
-OS  PUTX_Owner  0 <-- 
-OS  PUTX_NotOwner  0 <-- 
-
-OSS  GETS  0 <-- 
-OSS  GET_INSTR  0 <-- 
-OSS  GETX  0 <-- 
-OSS  PUTX_Owner  0 <-- 
-OSS  PUTX_NotOwner  0 <-- 
-
-M  GETS  0 <-- 
-M  GET_INSTR  0 <-- 
-M  GETX  0 <-- 
-M  PUTX_Owner  0 <-- 
-M  PUTX_NotOwner  0 <-- 
-
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr
deleted file mode 100755
index 5854430da..000000000
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simerr
+++ /dev/null
@@ -1,41 +0,0 @@
-["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "4", "-m", "1", "-s", "1024"]
-print config: 1
-Creating new MessageBuffer for 0 0
-Creating new MessageBuffer for 0 1
-Creating new MessageBuffer for 0 2
-Creating new MessageBuffer for 0 3
-Creating new MessageBuffer for 0 4
-Creating new MessageBuffer for 0 5
-Creating new MessageBuffer for 1 0
-Creating new MessageBuffer for 1 1
-Creating new MessageBuffer for 1 2
-Creating new MessageBuffer for 1 3
-Creating new MessageBuffer for 1 4
-Creating new MessageBuffer for 1 5
-Creating new MessageBuffer for 2 0
-Creating new MessageBuffer for 2 1
-Creating new MessageBuffer for 2 2
-Creating new MessageBuffer for 2 3
-Creating new MessageBuffer for 2 4
-Creating new MessageBuffer for 2 5
-Creating new MessageBuffer for 3 0
-Creating new MessageBuffer for 3 1
-Creating new MessageBuffer for 3 2
-Creating new MessageBuffer for 3 3
-Creating new MessageBuffer for 3 4
-Creating new MessageBuffer for 3 5
-Creating new MessageBuffer for 4 0
-Creating new MessageBuffer for 4 1
-Creating new MessageBuffer for 4 2
-Creating new MessageBuffer for 4 3
-Creating new MessageBuffer for 4 4
-Creating new MessageBuffer for 4 5
-Creating new MessageBuffer for 5 0
-Creating new MessageBuffer for 5 1
-Creating new MessageBuffer for 5 2
-Creating new MessageBuffer for 5 3
-Creating new MessageBuffer for 5 4
-Creating new MessageBuffer for 5 5
-warn: Sockets disabled, not accepting gdb connections
-For more information see: http://www.m5sim.org/warn/d946bea6
-hack: be nice to actually delete the event here
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout
deleted file mode 100755
index 1acb8ba38..000000000
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/simout
+++ /dev/null
@@ -1,88 +0,0 @@
-M5 Simulator System
-
-Copyright (c) 2001-2008
-The Regents of The University of Michigan
-All Rights Reserved
-
-
-M5 compiled Jul  6 2009 11:07:18
-M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
-M5 started Jul  6 2009 11:11:25
-M5 executing on maize
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp-ruby
-Global frequency set at 1000000000000 ticks per second
-  Debug: Adding to filter: 'q' (Queue)
-info: Entering event queue @ 0.  Starting simulation...
-Init done
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 2 completed
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 3 completed
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2
-Iteration 4 completed
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 5 completed
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 6 completed
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 8 completed
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
-Iteration 10 completed
-PASSED :-)
-Exiting @ tick 87713500 because target called exit()
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt
deleted file mode 100644
index e24c8da34..000000000
--- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp-ruby/stats.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate                                  38506                       # Simulator instruction rate (inst/s)
-host_mem_usage                                1363292                       # Number of bytes of host memory used
-host_seconds                                    17.59                       # Real time elapsed on the host
-host_tick_rate                                4986293                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                      677340                       # Number of instructions simulated
-sim_seconds                                  0.000088                       # Number of seconds simulated
-sim_ticks                                    87713500                       # Number of ticks simulated
-system.cpu0.idle_fraction                    0.045871                       # Percentage of idle cycles
-system.cpu0.not_idle_fraction                0.954129                       # Percentage of non-idle cycles
-system.cpu0.numCycles                          173308                       # number of cpu cycles simulated
-system.cpu0.num_insts                          167334                       # Number of instructions executed
-system.cpu0.num_refs                            58537                       # Number of memory references
-system.cpu0.workload.PROG:num_syscalls             89                       # Number of system calls
-system.cpu1.idle_fraction                    0.046241                       # Percentage of idle cycles
-system.cpu1.not_idle_fraction                0.953759                       # Percentage of non-idle cycles
-system.cpu1.numCycles                          173307                       # number of cpu cycles simulated
-system.cpu1.num_insts                          167269                       # Number of instructions executed
-system.cpu1.num_refs                            55900                       # Number of memory references
-system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
-system.cpu2.numCycles                          175428                       # number of cpu cycles simulated
-system.cpu2.num_insts                          175339                       # Number of instructions executed
-system.cpu2.num_refs                            82398                       # Number of memory references
-system.cpu3.idle_fraction                    0.045506                       # Percentage of idle cycles
-system.cpu3.not_idle_fraction                0.954494                       # Percentage of non-idle cycles
-system.cpu3.numCycles                          173308                       # number of cpu cycles simulated
-system.cpu3.num_insts                          167398                       # Number of instructions executed
-system.cpu3.num_refs                            53394                       # Number of memory references
-
----------- End Simulation Statistics   ----------