diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2010-05-13 23:45:59 -0400 |
| commit | e63c73b45d688c7af7a1a3ed01dbde538c57acc2 (patch) | |
| tree | b10b8bbf9dd89f219c5c63ab9d2d745924935425 /tests/quick/40.m5threads-test-atomic | |
| parent | fc746c2268bfceded0014749cddd8234fa55a35a (diff) | |
| download | gem5-e63c73b45d688c7af7a1a3ed01dbde538c57acc2.tar.xz | |
BPRED: Update regressions for tournament predictor fix.
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic')
3 files changed, 1172 insertions, 1172 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 2fffc58e2..e7279bca8 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -317,7 +317,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 1d66e4129..e80cf75e8 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -5,34 +5,34 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 25 2010 03:11:27 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:38:02 -M5 executing on SC2B0619 +M5 compiled May 12 2010 02:45:56 +M5 revision 3f044cf767ee 7080 default qtip bp_regress.patch tip +M5 started May 12 2010 02:45:58 +M5 executing on zizzer command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 1, Thread 3] Got lock [Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 Iteration 1 completed -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 3] Got lock [Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 @@ -41,26 +41,26 @@ Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 Iteration 4 completed -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 Iteration 5 completed -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 7, Thread 2] Got lock [Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 Iteration 7 completed [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 @@ -69,19 +69,19 @@ Iteration 7 completed [Iteration 8, Thread 3] Got lock [Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 Iteration 9 completed -[Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 220484500 because target called exit() +Exiting @ tick 217002500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 75d6c02bb..a59d4f21a 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,943 +1,942 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 38759 # Simulator instruction rate (inst/s) -host_mem_usage 200852 # Number of bytes of host memory used -host_seconds 11.32 # Real time elapsed on the host -host_tick_rate 19469095 # Simulator tick rate (ticks/s) +host_inst_rate 71817 # Simulator instruction rate (inst/s) +host_mem_usage 214292 # Number of bytes of host memory used +host_seconds 6.05 # Real time elapsed on the host +host_tick_rate 35890036 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 438923 # Number of instructions simulated -sim_seconds 0.000220 # Number of seconds simulated -sim_ticks 220484500 # Number of ticks simulated +sim_insts 434213 # Number of instructions simulated +sim_seconds 0.000217 # Number of seconds simulated +sim_ticks 217002500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 54549 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 70955 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 52073 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 66680 # Number of BTB lookups system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 31037 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 79925 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 79925 # Number of BP lookups +system.cpu0.BPredUnit.condIncorrect 30422 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 81408 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 81408 # Number of BP lookups system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 25657 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 567 # number cycles where commit BW limit reached +system.cpu0.commit.COM:branches 25190 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 578 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 355685 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.364783 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 0.822342 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 347008 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.368821 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 0.833965 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0-1 269749 75.84% 75.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1-2 56588 15.91% 91.75% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2-3 24519 6.89% 98.64% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3-4 1287 0.36% 99.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4-5 786 0.22% 99.23% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5-6 567 0.16% 99.38% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6-7 1608 0.45% 99.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 567 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0-1 262750 75.72% 75.72% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1-2 55494 15.99% 91.71% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2-3 23803 6.86% 98.57% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3-4 1293 0.37% 98.94% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4-5 820 0.24% 99.18% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5-6 559 0.16% 99.34% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6-7 1671 0.48% 99.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7-8 40 0.01% 99.83% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 578 0.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 355685 # Number of insts commited each cycle -system.cpu0.commit.COM:count 129748 # Number of instructions committed -system.cpu0.commit.COM:loads 30551 # Number of loads committed -system.cpu0.commit.COM:membars 8310 # Number of memory barriers committed -system.cpu0.commit.COM:refs 41937 # Number of memory references committed +system.cpu0.commit.COM:committed_per_cycle::total 347008 # Number of insts commited each cycle +system.cpu0.commit.COM:count 127984 # Number of instructions committed +system.cpu0.commit.COM:loads 30137 # Number of loads committed +system.cpu0.commit.COM:membars 7796 # Number of memory barriers committed +system.cpu0.commit.COM:refs 41570 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 31037 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 129748 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 9029 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 140741 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 104996 # Number of Instructions Simulated -system.cpu0.committedInsts_total 104996 # Number of Instructions Simulated -system.cpu0.cpi 3.832270 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.832270 # CPI: Total CPI of All Threads -system.cpu0.dcache.ReadReq_accesses 29224 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 18192.118227 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 15806.818182 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 29021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 3693000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.006946 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 203 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 2782000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.006022 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 176 # number of ReadReq MSHR misses -system.cpu0.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_avg_miss_latency 21093.220339 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 22239.583333 # average SwapReq mshr miss latency +system.cpu0.commit.branchMispredicts 30422 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 127984 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 8513 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 104211 # Number of Instructions Simulated +system.cpu0.committedInsts_total 104211 # Number of Instructions Simulated +system.cpu0.cpi 3.794734 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.794734 # CPI: Total CPI of All Threads +system.cpu0.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_hits 28373 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 4031500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate 0.007312 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses 209 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 3023000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.006088 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses +system.cpu0.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_avg_miss_latency 21973.684211 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 23510.869565 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu0.dcache.SwapReq_miss_latency 1244500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_rate 0.808219 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_misses 59 # number of SwapReq misses +system.cpu0.dcache.SwapReq_miss_latency 1252500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_rate 0.802817 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_misses 57 # number of SwapReq misses system.cpu0.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits -system.cpu0.dcache.SwapReq_mshr_miss_latency 1067500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.657534 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_misses 48 # number of SwapReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 11313 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 23258.064516 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 14768.867925 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 11189 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 2884000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.010961 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 124 # number of WriteReq misses +system.cpu0.dcache.SwapReq_mshr_miss_latency 1081500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.647887 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu0.dcache.WriteReq_accesses 11362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency 24003.906250 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 15831.818182 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_hits 11234 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 3072500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate 0.011266 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses 128 # number of WriteReq misses system.cpu0.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 1565500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 106 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_miss_latency 1741500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009681 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_misses 110 # number of WriteReq MSHR misses system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 735.966667 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 708.483871 # Average number of references to valid blocks. system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 40537 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 20113.149847 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 40210 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 6577000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.008067 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 327 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 4347500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.006957 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 282 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_accesses 39944 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency +system.cpu0.dcache.demand_hits 39607 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 7104000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate 0.008437 # miss rate for demand accesses +system.cpu0.dcache.demand_misses 337 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 4764500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate 0.007110 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_misses 284 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.055235 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 28.280349 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 40537 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 20113.149847 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 15416.666667 # average overall mshr miss latency +system.cpu0.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context +system.cpu0.dcache.overall_accesses 39944 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 40210 # number of overall hits -system.cpu0.dcache.overall_miss_latency 6577000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.008067 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 327 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 4347500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.006957 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 282 # number of overall MSHR misses +system.cpu0.dcache.overall_hits 39607 # number of overall hits +system.cpu0.dcache.overall_miss_latency 7104000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate 0.008437 # miss rate for overall accesses +system.cpu0.dcache.overall_misses 337 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 53 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 4764500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate 0.007110 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_misses 284 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu0.dcache.sampled_refs 31 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 28.280349 # Cycle average of tags in use -system.cpu0.dcache.total_refs 22079 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 29.152957 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21963 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.dcache.writebacks 1 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 31385 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:DecodedInsts 367055 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 175688 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 148454 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 34938 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:UnblockCycles 158 # Number of cycles decode is unblocking -system.cpu0.fetch.Branches 79925 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 83600 # Number of cache lines fetched -system.cpu0.fetch.Cycles 244044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 9987 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 413648 # Number of instructions fetch has processed -system.cpu0.fetch.SquashCycles 31188 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.198634 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 83600 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 54549 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 1.028021 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 399788 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.034668 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.929402 # Number of instructions fetched each cycle (Total) +system.cpu0.decode.DECODE:BlockedCycles 31861 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:DecodedInsts 361505 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 170760 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 144226 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 34255 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking +system.cpu0.fetch.Branches 81408 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 81347 # Number of cache lines fetched +system.cpu0.fetch.Cycles 236913 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 412447 # Number of instructions fetch has processed +system.cpu0.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.205860 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 1.042974 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0-1 239369 59.87% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1-2 86666 21.68% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2-3 18970 4.75% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3-4 18363 4.59% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4-5 2993 0.75% 91.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5-6 13233 3.31% 94.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6-7 1665 0.42% 95.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7-8 2406 0.60% 95.97% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 16123 4.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0-1 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1-2 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2-3 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3-4 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4-5 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5-6 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6-7 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7-8 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 399788 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses 83600 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 14035.763411 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11552.755906 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 82873 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 10204000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.008696 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 727 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 7336000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.007596 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 635 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits 80599 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 14184500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate 0.009195 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses 748 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 116 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 10114500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate 0.007769 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_misses 632 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 130.508661 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.avg_refs 127.530063 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 83600 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 14035.763411 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency -system.cpu0.icache.demand_hits 82873 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 10204000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.008696 # miss rate for demand accesses -system.cpu0.icache.demand_misses 727 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 7336000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.007596 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_accesses 81347 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency +system.cpu0.icache.demand_hits 80599 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 14184500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate 0.009195 # miss rate for demand accesses +system.cpu0.icache.demand_misses 748 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 116 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 10114500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate 0.007769 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses 632 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.187347 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 95.921890 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 83600 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 14035.763411 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11552.755906 # average overall mshr miss latency +system.cpu0.icache.occ_%::0 0.191179 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::0 97.883584 # Average occupied blocks per context +system.cpu0.icache.overall_accesses 81347 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 82873 # number of overall hits -system.cpu0.icache.overall_miss_latency 10204000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.008696 # miss rate for overall accesses -system.cpu0.icache.overall_misses 727 # number of overall misses -system.cpu0.icache.overall_mshr_hits 92 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 7336000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.007596 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 635 # number of overall MSHR misses +system.cpu0.icache.overall_hits 80599 # number of overall hits +system.cpu0.icache.overall_miss_latency 14184500 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate 0.009195 # miss rate for overall accesses +system.cpu0.icache.overall_misses 748 # number of overall misses +system.cpu0.icache.overall_mshr_hits 116 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 10114500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate 0.007769 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses 632 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 524 # number of replacements -system.cpu0.icache.sampled_refs 635 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 522 # number of replacements +system.cpu0.icache.sampled_refs 632 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 95.921890 # Cycle average of tags in use -system.cpu0.icache.total_refs 82873 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 97.883584 # Cycle average of tags in use +system.cpu0.icache.total_refs 80599 # Total number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idleCycles 2585 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 37656 # Number of branches executed -system.cpu0.iew.EXEC:nop 48476 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.417965 # Inst execution rate -system.cpu0.iew.EXEC:refs 49837 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 13176 # Number of stores executed +system.cpu0.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 37149 # Number of branches executed +system.cpu0.iew.EXEC:nop 47058 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.419532 # Inst execution rate +system.cpu0.iew.EXEC:refs 49104 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 13043 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 81944 # num instructions consuming a value -system.cpu0.iew.WB:count 164449 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.932149 # average fanout of values written-back +system.cpu0.iew.WB:consumers 81150 # num instructions consuming a value +system.cpu0.iew.WB:count 162295 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.931855 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 76384 # num instructions producing a value -system.cpu0.iew.WB:rate 0.408698 # insts written-back per cycle -system.cpu0.iew.WB:sent 164672 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 31697 # Number of branch mispredicts detected at execute +system.cpu0.iew.WB:producers 75620 # num instructions producing a value +system.cpu0.iew.WB:rate 0.410403 # insts written-back per cycle +system.cpu0.iew.WB:sent 162544 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute system.cpu0.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 41051 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 9374 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 4077 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 22447 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 270509 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 36661 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 34703 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 168178 # Number of executed instructions +system.cpu0.iew.iewDispLoadInsts 40176 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 9384 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 3614 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 22433 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 266034 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 36061 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 34221 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 165905 # Number of executed instructions system.cpu0.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 34938 # Number of cycles IEW is squashing +system.cpu0.iew.iewSquashCycles 34255 # Number of cycles IEW is squashing system.cpu0.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 7417 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.forwLoads 7459 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 646 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.memOrderViolation 698 # Number of memory ordering violations system.cpu0.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 10500 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 11061 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 646 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 856 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 30841 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.260942 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.260942 # IPC: Total IPC of All Threads +system.cpu0.iew.lsq.thread.0.squashedLoads 10039 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 11000 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 698 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.263523 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.263523 # IPC: Total IPC of All Threads system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 142871 70.42% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.42% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 46166 22.76% 93.18% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13844 6.82% 100.00% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.63% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 45052 22.51% 93.14% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 13735 6.86% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 202881 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 200126 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.000904 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 23 13.29% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 11 6.36% 19.65% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 139 80.35% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 19 10.50% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.50% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 17 9.39% 19.89% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 399788 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.507471 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.960639 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0-1 279763 69.98% 69.98% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1-2 72065 18.03% 88.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2-3 24983 6.25% 94.25% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14756 3.69% 97.94% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5406 1.35% 99.30% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2153 0.54% 99.83% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6-7 473 0.12% 99.95% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7-8 157 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 32 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0-1 272942 69.93% 69.93% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1-2 69416 17.79% 87.72% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2-3 25173 6.45% 94.16% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3-4 14490 3.71% 97.88% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4-5 5424 1.39% 99.27% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5-6 2186 0.56% 99.83% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6-7 485 0.12% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7-8 162 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 28 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 399788 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.504211 # Inst issue rate -system.cpu0.iq.iqInstsAdded 204299 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 202881 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 17734 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 79448 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.506068 # Inst issue rate +system.cpu0.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 200126 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 77302 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu0.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 8705 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 34402 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.memDep0.conflictingLoads 7616 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 83 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 41051 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 22447 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 402373 # number of cpu cycles simulated -system.cpu0.rename.RENAME:CommittedMaps 87918 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IdleCycles 188663 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:RenameLookups 464430 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 298607 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 213629 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 135723 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 34938 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 563 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 125711 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 30736 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 9619 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 36235 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 9747 # count of temporary serializing insts renamed -system.cpu0.timesIdled 284 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.iq.iqSquashedNonSpecRemoved 8735 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 33615 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.memDep0.conflictingLoads 7669 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 92 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 395453 # number of cpu cycles simulated +system.cpu0.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle +system.cpu0.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 293451 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 211386 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 131636 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 34255 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 645 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 123786 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 31130 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 9653 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 36749 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 9784 # count of temporary serializing insts renamed +system.cpu0.timesIdled 292 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 53615 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 73516 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 48405 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 65841 # Number of BTB lookups system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 30904 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 87311 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 87311 # Number of BP lookups +system.cpu1.BPredUnit.condIncorrect 32660 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 82266 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 82266 # Number of BP lookups system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 25648 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 570 # number cycles where commit BW limit reached +system.cpu1.commit.COM:branches 25082 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 576 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 355192 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.364749 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 0.823293 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 346536 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.381828 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 0.836481 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0-1 269483 75.87% 75.87% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1-2 56385 15.87% 91.74% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2-3 24471 6.89% 98.63% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3-4 1296 0.36% 99.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4-5 793 0.22% 99.22% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5-6 569 0.16% 99.38% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6-7 1611 0.45% 99.84% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 570 0.16% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0-1 257870 74.41% 74.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1-2 60023 17.32% 91.73% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2-3 23680 6.83% 98.57% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3-4 1288 0.37% 98.94% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4-5 802 0.23% 99.17% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5-6 567 0.16% 99.33% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6-7 1691 0.49% 99.82% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7-8 39 0.01% 99.83% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 576 0.17% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 355192 # Number of insts commited each cycle -system.cpu1.commit.COM:count 129556 # Number of instructions committed -system.cpu1.commit.COM:loads 30466 # Number of loads committed -system.cpu1.commit.COM:membars 8390 # Number of memory barriers committed -system.cpu1.commit.COM:refs 41763 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 346536 # Number of insts commited each cycle +system.cpu1.commit.COM:count 132317 # Number of instructions committed +system.cpu1.commit.COM:loads 32415 # Number of loads committed +system.cpu1.commit.COM:membars 5314 # Number of memory barriers committed +system.cpu1.commit.COM:refs 46218 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 30904 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 129556 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 9104 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 142883 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 104728 # Number of Instructions Simulated -system.cpu1.committedInsts_total 104728 # Number of Instructions Simulated -system.cpu1.cpi 3.839040 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 3.839040 # CPI: Total CPI of All Threads -system.cpu1.dcache.ReadReq_accesses 29199 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 17894.736842 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 15858.433735 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 29009 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 3400000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.006507 # miss rate for ReadReq accesses +system.cpu1.commit.branchMispredicts 32660 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 132317 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 6025 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 111128 # Number of Instructions Simulated +system.cpu1.committedInsts_total 111128 # Number of Instructions Simulated +system.cpu1.cpi 3.555675 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 3.555675 # CPI: Total CPI of All Threads +system.cpu1.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_hits 28295 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 3169000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate 0.006670 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_misses 190 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 24 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 2632500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.005685 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 166 # number of ReadReq MSHR misses -system.cpu1.dcache.SwapReq_accesses 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_avg_miss_latency 22592.592593 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 24604.651163 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_miss_latency 1220000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_rate 0.794118 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_misses 54 # number of SwapReq misses -system.cpu1.dcache.SwapReq_mshr_hits 11 # number of SwapReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_miss_latency 1058000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.632353 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_misses 43 # number of SwapReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 11229 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 23876.984127 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15889.908257 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 11103 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 3008500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.011221 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 126 # number of WriteReq misses +system.cpu1.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 2299000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.005441 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses 155 # number of ReadReq MSHR misses +system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_avg_miss_latency 22773.584906 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 22782.608696 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_miss_latency 1207000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_rate 0.815385 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_misses 53 # number of SwapReq misses +system.cpu1.dcache.SwapReq_mshr_hits 7 # number of SwapReq MSHR hits +system.cpu1.dcache.SwapReq_mshr_miss_latency 1048000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.707692 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu1.dcache.WriteReq_accesses 13738 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency 22585.271318 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 14535.714286 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_hits 13609 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 2913500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate 0.009390 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses 129 # number of WriteReq misses system.cpu1.dcache.WriteReq_mshr_hits 17 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 1732000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.009707 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 109 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_miss_latency 1628000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.008153 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses 112 # number of WriteReq MSHR misses system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 709.516129 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 810.166667 # Average number of references to valid blocks. system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 40428 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 20280.063291 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 40112 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 6408500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.007816 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 316 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 4364500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.006802 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_accesses 42223 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency +system.cpu1.dcache.demand_hits 41904 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 6082500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate 0.007555 # miss rate for demand accesses +system.cpu1.dcache.demand_misses 319 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 52 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 3927000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate 0.006324 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.053563 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 27.424102 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 40428 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 20280.063291 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 15870.909091 # average overall mshr miss latency +system.cpu1.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses 42223 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 40112 # number of overall hits -system.cpu1.dcache.overall_miss_latency 6408500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.007816 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 316 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 4364500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.006802 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 275 # number of overall MSHR misses +system.cpu1.dcache.overall_hits 41904 # number of overall hits +system.cpu1.dcache.overall_miss_latency 6082500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate 0.007555 # miss rate for overall accesses +system.cpu1.dcache.overall_misses 319 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 52 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 3927000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate 0.006324 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 27.424102 # Cycle average of tags in use -system.cpu1.dcache.total_refs 21995 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 28.067737 # Cycle average of tags in use +system.cpu1.dcache.total_refs 24305 # Total number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 31080 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:DecodedInsts 370792 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 175773 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 148188 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 35250 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:BlockedCycles 35593 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:DecodedInsts 394229 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 164873 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 145919 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 36967 # Number of cycles decode is squashing system.cpu1.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking -system.cpu1.fetch.Branches 87311 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 83559 # Number of cache lines fetched -system.cpu1.fetch.Cycles 243794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 9908 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 428254 # Number of instructions fetch has processed -system.cpu1.fetch.SquashCycles 31054 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.217162 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 83559 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 53615 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 1.065163 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 399545 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.071854 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.991830 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.Branches 82266 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 80954 # Number of cache lines fetched +system.cpu1.fetch.Cycles 235714 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 435938 # Number of instructions fetch has processed +system.cpu1.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.208197 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 1.103263 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0-1 239335 59.90% 59.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1-2 86108 21.55% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2-3 18621 4.66% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3-4 13625 3.41% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4-5 2965 0.74% 90.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5-6 17436 4.36% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6-7 2130 0.53% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7-8 2391 0.60% 95.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 16934 4.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0-1 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1-2 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2-3 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3-4 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4-5 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5-6 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6-7 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7-8 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 399545 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses 83559 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 13800.273598 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11301.412873 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 82828 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 10088000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.008748 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 731 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 7199000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.007623 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 637 # number of ReadReq MSHR misses +system.cpu1.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits 80218 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 10255000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate 0.009092 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses 736 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 7339500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate 0.007893 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses 639 # number of ReadReq MSHR misses system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 130.028257 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 125.536776 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 83559 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 13800.273598 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency -system.cpu1.icache.demand_hits 82828 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 10088000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.008748 # miss rate for demand accesses -system.cpu1.icache.demand_misses 731 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 94 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 7199000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.007623 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 637 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_accesses 80954 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency +system.cpu1.icache.demand_hits 80218 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 10255000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate 0.009092 # miss rate for demand accesses +system.cpu1.icache.demand_misses 736 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 7339500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate 0.007893 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses 639 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.183643 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 94.025224 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 83559 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 13800.273598 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11301.412873 # average overall mshr miss latency +system.cpu1.icache.occ_%::0 0.188794 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 96.662446 # Average occupied blocks per context +system.cpu1.icache.overall_accesses 80954 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 82828 # number of overall hits -system.cpu1.icache.overall_miss_latency 10088000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.008748 # miss rate for overall accesses -system.cpu1.icache.overall_misses 731 # number of overall misses -system.cpu1.icache.overall_mshr_hits 94 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 7199000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.007623 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 637 # number of overall MSHR misses +system.cpu1.icache.overall_hits 80218 # number of overall hits +system.cpu1.icache.overall_miss_latency 10255000 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate 0.009092 # miss rate for overall accesses +system.cpu1.icache.overall_misses 736 # number of overall misses +system.cpu1.icache.overall_mshr_hits 97 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 7339500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate 0.007893 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses 639 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 525 # number of replacements -system.cpu1.icache.sampled_refs 637 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 527 # number of replacements +system.cpu1.icache.sampled_refs 639 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 94.025224 # Cycle average of tags in use -system.cpu1.icache.total_refs 82828 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 96.662446 # Cycle average of tags in use +system.cpu1.icache.total_refs 80218 # Total number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idleCycles 2510 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 37542 # Number of branches executed -system.cpu1.iew.EXEC:nop 48922 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.416853 # Inst execution rate -system.cpu1.iew.EXEC:refs 49631 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 13081 # Number of stores executed +system.cpu1.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 39408 # Number of branches executed +system.cpu1.iew.EXEC:nop 47237 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.449348 # Inst execution rate +system.cpu1.iew.EXEC:refs 53769 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 15425 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 81643 # num instructions consuming a value -system.cpu1.iew.WB:count 163892 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.931911 # average fanout of values written-back +system.cpu1.iew.WB:consumers 88234 # num instructions consuming a value +system.cpu1.iew.WB:count 173934 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.937246 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 76084 # num instructions producing a value -system.cpu1.iew.WB:rate 0.407636 # insts written-back per cycle -system.cpu1.iew.WB:sent 164117 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 31560 # Number of branch mispredicts detected at execute +system.cpu1.iew.WB:producers 82697 # num instructions producing a value +system.cpu1.iew.WB:rate 0.440189 # insts written-back per cycle +system.cpu1.iew.WB:sent 174194 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 41822 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 9263 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 4013 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 22260 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 272458 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 36550 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 35100 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 167598 # Number of executed instructions +system.cpu1.iew.iewDispLoadInsts 43341 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 11749 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 3545 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 27172 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 284714 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 38344 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 36975 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 177553 # Number of executed instructions system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 35250 # Number of cycles IEW is squashing +system.cpu1.iew.iewSquashCycles 36967 # Number of cycles IEW is squashing system.cpu1.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 7331 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.forwLoads 9839 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 641 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.memOrderViolation 701 # Number of memory ordering violations system.cpu1.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 11356 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 10963 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 641 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 844 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 30716 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.260482 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.260482 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.squashedLoads 10926 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 13369 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 701 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.281241 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.281241 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 142808 70.45% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.45% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 46141 22.76% 93.22% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 13749 6.78% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.57% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 44868 20.91% 92.48% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 16122 7.52% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 202698 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.000853 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 214528 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.000867 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 23 13.29% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 13.29% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 11 6.36% 19.65% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 139 80.35% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 399545 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.507322 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.960841 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0-1 279804 70.03% 70.03% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1-2 71581 17.92% 87.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2-3 25282 6.33% 94.27% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3-4 14650 3.67% 97.94% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.36% 99.30% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2146 0.54% 99.83% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6-7 473 0.12% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7-8 157 0.04% 99.99% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 32 0.01% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0-1 270914 69.00% 69.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1-2 66150 16.85% 85.85% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2-3 30383 7.74% 93.59% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3-4 16859 4.29% 97.88% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4-5 5420 1.38% 99.26% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5-6 2202 0.56% 99.83% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6-7 491 0.13% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7-8 161 0.04% 99.99% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 399545 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.504155 # Inst issue rate -system.cpu1.iq.iqInstsAdded 205352 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 202698 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 18184 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 81269 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 9080 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 37464 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.memDep0.conflictingLoads 8438 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 93 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 41822 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 22260 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 402055 # number of cpu cycles simulated -system.cpu1.rename.RENAME:CommittedMaps 87658 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IdleCycles 188598 # Number of cycles rename is idle +system.cpu1.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.542923 # Inst issue rate +system.cpu1.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 214528 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 86635 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 11566 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 36678 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.memDep0.conflictingLoads 10938 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 96 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 395135 # number of cpu cycles simulated +system.cpu1.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:RenameLookups 466261 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 302877 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 213560 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 135600 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 35250 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 564 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 125902 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 30430 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 9493 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 36017 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 9618 # count of temporary serializing insts renamed -system.cpu1.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.rename.RENAME:RenameLookups 494732 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 312015 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 231166 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 130989 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 36967 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 619 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 136540 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 34885 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 11999 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 46061 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 12120 # count of temporary serializing insts renamed +system.cpu1.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.BTBHits 44906 # Number of BTB hits -system.cpu2.BPredUnit.BTBLookups 70035 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 44089 # Number of BTB hits +system.cpu2.BPredUnit.BTBLookups 68672 # Number of BTB lookups system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu2.BPredUnit.condIncorrect 43027 # Number of conditional branches incorrect -system.cpu2.BPredUnit.condPredicted 71789 # Number of conditional branches predicted -system.cpu2.BPredUnit.lookups 71789 # Number of BP lookups +system.cpu2.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect +system.cpu2.BPredUnit.condPredicted 70853 # Number of conditional branches predicted +system.cpu2.BPredUnit.lookups 70853 # Number of BP lookups system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu2.commit.COM:branches 23667 # Number of branches committed -system.cpu2.commit.COM:bw_lim_events 171 # number cycles where commit BW limit reached +system.cpu2.commit.COM:branches 23275 # Number of branches committed +system.cpu2.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached system.cpu2.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.commit.COM:committed_per_cycle::samples 377940 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::mean 0.368394 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::stdev 0.672472 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::0-1 268475 71.04% 71.04% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::1-2 84750 22.42% 93.46% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::2-3 22813 6.04% 99.50% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::3-4 683 0.18% 99.68% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::4-5 329 0.09% 99.76% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::5-6 229 0.06% 99.83% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::6-7 453 0.12% 99.94% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::7-8 37 0.01% 99.95% # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::8 171 0.05% 100.00% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::0-1 264099 71.08% 71.08% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::1-2 83154 22.38% 93.46% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::2-3 22390 6.03% 99.48% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::3-4 687 0.18% 99.67% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::4-5 334 0.09% 99.76% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::5-6 230 0.06% 99.82% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::6-7 452 0.12% 99.94% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::7-8 34 0.01% 99.95% # Number of insts commited each cycle +system.cpu2.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.COM:committed_per_cycle::total 377940 # Number of insts commited each cycle -system.cpu2.commit.COM:count 139231 # Number of instructions committed -system.cpu2.commit.COM:loads 42546 # Number of loads committed +system.cpu2.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle +system.cpu2.commit.COM:count 136879 # Number of instructions committed +system.cpu2.commit.COM:loads 41762 # Number of loads committed system.cpu2.commit.COM:membars 84 # Number of memory barriers committed -system.cpu2.commit.COM:refs 64325 # Number of memory references committed +system.cpu2.commit.COM:refs 63149 # Number of memory references committed system.cpu2.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.branchMispredicts 43027 # The number of times a branch was mispredicted -system.cpu2.commit.commitCommittedInsts 139231 # The number of committed instructions +system.cpu2.commit.branchMispredicts 42322 # The number of times a branch was mispredicted +system.cpu2.commit.commitCommittedInsts 136879 # The number of committed instructions system.cpu2.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.commitSquashedInsts 182418 # The number of squashed insts skipped by commit -system.cpu2.committedInsts 118749 # Number of Instructions Simulated -system.cpu2.committedInsts_total 118749 # Number of Instructions Simulated -system.cpu2.cpi 3.713463 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.713463 # CPI: Total CPI of All Threads -system.cpu2.dcache.ReadReq_accesses 24971 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 30599.025974 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 23979.820628 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 24663 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 9424500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.012334 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 308 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_miss_latency 5347500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.008930 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 223 # number of ReadReq MSHR misses +system.cpu2.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit +system.cpu2.committedInsts 116789 # Number of Instructions Simulated +system.cpu2.committedInsts_total 116789 # Number of Instructions Simulated +system.cpu2.cpi 3.716155 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.716155 # CPI: Total CPI of All Threads +system.cpu2.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_hits 24347 # number of ReadReq hits +system.cpu2.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_misses 318 # number of ReadReq misses +system.cpu2.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses system.cpu2.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_avg_miss_latency 15538.461538 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 12538.461538 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 15653.846154 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 12653.846154 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu2.dcache.SwapReq_miss_latency 404000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency 407000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu2.dcache.SwapReq_mshr_miss_latency 326000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 329000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 21737 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 45735.701906 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 39151.515152 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 21160 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 26389500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.026545 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_hits 20768 # number of WriteReq hits +system.cpu2.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_misses 577 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_hits 379 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_miss_latency 7752000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009109 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 198 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses system.cpu2.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 168.806818 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 162.931818 # Average number of references to valid blocks. system.cpu2.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 46708 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 40467.796610 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 45823 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 35814000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.018948 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 885 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 464 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 13099500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.009013 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 421 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_accesses 46010 # number of demand (read+write) accesses +system.cpu2.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency +system.cpu2.dcache.demand_hits 45115 # number of demand (read+write) hits +system.cpu2.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses +system.cpu2.dcache.demand_misses 895 # number of demand (read+write) misses +system.cpu2.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.285109 # Average percentage of cache occupancy -system.cpu2.dcache.occ_%::1 -0.006965 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 145.975885 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -3.566137 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 46708 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 40467.796610 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 31115.201900 # average overall mshr miss latency +system.cpu2.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy +system.cpu2.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context +system.cpu2.dcache.overall_accesses 46010 # number of overall (read+write) accesses +system.cpu2.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 45823 # number of overall hits -system.cpu2.dcache.overall_miss_latency 35814000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.018948 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 885 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 464 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 13099500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.009013 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 421 # number of overall MSHR misses +system.cpu2.dcache.overall_hits 45115 # number of overall hits +system.cpu2.dcache.overall_miss_latency 36067000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses +system.cpu2.dcache.overall_misses 895 # number of overall misses +system.cpu2.dcache.overall_mshr_hits 467 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_misses 428 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.dcache.replacements 10 # number of replacements system.cpu2.dcache.sampled_refs 176 # Sample count of references to valid blocks. system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 142.409748 # Cycle average of tags in use -system.cpu2.dcache.total_refs 29710 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 141.792519 # Cycle average of tags in use +system.cpu2.dcache.total_refs 28676 # Total number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.dcache.writebacks 6 # number of writebacks -system.cpu2.decode.DECODE:BlockedCycles 54269 # Number of cycles decode is blocked -system.cpu2.decode.DECODE:DecodedInsts 458617 # Number of instructions handled by decode -system.cpu2.decode.DECODE:IdleCycles 166605 # Number of cycles decode is idle -system.cpu2.decode.DECODE:RunCycles 156987 # Number of cycles decode is running -system.cpu2.decode.DECODE:SquashCycles 44866 # Number of cycles decode is squashing -system.cpu2.decode.DECODE:UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu2.fetch.Branches 71789 # Number of branches that fetch encountered -system.cpu2.fetch.CacheLines 88443 # Number of cache lines fetched -system.cpu2.fetch.Cycles 246728 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.IcacheSquashes 21058 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.Insts 464576 # Number of instructions fetch has processed -system.cpu2.fetch.SquashCycles 43179 # Number of cycles fetch has spent squashing -system.cpu2.fetch.branchRate 0.162798 # Number of branch fetches per cycle -system.cpu2.fetch.icacheStallCycles 88443 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.predictedBranches 44906 # Number of branches that fetch has predicted taken -system.cpu2.fetch.rate 1.053532 # Number of inst fetches per cycle -system.cpu2.fetch.rateDist::samples 422806 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.098792 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.122739 # Number of instructions fetched each cycle (Total) +system.cpu2.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked +system.cpu2.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode +system.cpu2.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle +system.cpu2.decode.DECODE:RunCycles 154431 # Number of cycles decode is running +system.cpu2.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing +system.cpu2.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking +system.cpu2.fetch.Branches 70853 # Number of branches that fetch encountered +system.cpu2.fetch.CacheLines 87025 # Number of cache lines fetched +system.cpu2.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.Insts 457882 # Number of instructions fetch has processed +system.cpu2.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing +system.cpu2.fetch.branchRate 0.163254 # Number of branch fetches per cycle +system.cpu2.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken +system.cpu2.fetch.rate 1.055013 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0-1 264558 62.57% 62.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1-2 88255 20.87% 83.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2-3 1011 0.24% 83.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3-4 21518 5.09% 88.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4-5 1067 0.25% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5-6 21230 5.02% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6-7 652 0.15% 94.20% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7-8 705 0.17% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 23810 5.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0-1 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1-2 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2-3 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3-4 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4-5 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5-6 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6-7 680 0.16% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7-8 710 0.17% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 422806 # Number of instructions fetched each cycle (Total) -system.cpu2.icache.ReadReq_accesses 88443 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 37054.535017 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35099.253731 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 87572 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 32274500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.009848 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 871 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_miss_latency 23516500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.007576 # mshr miss rate for ReadReq accesses +system.cpu2.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total) +system.cpu2.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_hits 86155 # number of ReadReq hits +system.cpu2.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_misses 870 # number of ReadReq misses +system.cpu2.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses system.cpu2.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 130.899851 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 128.781764 # Average number of references to valid blocks. system.cpu2.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 88443 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 37054.535017 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency -system.cpu2.icache.demand_hits 87572 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 32274500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.009848 # miss rate for demand accesses -system.cpu2.icache.demand_misses 871 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 23516500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.007576 # mshr miss rate for demand accesses +system.cpu2.icache.demand_accesses 87025 # number of demand (read+write) accesses +system.cpu2.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency +system.cpu2.icache.demand_hits 86155 # number of demand (read+write) hits +system.cpu2.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_rate 0.009997 # miss rate for demand accesses +system.cpu2.icache.demand_misses 870 # number of demand (read+write) misses +system.cpu2.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.526897 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 269.771036 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 88443 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 37054.535017 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 35099.253731 # average overall mshr miss latency +system.cpu2.icache.occ_%::0 0.526442 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 269.538121 # Average occupied blocks per context +system.cpu2.icache.overall_accesses 87025 # number of overall (read+write) accesses +system.cpu2.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 87572 # number of overall hits -system.cpu2.icache.overall_miss_latency 32274500 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.009848 # miss rate for overall accesses -system.cpu2.icache.overall_misses 871 # number of overall misses -system.cpu2.icache.overall_mshr_hits 201 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 23516500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.007576 # mshr miss rate for overall accesses +system.cpu2.icache.overall_hits 86155 # number of overall hits +system.cpu2.icache.overall_miss_latency 32248500 # number of overall miss cycles +system.cpu2.icache.overall_miss_rate 0.009997 # miss rate for overall accesses +system.cpu2.icache.overall_misses 870 # number of overall misses +system.cpu2.icache.overall_mshr_hits 200 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_misses 670 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.icache.replacements 363 # number of replacements system.cpu2.icache.sampled_refs 669 # Sample count of references to valid blocks. system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 269.771036 # Cycle average of tags in use -system.cpu2.icache.total_refs 87572 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 269.538121 # Cycle average of tags in use +system.cpu2.icache.total_refs 86155 # Total number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idleCycles 18164 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.iew.EXEC:branches 45174 # Number of branches executed -system.cpu2.iew.EXEC:nop 60963 # number of nop insts executed -system.cpu2.iew.EXEC:rate 0.434102 # Inst execution rate -system.cpu2.iew.EXEC:refs 67735 # number of memory reference insts executed -system.cpu2.iew.EXEC:stores 22705 # Number of stores executed +system.cpu2.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.iew.EXEC:branches 44503 # Number of branches executed +system.cpu2.iew.EXEC:nop 59775 # number of nop insts executed +system.cpu2.iew.EXEC:rate 0.434987 # Inst execution rate +system.cpu2.iew.EXEC:refs 66647 # number of memory reference insts executed +system.cpu2.iew.EXEC:stores 22312 # Number of stores executed system.cpu2.iew.EXEC:swp 0 # number of swp insts executed -system.cpu2.iew.WB:consumers 96501 # num instructions consuming a value -system.cpu2.iew.WB:count 189859 # cumulative count of insts written-back -system.cpu2.iew.WB:fanout 0.973959 # average fanout of values written-back +system.cpu2.iew.WB:consumers 95172 # num instructions consuming a value +system.cpu2.iew.WB:count 187212 # cumulative count of insts written-back +system.cpu2.iew.WB:fanout 0.972912 # average fanout of values written-back system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.iew.WB:producers 93988 # num instructions producing a value -system.cpu2.iew.WB:rate 0.430549 # insts written-back per cycle -system.cpu2.iew.WB:sent 190138 # cumulative count of insts sent to commit -system.cpu2.iew.branchMispredicts 43334 # Number of branch mispredicts detected at execute +system.cpu2.iew.WB:producers 92594 # num instructions producing a value +system.cpu2.iew.WB:rate 0.431358 # insts written-back per cycle +system.cpu2.iew.WB:sent 187507 # cumulative count of insts sent to commit +system.cpu2.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute system.cpu2.iew.iewBlockCycles 24 # Number of cycles IEW is blocking -system.cpu2.iew.iewDispLoadInsts 46475 # Number of dispatched load instructions -system.cpu2.iew.iewDispNonSpecInsts 21048 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewDispSquashedInsts 2818 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispStoreInsts 43788 # Number of dispatched store instructions -system.cpu2.iew.iewDispatchedInsts 321686 # Number of instructions dispatched to IQ -system.cpu2.iew.iewExecLoadInsts 45030 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 43684 # Number of squashed instructions skipped in execute -system.cpu2.iew.iewExecutedInsts 191426 # Number of executed instructions +system.cpu2.iew.iewDispLoadInsts 45739 # Number of dispatched load instructions +system.cpu2.iew.iewDispNonSpecInsts 20652 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewDispSquashedInsts 2935 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispStoreInsts 43021 # Number of dispatched store instructions +system.cpu2.iew.iewDispatchedInsts 316777 # Number of instructions dispatched to IQ +system.cpu2.iew.iewExecLoadInsts 44335 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 42979 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecutedInsts 188787 # Number of executed instructions system.cpu2.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.iewSquashCycles 44866 # Number of cycles IEW is squashing +system.cpu2.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing system.cpu2.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking system.cpu2.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.lsq.thread.0.forwLoads 19969 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread.0.memOrderViolation 186 # Number of memory ordering violations +system.cpu2.iew.lsq.thread.0.memOrderViolation 197 # Number of memory ordering violations system.cpu2.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread.0.squashedLoads 3929 # Number of loads squashed -system.cpu2.iew.lsq.thread.0.squashedStores 22009 # Number of stores squashed -system.cpu2.iew.memOrderViolationEvents 186 # Number of memory order violations -system.cpu2.iew.predictedNotTakenIncorrect 868 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.predictedTakenIncorrect 42466 # Number of branches that were predicted taken incorrectly -system.cpu2.ipc 0.269290 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.269290 # IPC: Total IPC of All Threads +system.cpu2.iew.lsq.thread.0.squashedLoads 3977 # Number of loads squashed +system.cpu2.iew.lsq.thread.0.squashedStores 21634 # Number of stores squashed +system.cpu2.iew.memOrderViolationEvents 197 # Number of memory order violations +system.cpu2.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly +system.cpu2.ipc 0.269095 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.269095 # IPC: Total IPC of All Threads system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntAlu 166509 70.82% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.82% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemRead 45663 19.42% 90.24% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22938 9.76% 100.00% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.86% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemRead 44972 19.40% 90.27% # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::MemWrite 22555 9.73% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.ISSUE:FU_type_0::total 235110 # Type of FU issued +system.cpu2.iq.ISSUE:FU_type_0::total 231766 # Type of FU issued system.cpu2.iq.ISSUE:fu_busy_cnt 133 # FU busy when requested -system.cpu2.iq.ISSUE:fu_busy_rate 0.000566 # FU busy rate (busy events/executed inst) +system.cpu2.iq.ISSUE:fu_busy_rate 0.000574 # FU busy rate (busy events/executed inst) system.cpu2.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IntAlu 38 28.57% 28.57% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IntMult 0 0.00% 28.57% # attempts to use FU when none available @@ -952,576 +951,577 @@ system.cpu2.iq.ISSUE:fu_full::MemRead 27 20.30% 48.87% # at system.cpu2.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.ISSUE:issued_per_cycle::samples 422806 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.556071 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.945329 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::0-1 286677 67.80% 67.80% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::1-2 67298 15.92% 83.72% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::2-3 43645 10.32% 94.04% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::3-4 22116 5.23% 99.27% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1740 0.41% 99.69% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::5-6 920 0.22% 99.90% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::6-7 282 0.07% 99.97% # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::7-8 102 0.02% 99.99% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::0-1 281858 67.78% 67.78% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::1-2 66212 15.92% 83.70% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::2-3 42876 10.31% 94.01% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::3-4 21783 5.24% 99.25% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::4-5 1770 0.43% 99.67% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::5-6 926 0.22% 99.90% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::6-7 279 0.07% 99.96% # Number of insts issued each cycle +system.cpu2.iq.ISSUE:issued_per_cycle::7-8 123 0.03% 99.99% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:issued_per_cycle::total 422806 # Number of insts issued each cycle -system.cpu2.iq.ISSUE:rate 0.533166 # Inst issue rate -system.cpu2.iq.iqInstsAdded 239551 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqInstsIssued 235110 # Number of instructions issued -system.cpu2.iq.iqNonSpecInstsAdded 21172 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqSquashedInstsExamined 99184 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedNonSpecRemoved 20613 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.iqSquashedOperandsExamined 15669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.memDep0.conflictingLoads 20136 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 109 # Number of conflicting stores. -system.cpu2.memDep0.insertedLoads 46475 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 43788 # Number of stores inserted to the mem dependence unit. -system.cpu2.numCycles 440970 # number of cpu cycles simulated +system.cpu2.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle +system.cpu2.iq.ISSUE:rate 0.534016 # Inst issue rate +system.cpu2.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqInstsIssued 231766 # Number of instructions issued +system.cpu2.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.memDep0.conflictingLoads 19721 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 107 # Number of conflicting stores. +system.cpu2.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit. +system.cpu2.numCycles 434006 # number of cpu cycles simulated system.cpu2.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking -system.cpu2.rename.RENAME:CommittedMaps 97924 # Number of HB maps that are committed -system.cpu2.rename.RENAME:IdleCycles 188399 # Number of cycles rename is idle +system.cpu2.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed +system.cpu2.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle system.cpu2.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RENAME:RenameLookups 512581 # Number of register rename lookups that rename has made -system.cpu2.rename.RENAME:RenamedInsts 328892 # Number of instructions processed by rename -system.cpu2.rename.RENAME:RenamedOperands 245007 # Number of destination operands rename has renamed -system.cpu2.rename.RENAME:RunCycles 135302 # Number of cycles rename is running -system.cpu2.rename.RENAME:SquashCycles 44866 # Number of cycles rename is squashing -system.cpu2.rename.RENAME:UnblockCycles 350 # Number of cycles rename is unblocking -system.cpu2.rename.RENAME:UndoneMaps 147083 # Number of HB maps that are undone due to squashing -system.cpu2.rename.RENAME:serializeStallCycles 53857 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RENAME:serializingInsts 21162 # count of serializing insts renamed -system.cpu2.rename.RENAME:skidInsts 84753 # count of insts added to the skid buffer -system.cpu2.rename.RENAME:tempSerializingInsts 21158 # count of temporary serializing insts renamed +system.cpu2.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made +system.cpu2.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename +system.cpu2.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed +system.cpu2.rename.RENAME:RunCycles 133139 # Number of cycles rename is running +system.cpu2.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing +system.cpu2.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking +system.cpu2.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing +system.cpu2.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed +system.cpu2.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer +system.cpu2.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed system.cpu2.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.BTBHits 51243 # Number of BTB hits -system.cpu3.BPredUnit.BTBLookups 69683 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 53713 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 65870 # Number of BTB lookups system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu3.BPredUnit.condIncorrect 32692 # Number of conditional branches incorrect -system.cpu3.BPredUnit.condPredicted 78569 # Number of conditional branches predicted -system.cpu3.BPredUnit.lookups 78569 # Number of BP lookups +system.cpu3.BPredUnit.condIncorrect 29792 # Number of conditional branches incorrect +system.cpu3.BPredUnit.condPredicted 83669 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 83669 # Number of BP lookups system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -system.cpu3.commit.COM:branches 25257 # Number of branches committed -system.cpu3.commit.COM:bw_lim_events 568 # number cycles where commit BW limit reached +system.cpu3.commit.COM:branches 25470 # Number of branches committed +system.cpu3.commit.COM:bw_lim_events 577 # number cycles where commit BW limit reached system.cpu3.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.commit.COM:committed_per_cycle::samples 351415 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::mean 0.376558 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::stdev 0.826419 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::samples 350132 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::mean 0.363609 # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::stdev 0.831936 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::0-1 262526 74.71% 74.71% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::1-2 59947 17.06% 91.76% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::2-3 24097 6.86% 98.62% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::3-4 1297 0.37% 98.99% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::4-5 787 0.22% 99.21% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::5-6 568 0.16% 99.38% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::6-7 1611 0.46% 99.83% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::7-8 14 0.00% 99.84% # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::8 568 0.16% 100.00% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::0-1 266836 76.21% 76.21% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::1-2 54270 15.50% 91.71% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::2-3 24066 6.87% 98.58% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::3-4 1288 0.37% 98.95% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::4-5 810 0.23% 99.18% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::5-6 561 0.16% 99.34% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::6-7 1684 0.48% 99.82% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::7-8 40 0.01% 99.84% # Number of insts commited each cycle +system.cpu3.commit.COM:committed_per_cycle::8 577 0.16% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.COM:committed_per_cycle::total 351415 # Number of insts commited each cycle -system.cpu3.commit.COM:count 132328 # Number of instructions committed -system.cpu3.commit.COM:loads 32245 # Number of loads committed -system.cpu3.commit.COM:membars 5830 # Number of memory barriers committed -system.cpu3.commit.COM:refs 45707 # Number of memory references committed +system.cpu3.commit.COM:committed_per_cycle::total 350132 # Number of insts commited each cycle +system.cpu3.commit.COM:count 127311 # Number of instructions committed +system.cpu3.commit.COM:loads 29520 # Number of loads committed +system.cpu3.commit.COM:membars 8970 # Number of memory barriers committed +system.cpu3.commit.COM:refs 40059 # Number of memory references committed system.cpu3.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.branchMispredicts 32692 # The number of times a branch was mispredicted -system.cpu3.commit.commitCommittedInsts 132328 # The number of committed instructions -system.cpu3.commit.commitNonSpecStalls 6543 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.commitSquashedInsts 149632 # The number of squashed insts skipped by commit -system.cpu3.committedInsts 110450 # Number of Instructions Simulated -system.cpu3.committedInsts_total 110450 # Number of Instructions Simulated -system.cpu3.cpi 3.645957 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 3.645957 # CPI: Total CPI of All Threads -system.cpu3.dcache.ReadReq_accesses 28797 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 19788.770053 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 16721.212121 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 28610 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 3700500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.006494 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 187 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_miss_latency 2759000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.005730 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses -system.cpu3.dcache.SwapReq_accesses 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_avg_miss_latency 21918.181818 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22138.297872 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_miss_latency 1205500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_rate 0.820896 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_misses 55 # number of SwapReq misses -system.cpu3.dcache.SwapReq_mshr_hits 8 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_miss_latency 1040500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.701493 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_misses 47 # number of SwapReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 13395 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 23007.751938 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14729.729730 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 13266 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 2968000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.009630 # miss rate for WriteReq accesses +system.cpu3.commit.branchMispredicts 29792 # The number of times a branch was mispredicted +system.cpu3.commit.commitCommittedInsts 127311 # The number of committed instructions +system.cpu3.commit.commitNonSpecStalls 9688 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit +system.cpu3.committedInsts 102085 # Number of Instructions Simulated +system.cpu3.committedInsts_total 102085 # Number of Instructions Simulated +system.cpu3.cpi 3.876926 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 3.876926 # CPI: Total CPI of All Threads +system.cpu3.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_hits 28662 # number of ReadReq hits +system.cpu3.dcache.ReadReq_miss_latency 3852000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_rate 0.007067 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_misses 204 # number of ReadReq misses +system.cpu3.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_miss_latency 2921500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.006062 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_misses 175 # number of ReadReq MSHR misses +system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_avg_miss_latency 22155.172414 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 24152.173913 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_miss_latency 1285000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_mshr_hits 12 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_miss_latency 1111000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.638889 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_misses 46 # number of SwapReq MSHR misses +system.cpu3.dcache.WriteReq_accesses 10467 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_avg_miss_latency 23593.023256 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15414.414414 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_hits 10338 # number of WriteReq hits +system.cpu3.dcache.WriteReq_miss_latency 3043500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_rate 0.012324 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_misses 129 # number of WriteReq misses system.cpu3.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_miss_latency 1635000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.008287 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_latency 1711000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.010605 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_misses 111 # number of WriteReq MSHR misses system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 804.066667 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 701.333333 # Average number of references to valid blocks. system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 42192 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 21102.848101 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 41876 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 6668500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.007490 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 316 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 4394000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.006542 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 276 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_accesses 39333 # number of demand (read+write) accesses +system.cpu3.dcache.demand_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency +system.cpu3.dcache.demand_hits 39000 # number of demand (read+write) hits +system.cpu3.dcache.demand_miss_latency 6895500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_rate 0.008466 # miss rate for demand accesses +system.cpu3.dcache.demand_misses 333 # number of demand (read+write) misses +system.cpu3.dcache.demand_mshr_hits 47 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_miss_latency 4632500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_rate 0.007271 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_misses 286 # number of demand (read+write) MSHR misses system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.056978 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 29.172631 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 42192 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 21102.848101 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 15920.289855 # average overall mshr miss latency +system.cpu3.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy +system.cpu3.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context +system.cpu3.dcache.overall_accesses 39333 # number of overall (read+write) accesses +system.cpu3.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 41876 # number of overall hits -system.cpu3.dcache.overall_miss_latency 6668500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.007490 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 316 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 40 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 4394000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.006542 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 276 # number of overall MSHR misses +system.cpu3.dcache.overall_hits 39000 # number of overall hits +system.cpu3.dcache.overall_miss_latency 6895500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_rate 0.008466 # miss rate for overall accesses +system.cpu3.dcache.overall_misses 333 # number of overall misses +system.cpu3.dcache.overall_mshr_hits 47 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_miss_latency 4632500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_rate 0.007271 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_misses 286 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.dcache.replacements 2 # number of replacements system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 29.172631 # Cycle average of tags in use -system.cpu3.dcache.total_refs 24122 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 27.232391 # Cycle average of tags in use +system.cpu3.dcache.total_refs 21040 # Total number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.decode.DECODE:BlockedCycles 35128 # Number of cycles decode is blocked -system.cpu3.decode.DECODE:DecodedInsts 388171 # Number of instructions handled by decode -system.cpu3.decode.DECODE:IdleCycles 168108 # Number of cycles decode is idle -system.cpu3.decode.DECODE:RunCycles 148027 # Number of cycles decode is running -system.cpu3.decode.DECODE:SquashCycles 36551 # Number of cycles decode is squashing -system.cpu3.decode.DECODE:UnblockCycles 152 # Number of cycles decode is unblocking -system.cpu3.fetch.Branches 78569 # Number of branches that fetch encountered -system.cpu3.fetch.CacheLines 81998 # Number of cache lines fetched -system.cpu3.fetch.Cycles 239499 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.IcacheSquashes 12083 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.Insts 427102 # Number of instructions fetch has processed -system.cpu3.fetch.SquashCycles 32841 # Number of cycles fetch has spent squashing -system.cpu3.fetch.branchRate 0.195107 # Number of branch fetches per cycle -system.cpu3.fetch.icacheStallCycles 81998 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.predictedBranches 51243 # Number of branches that fetch has predicted taken -system.cpu3.fetch.rate 1.060607 # Number of inst fetches per cycle -system.cpu3.fetch.rateDist::samples 397135 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.075458 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.013935 # Number of instructions fetched each cycle (Total) +system.cpu3.decode.DECODE:BlockedCycles 30059 # Number of cycles decode is blocked +system.cpu3.decode.DECODE:DecodedInsts 353088 # Number of instructions handled by decode +system.cpu3.decode.DECODE:IdleCycles 174967 # Number of cycles decode is idle +system.cpu3.decode.DECODE:RunCycles 144955 # Number of cycles decode is running +system.cpu3.decode.DECODE:SquashCycles 33628 # Number of cycles decode is squashing +system.cpu3.decode.DECODE:UnblockCycles 151 # Number of cycles decode is unblocking +system.cpu3.fetch.Branches 83669 # Number of branches that fetch encountered +system.cpu3.fetch.CacheLines 82467 # Number of cache lines fetched +system.cpu3.fetch.Cycles 239936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.Insts 410532 # Number of instructions fetch has processed +system.cpu3.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing +system.cpu3.fetch.branchRate 0.211405 # Number of branch fetches per cycle +system.cpu3.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken +system.cpu3.fetch.rate 1.037284 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0-1 239656 60.35% 60.35% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1-2 85048 21.42% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2-3 14012 3.53% 85.29% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3-4 17951 4.52% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4-5 2990 0.75% 90.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5-6 15291 3.85% 94.41% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6-7 1676 0.42% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7-8 2382 0.60% 95.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 18129 4.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0-1 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1-2 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2-3 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3-4 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4-5 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5-6 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6-7 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7-8 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 397135 # Number of instructions fetched each cycle (Total) -system.cpu3.icache.ReadReq_accesses 81998 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 19529.880478 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 16592.417062 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 81245 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 14706000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.009183 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 753 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_miss_latency 10503000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.007720 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 633 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu3.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total) +system.cpu3.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_hits 81734 # number of ReadReq hits +system.cpu3.icache.ReadReq_miss_latency 10621000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_rate 0.008888 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_misses 733 # number of ReadReq misses +system.cpu3.icache.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_miss_latency 7591000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate 0.007712 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_misses 636 # number of ReadReq MSHR misses +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 128.349131 # Average number of references to valid blocks. -system.cpu3.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu3.icache.avg_refs 128.512579 # Average number of references to valid blocks. +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 81998 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 19529.880478 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency -system.cpu3.icache.demand_hits 81245 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 14706000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.009183 # miss rate for demand accesses -system.cpu3.icache.demand_misses 753 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 10503000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.007720 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 633 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_accesses 82467 # number of demand (read+write) accesses +system.cpu3.icache.demand_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency +system.cpu3.icache.demand_hits 81734 # number of demand (read+write) hits +system.cpu3.icache.demand_miss_latency 10621000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_rate 0.008888 # miss rate for demand accesses +system.cpu3.icache.demand_misses 733 # number of demand (read+write) misses +system.cpu3.icache.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_miss_latency 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_rate 0.007712 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_misses 636 # number of demand (read+write) MSHR misses system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.192956 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 98.793514 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 81998 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 19529.880478 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 16592.417062 # average overall mshr miss latency +system.cpu3.icache.occ_%::0 0.182938 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 93.664377 # Average occupied blocks per context +system.cpu3.icache.overall_accesses 82467 # number of overall (read+write) accesses +system.cpu3.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 81245 # number of overall hits -system.cpu3.icache.overall_miss_latency 14706000 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.009183 # miss rate for overall accesses -system.cpu3.icache.overall_misses 753 # number of overall misses -system.cpu3.icache.overall_mshr_hits 120 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 10503000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.007720 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 633 # number of overall MSHR misses +system.cpu3.icache.overall_hits 81734 # number of overall hits +system.cpu3.icache.overall_miss_latency 10621000 # number of overall miss cycles +system.cpu3.icache.overall_miss_rate 0.008888 # miss rate for overall accesses +system.cpu3.icache.overall_misses 733 # number of overall misses +system.cpu3.icache.overall_mshr_hits 97 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_miss_latency 7591000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_rate 0.007712 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_misses 636 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 522 # number of replacements -system.cpu3.icache.sampled_refs 633 # Sample count of references to valid blocks. +system.cpu3.icache.replacements 524 # number of replacements +system.cpu3.icache.sampled_refs 636 # Sample count of references to valid blocks. system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 98.793514 # Cycle average of tags in use -system.cpu3.icache.total_refs 81245 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 93.664377 # Cycle average of tags in use +system.cpu3.icache.total_refs 81734 # Total number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idleCycles 5561 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.iew.EXEC:branches 39289 # Number of branches executed -system.cpu3.iew.EXEC:nop 47300 # number of nop insts executed -system.cpu3.iew.EXEC:rate 0.440007 # Inst execution rate -system.cpu3.iew.EXEC:refs 53548 # number of memory reference insts executed -system.cpu3.iew.EXEC:stores 15235 # Number of stores executed +system.cpu3.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.iew.EXEC:branches 36547 # Number of branches executed +system.cpu3.iew.EXEC:nop 47873 # number of nop insts executed +system.cpu3.iew.EXEC:rate 0.410224 # Inst execution rate +system.cpu3.iew.EXEC:refs 47615 # number of memory reference insts executed +system.cpu3.iew.EXEC:stores 12164 # Number of stores executed system.cpu3.iew.EXEC:swp 0 # number of swp insts executed -system.cpu3.iew.WB:consumers 87751 # num instructions consuming a value -system.cpu3.iew.WB:count 173492 # cumulative count of insts written-back -system.cpu3.iew.WB:fanout 0.936696 # average fanout of values written-back +system.cpu3.iew.WB:consumers 78764 # num instructions consuming a value +system.cpu3.iew.WB:count 158732 # cumulative count of insts written-back +system.cpu3.iew.WB:fanout 0.929676 # average fanout of values written-back system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.iew.WB:producers 82196 # num instructions producing a value -system.cpu3.iew.WB:rate 0.430826 # insts written-back per cycle -system.cpu3.iew.WB:sent 173712 # cumulative count of insts sent to commit -system.cpu3.iew.branchMispredicts 33345 # Number of branch mispredicts detected at execute +system.cpu3.iew.WB:producers 73225 # num instructions producing a value +system.cpu3.iew.WB:rate 0.401065 # insts written-back per cycle +system.cpu3.iew.WB:sent 158983 # cumulative count of insts sent to commit +system.cpu3.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu3.iew.iewDispLoadInsts 42639 # Number of dispatched load instructions -system.cpu3.iew.iewDispNonSpecInsts 11434 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewDispSquashedInsts 4085 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispStoreInsts 26562 # Number of dispatched store instructions -system.cpu3.iew.iewDispatchedInsts 281979 # Number of instructions dispatched to IQ -system.cpu3.iew.iewExecLoadInsts 38313 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 36396 # Number of squashed instructions skipped in execute -system.cpu3.iew.iewExecutedInsts 177189 # Number of executed instructions +system.cpu3.iew.iewDispLoadInsts 39543 # Number of dispatched load instructions +system.cpu3.iew.iewDispNonSpecInsts 8501 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispSquashedInsts 3508 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispStoreInsts 20654 # Number of dispatched store instructions +system.cpu3.iew.iewDispatchedInsts 261662 # Number of instructions dispatched to IQ +system.cpu3.iew.iewExecLoadInsts 35451 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 33572 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 162357 # Number of executed instructions system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.iewSquashCycles 36551 # Number of cycles IEW is squashing +system.cpu3.iew.iewSquashCycles 33628 # Number of cycles IEW is squashing system.cpu3.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu3.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.lsq.thread.0.forwLoads 9499 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread.0.forwLoads 6568 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread.0.memOrderViolation 639 # Number of memory ordering violations +system.cpu3.iew.lsq.thread.0.memOrderViolation 694 # Number of memory ordering violations system.cpu3.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread.0.squashedLoads 10394 # Number of loads squashed -system.cpu3.iew.lsq.thread.0.squashedStores 13100 # Number of stores squashed -system.cpu3.iew.memOrderViolationEvents 639 # Number of memory order violations -system.cpu3.iew.predictedNotTakenIncorrect 830 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.predictedTakenIncorrect 32515 # Number of branches that were predicted taken incorrectly -system.cpu3.ipc 0.274276 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.274276 # IPC: Total IPC of All Threads +system.cpu3.iew.lsq.thread.0.squashedLoads 10023 # Number of loads squashed +system.cpu3.iew.lsq.thread.0.squashedStores 10115 # Number of stores squashed +system.cpu3.iew.memOrderViolationEvents 694 # Number of memory order violations +system.cpu3.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly +system.cpu3.ipc 0.257936 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.257936 # IPC: Total IPC of All Threads system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntAlu 152352 71.33% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.33% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemRead 45332 21.22% 92.56% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::MemWrite 15901 7.44% 100.00% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.15% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemRead 45623 23.29% 93.43% # Type of FU issued +system.cpu3.iq.ISSUE:FU_type_0::MemWrite 12865 6.57% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.ISSUE:FU_type_0::total 213585 # Type of FU issued -system.cpu3.iq.ISSUE:fu_busy_cnt 168 # FU busy when requested -system.cpu3.iq.ISSUE:fu_busy_rate 0.000787 # FU busy rate (busy events/executed inst) +system.cpu3.iq.ISSUE:FU_type_0::total 195929 # Type of FU issued +system.cpu3.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested +system.cpu3.iq.ISSUE:fu_busy_rate 0.000949 # FU busy rate (busy events/executed inst) system.cpu3.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntAlu 18 10.71% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.71% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemRead 11 6.55% 17.26% # attempts to use FU when none available -system.cpu3.iq.ISSUE:fu_full::MemWrite 139 82.74% 100.00% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntAlu 24 12.90% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.90% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemRead 17 9.14% 22.04% # attempts to use FU when none available +system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.ISSUE:issued_per_cycle::samples 397135 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.537815 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.988033 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::0-1 274584 69.14% 69.14% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::1-2 68377 17.22% 86.36% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::2-3 29162 7.34% 93.70% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::3-4 16815 4.23% 97.94% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5405 1.36% 99.30% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2141 0.54% 99.84% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::6-7 468 0.12% 99.95% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::7-8 158 0.04% 99.99% # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::8 25 0.01% 100.00% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::0-1 276221 70.31% 70.31% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::1-2 71375 18.17% 88.48% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::2-3 23368 5.95% 94.42% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::3-4 13587 3.46% 97.88% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::4-5 5437 1.38% 99.27% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::5-6 2194 0.56% 99.83% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::6-7 490 0.12% 99.95% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::7-8 161 0.04% 99.99% # Number of insts issued each cycle +system.cpu3.iq.ISSUE:issued_per_cycle::8 34 0.01% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:issued_per_cycle::total 397135 # Number of insts issued each cycle -system.cpu3.iq.ISSUE:rate 0.530388 # Inst issue rate -system.cpu3.iq.iqInstsAdded 217367 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqInstsIssued 213585 # Number of instructions issued -system.cpu3.iq.iqNonSpecInstsAdded 17312 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqSquashedInstsExamined 84893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedNonSpecRemoved 10769 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.iqSquashedOperandsExamined 34030 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.memDep0.conflictingLoads 9667 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 80 # Number of conflicting stores. -system.cpu3.memDep0.insertedLoads 42639 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 26562 # Number of stores inserted to the mem dependence unit. -system.cpu3.numCycles 402696 # number of cpu cycles simulated -system.cpu3.rename.RENAME:CommittedMaps 93774 # Number of HB maps that are committed -system.cpu3.rename.RENAME:IdleCycles 183092 # Number of cycles rename is idle -system.cpu3.rename.RENAME:RenameLookups 489966 # Number of register rename lookups that rename has made -system.cpu3.rename.RENAME:RenamedInsts 307555 # Number of instructions processed by rename -system.cpu3.rename.RENAME:RenamedOperands 229124 # Number of destination operands rename has renamed -system.cpu3.rename.RENAME:RunCycles 133281 # Number of cycles rename is running -system.cpu3.rename.RENAME:SquashCycles 36551 # Number of cycles rename is squashing -system.cpu3.rename.RENAME:UnblockCycles 561 # Number of cycles rename is unblocking -system.cpu3.rename.RENAME:UndoneMaps 135350 # Number of HB maps that are undone due to squashing -system.cpu3.rename.RENAME:serializeStallCycles 34481 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RENAME:serializingInsts 11653 # count of serializing insts renamed -system.cpu3.rename.RENAME:skidInsts 44534 # count of insts added to the skid buffer -system.cpu3.rename.RENAME:tempSerializingInsts 11782 # count of temporary serializing insts renamed -system.cpu3.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.l2c.ReadExReq_accesses::0 12 # number of ReadExReq accesses(hits+misses) +system.cpu3.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle +system.cpu3.iq.ISSUE:rate 0.495050 # Inst issue rate +system.cpu3.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqInstsIssued 195929 # Number of instructions issued +system.cpu3.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqSquashedInstsExamined 74909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedNonSpecRemoved 7843 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.iqSquashedOperandsExamined 33478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.memDep0.conflictingLoads 6760 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 87 # Number of conflicting stores. +system.cpu3.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit. +system.cpu3.numCycles 395776 # number of cpu cycles simulated +system.cpu3.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed +system.cpu3.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle +system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RENAME:RenameLookups 447878 # Number of register rename lookups that rename has made +system.cpu3.rename.RENAME:RenamedInsts 290237 # Number of instructions processed by rename +system.cpu3.rename.RENAME:RenamedOperands 204758 # Number of destination operands rename has renamed +system.cpu3.rename.RENAME:RunCycles 133245 # Number of cycles rename is running +system.cpu3.rename.RENAME:SquashCycles 33628 # Number of cycles rename is squashing +system.cpu3.rename.RENAME:UnblockCycles 630 # Number of cycles rename is unblocking +system.cpu3.rename.RENAME:UndoneMaps 119564 # Number of HB maps that are undone due to squashing +system.cpu3.rename.RENAME:serializeStallCycles 29341 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RENAME:serializingInsts 8772 # count of serializing insts renamed +system.cpu3.rename.RENAME:skidInsts 33179 # count of insts added to the skid buffer +system.cpu3.rename.RENAME:tempSerializingInsts 8900 # count of temporary serializing insts renamed +system.cpu3.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.l2c.ReadExReq_accesses::0 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 572875 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 572875 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 73132.978723 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 528807.692308 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1747690.671031 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40316.793893 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 6874500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_avg_miss_latency::0 528730.769231 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 572791.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 73122.340426 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 572791.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1747436.442990 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40312.977099 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 6873500 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 12 # number of ReadExReq misses +system.l2c.ReadExReq_misses::0 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::2 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5281500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 10.916667 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_latency 5281000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 10.076923 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 1.393617 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 10.076923 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 649 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 651 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::0 646 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 653 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::2 752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 647 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2699 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 4142500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 7249375 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 63451.859956 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 325814.606742 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 11781141.466698 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39997.282609 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits::0 642 # number of ReadReq hits +system.l2c.ReadReq_accesses::3 650 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2701 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 362318.750000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 4830916.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 63425.601751 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 2229653.846154 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 7486314.864571 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_hits::0 566 # number of ReadReq hits system.l2c.ReadReq_hits::1 647 # number of ReadReq hits system.l2c.ReadReq_hits::2 295 # number of ReadReq hits -system.l2c.ReadReq_hits::3 558 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2142 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 28997500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.010786 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006144 # miss rate for ReadReq accesses +system.l2c.ReadReq_hits::3 637 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 28985500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.123839 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.009188 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::2 0.607713 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.137558 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.762201 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 7 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4 # number of ReadReq misses +system.l2c.ReadReq_miss_rate::3 0.020000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.760740 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 80 # number of ReadReq misses +system.l2c.ReadReq_misses::1 6 # number of ReadReq misses system.l2c.ReadReq_misses::2 457 # number of ReadReq misses -system.l2c.ReadReq_misses::3 89 # number of ReadReq misses -system.l2c.ReadReq_misses::total 557 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 22078500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.850539 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.847926 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_misses::3 13 # number of ReadReq misses +system.l2c.ReadReq_misses::total 556 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 22080000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.854489 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.845329 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 0.734043 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 0.853168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.285677 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 0.849231 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.283092 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_accesses::0 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::1 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 52 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 53 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::3 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 114 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 68894.736842 # average UpgradeReq miss latency +system.l2c.UpgradeReq_accesses::total 117 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 62333.333333 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 59500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 25173.076923 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 24698.113208 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::3 62333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 215901.147099 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40039.473684 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 208864.779874 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40038.461538 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::1 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 52 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 53 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::3 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 114 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 4564500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 6 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 5.181818 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 2.192308 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 5.428571 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 18.802697 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 114 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::total 117 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 4684500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 5.318182 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 2.207547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 5.571429 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 18.668586 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 3.998131 # Average number of references to valid blocks. +system.l2c.avg_refs 4.003738 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 661 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 663 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 659 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 665 # number of demand (read+write) accesses system.l2c.demand_accesses::2 846 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 660 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2830 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 1888000 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 2242000 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 65103.448276 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 351686.274510 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 4546789.722786 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency -system.l2c.demand_hits::0 642 # number of demand (read+write) hits +system.l2c.demand_accesses::3 662 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2832 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 385580.645161 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1992166.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 65079.854809 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3877187.166637 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency +system.l2c.demand_hits::0 566 # number of demand (read+write) hits system.l2c.demand_hits::1 647 # number of demand (read+write) hits system.l2c.demand_hits::2 295 # number of demand (read+write) hits -system.l2c.demand_hits::3 558 # number of demand (read+write) hits -system.l2c.demand_hits::total 2142 # number of demand (read+write) hits -system.l2c.demand_miss_latency 35872000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.028744 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.024133 # miss rate for demand accesses +system.l2c.demand_hits::3 637 # number of demand (read+write) hits +system.l2c.demand_hits::total 2145 # number of demand (read+write) hits +system.l2c.demand_miss_latency 35859000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.141123 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.027068 # miss rate for demand accesses system.l2c.demand_miss_rate::2 0.651300 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.154545 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.858723 # miss rate for demand accesses -system.l2c.demand_misses::0 19 # number of demand (read+write) misses -system.l2c.demand_misses::1 16 # number of demand (read+write) misses +system.l2c.demand_miss_rate::3 0.037764 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.857255 # miss rate for demand accesses +system.l2c.demand_misses::0 93 # number of demand (read+write) misses +system.l2c.demand_misses::1 18 # number of demand (read+write) misses system.l2c.demand_misses::2 551 # number of demand (read+write) misses -system.l2c.demand_misses::3 102 # number of demand (read+write) misses -system.l2c.demand_misses::total 688 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 27360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 1.033283 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.030166 # mshr miss rate for demand accesses +system.l2c.demand_misses::3 25 # number of demand (read+write) misses +system.l2c.demand_misses::total 687 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 27361000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 1.036419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.027068 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 0.807329 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.034848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 3.905626 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.031722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 3.902537 # mshr miss rate for demand accesses system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.000042 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.000041 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.005574 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.001194 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000088 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 2.720574 # Average occupied blocks per context -system.l2c.occ_blocks::1 2.658049 # Average occupied blocks per context -system.l2c.occ_blocks::2 365.307630 # Average occupied blocks per context -system.l2c.occ_blocks::3 78.263554 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.734616 # Average occupied blocks per context -system.l2c.overall_accesses::0 661 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 663 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.001067 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.000056 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.005570 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.000152 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 69.921003 # Average occupied blocks per context +system.l2c.occ_blocks::1 3.643564 # Average occupied blocks per context +system.l2c.occ_blocks::2 365.031703 # Average occupied blocks per context +system.l2c.occ_blocks::3 9.942146 # Average occupied blocks per context +system.l2c.occ_blocks::4 5.939892 # Average occupied blocks per context +system.l2c.overall_accesses::0 659 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 665 # number of overall (read+write) accesses system.l2c.overall_accesses::2 846 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 660 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2830 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 1888000 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 2242000 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 65103.448276 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 351686.274510 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 4546789.722786 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40058.565154 # average overall mshr miss latency +system.l2c.overall_accesses::3 662 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2832 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 385580.645161 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1992166.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 65079.854809 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1434360 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3877187.166637 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 642 # number of overall hits +system.l2c.overall_hits::0 566 # number of overall hits system.l2c.overall_hits::1 647 # number of overall hits system.l2c.overall_hits::2 295 # number of overall hits -system.l2c.overall_hits::3 558 # number of overall hits -system.l2c.overall_hits::total 2142 # number of overall hits -system.l2c.overall_miss_latency 35872000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.028744 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.024133 # miss rate for overall accesses +system.l2c.overall_hits::3 637 # number of overall hits +system.l2c.overall_hits::total 2145 # number of overall hits +system.l2c.overall_miss_latency 35859000 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.141123 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.027068 # miss rate for overall accesses system.l2c.overall_miss_rate::2 0.651300 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.154545 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.858723 # miss rate for overall accesses -system.l2c.overall_misses::0 19 # number of overall misses -system.l2c.overall_misses::1 16 # number of overall misses +system.l2c.overall_miss_rate::3 0.037764 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.857255 # miss rate for overall accesses +system.l2c.overall_misses::0 93 # number of overall misses +system.l2c.overall_misses::1 18 # number of overall misses system.l2c.overall_misses::2 551 # number of overall misses -system.l2c.overall_misses::3 102 # number of overall misses -system.l2c.overall_misses::total 688 # number of overall misses -system.l2c.overall_mshr_hits 5 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 27360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 1.033283 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.030166 # mshr miss rate for overall accesses +system.l2c.overall_misses::3 25 # number of overall misses +system.l2c.overall_misses::total 687 # number of overall misses +system.l2c.overall_mshr_hits 4 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 27361000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 1.036419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.027068 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 0.807329 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.034848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 3.905626 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.031722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 3.902537 # mshr miss rate for overall accesses system.l2c.overall_mshr_misses 683 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.replacements 0 # number of replacements system.l2c.sampled_refs 535 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 454.684423 # Cycle average of tags in use -system.l2c.total_refs 2139 # Total number of references to valid blocks. +system.l2c.tagsinuse 454.478308 # Cycle average of tags in use +system.l2c.total_refs 2142 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks |