diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2011-09-13 12:58:09 -0400 |
| commit | 28a2236ec18e3d5a82d6f7caffbf8285aec48b38 (patch) | |
| tree | bfd2d8d78733f95b30e9f671229ce2f0f55f4d94 /tests/quick/40.m5threads-test-atomic | |
| parent | 649c239ceef2d107fae253b1008c6f214f242d73 (diff) | |
| download | gem5-28a2236ec18e3d5a82d6f7caffbf8285aec48b38.tar.xz | |
O3: Update stats for new ordering fix.
Diffstat (limited to 'tests/quick/40.m5threads-test-atomic')
3 files changed, 557 insertions, 551 deletions
diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 14fd2a611..dc4523b69 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -102,6 +102,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu0.tracer trapLatency=13 @@ -457,7 +458,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -551,6 +552,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu1.tracer trapLatency=13 @@ -981,6 +983,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu2.tracer trapLatency=13 @@ -1411,6 +1414,7 @@ smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 +store_set_clear_period=250000 system=system tracer=system.cpu3.tracer trapLatency=13 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 67f90c44c..9264a5759 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout +Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 18 2011 17:36:58 -gem5 started Jul 18 2011 17:37:01 -gem5 executing on u200439-lin.austin.arm.com +gem5 compiled Aug 20 2011 13:07:22 +gem5 started Aug 20 2011 13:07:32 +gem5 executing on zizzer command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -79,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 104314500 because target called exit() +Exiting @ tick 104317500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 30cbeea1f..101c2c9bd 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,98 +1,98 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000104 # Number of seconds simulated -sim_ticks 104314500 # Number of ticks simulated +sim_ticks 104317500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102986 # Simulator instruction rate (inst/s) -host_tick_rate 10543012 # Simulator tick rate (ticks/s) -host_mem_usage 263248 # Number of bytes of host memory used -host_seconds 9.89 # Real time elapsed on the host -sim_insts 1018958 # Number of instructions simulated +host_inst_rate 86437 # Simulator instruction rate (inst/s) +host_tick_rate 8848828 # Simulator tick rate (ticks/s) +host_mem_usage 223064 # Number of bytes of host memory used +host_seconds 11.79 # Real time elapsed on the host +sim_insts 1018993 # Number of instructions simulated system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 208630 # number of cpu cycles simulated +system.cpu0.numCycles 208636 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 80647 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 78658 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 80640 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 78657 # Number of conditional branches predicted system.cpu0.BPredUnit.condIncorrect 1043 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 79786 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 77333 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 79781 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 77332 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 410 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 408 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16573 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 478963 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 80647 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 158144 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3218 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12869 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 16565 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 478922 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 80640 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77740 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 158137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3216 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 12889 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1227 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5521 # Number of cache lines fetched +system.cpu0.fetch.CacheLines 5515 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 190842 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.509736 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.192738 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 190846 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.509468 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.192643 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32698 17.13% 17.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78519 41.14% 58.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 548 0.29% 58.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 993 0.52% 59.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 666 0.35% 59.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32709 17.14% 17.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78517 41.14% 58.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 548 0.29% 58.57% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 994 0.52% 59.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 666 0.35% 59.44% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::5 74596 39.09% 98.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 803 0.42% 98.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 245 0.13% 99.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1774 0.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 801 0.42% 98.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 243 0.13% 99.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 1772 0.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 190842 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.386555 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.295753 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16953 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14325 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 157237 # Number of cycles decode is running +system.cpu0.fetch.rateDist::total 190846 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.386510 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.295491 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16943 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14345 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 157232 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 303 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2024 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 476777 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2024 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17557 # Number of cycles rename is idle +system.cpu0.decode.SquashCycles 2023 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 476750 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2023 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17547 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 1397 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12280 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 156961 # Number of cycles rename is running +system.cpu0.rename.serializeStallCycles 12300 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 156956 # Number of cycles rename is running system.cpu0.rename.UnblockCycles 623 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 474190 # Number of instructions processed by rename +system.cpu0.rename.RenamedInsts 474177 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full system.cpu0.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 324005 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 945716 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 945716 # Number of integer rename lookups +system.cpu0.rename.RenamedOperands 323986 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 945682 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 945682 # Number of integer rename lookups system.cpu0.rename.CommittedMaps 313636 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10369 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 805 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 826 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3607 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 152098 # Number of loads inserted to the mem dependence unit. +system.cpu0.rename.UndoneMaps 10350 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 803 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 824 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 152097 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 76745 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 74317 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 74189 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 396736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 848 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 395043 # Number of instructions issued +system.cpu0.iq.iqInstsAdded 396725 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 846 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 395036 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8301 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 7145 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 289 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 190842 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.070000 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.087097 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 8285 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7136 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 287 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 190846 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.069920 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.087146 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 31780 16.65% 16.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5153 2.70% 19.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 75954 39.80% 59.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 31787 16.66% 16.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5152 2.70% 19.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 75953 39.80% 59.15% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::3 75299 39.46% 98.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1583 0.83% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1582 0.83% 99.44% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 772 0.40% 99.84% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 222 0.12% 99.96% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 71 0.04% 100.00% # Number of insts issued each cycle @@ -100,7 +100,7 @@ system.cpu0.iq.issued_per_cycle::8 8 0.00% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 190842 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 190846 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 35 14.96% 14.96% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 0 0.00% 14.96% # attempts to use FU when none available @@ -136,7 +136,7 @@ system.cpu0.iq.fu_full::MemWrite 119 50.85% 100.00% # at system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 166899 42.25% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 166893 42.25% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.25% # Type of FU issued @@ -165,85 +165,85 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.25% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.25% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.25% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 151806 38.43% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 151805 38.43% 80.68% # Type of FU issued system.cpu0.iq.FU_type_0::MemWrite 76338 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 395043 # Type of FU issued -system.cpu0.iq.rate 1.893510 # Inst issue rate +system.cpu0.iq.FU_type_0::total 395036 # Type of FU issued +system.cpu0.iq.rate 1.893422 # Inst issue rate system.cpu0.iq.fu_busy_cnt 234 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.000592 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 981260 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405931 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 393580 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_reads 981250 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405901 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 393576 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 395277 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 395270 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 73924 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1696 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1695 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations system.cpu0.iew.lsq.thread0.squashedStores 1038 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2024 # Number of cycles IEW is squashing +system.cpu0.iew.iewSquashCycles 2023 # Number of cycles IEW is squashing system.cpu0.iew.iewBlockCycles 1027 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 472386 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispatchedInsts 472373 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 357 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 152098 # Number of dispatched load instructions +system.cpu0.iew.iewDispLoadInsts 152097 # Number of dispatched load instructions system.cpu0.iew.iewDispStoreInsts 76745 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 747 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispNonSpecInsts 745 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 47 # Number of memory order violations +system.cpu0.iew.memOrderViolationEvents 45 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 734 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1201 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 394160 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 151501 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 883 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 394155 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 151500 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 881 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 74802 # number of nop insts executed -system.cpu0.iew.exec_refs 227729 # number of memory reference insts executed -system.cpu0.iew.exec_branches 78433 # Number of branches executed +system.cpu0.iew.exec_refs 227728 # number of memory reference insts executed +system.cpu0.iew.exec_branches 78432 # Number of branches executed system.cpu0.iew.exec_stores 76228 # Number of stores executed -system.cpu0.iew.exec_rate 1.889278 # Inst execution rate -system.cpu0.iew.wb_sent 393840 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 393580 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 233254 # num instructions producing a value -system.cpu0.iew.wb_consumers 235363 # num instructions consuming a value +system.cpu0.iew.exec_rate 1.889199 # Inst execution rate +system.cpu0.iew.wb_sent 393836 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 393576 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 233255 # num instructions producing a value +system.cpu0.iew.wb_consumers 235364 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.886498 # insts written-back per cycle +system.cpu0.iew.wb_rate 1.886424 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 9548 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 9535 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 188835 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.450812 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.134995 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 188840 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.450747 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.135046 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32324 17.12% 17.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78261 41.44% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2190 1.16% 59.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32333 17.12% 17.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78258 41.44% 58.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2188 1.16% 59.72% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 719 0.38% 60.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 660 0.35% 60.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 73613 38.98% 99.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 484 0.26% 99.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 659 0.35% 60.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 73614 38.98% 99.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 485 0.26% 99.69% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::7 280 0.15% 99.84% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 304 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 188835 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 188840 # Number of insts commited each cycle system.cpu0.commit.count 462799 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed system.cpu0.commit.refs 226109 # Number of memory references committed @@ -255,47 +255,47 @@ system.cpu0.commit.int_insts 311966 # Nu system.cpu0.commit.function_calls 223 # Number of function calls committed. system.cpu0.commit.bw_lim_events 304 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 659717 # The number of ROB reads -system.cpu0.rob.rob_writes 946730 # The number of ROB writes +system.cpu0.rob.rob_reads 659709 # The number of ROB reads +system.cpu0.rob.rob_writes 946703 # The number of ROB writes system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 17790 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.committedInsts 388389 # Number of Instructions Simulated system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated -system.cpu0.cpi 0.537168 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.537168 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.861616 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.861616 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 705237 # number of integer regfile reads -system.cpu0.int_regfile_writes 317939 # number of integer regfile writes +system.cpu0.cpi 0.537183 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.537183 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.861563 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.861563 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 705230 # number of integer regfile reads +system.cpu0.int_regfile_writes 317935 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 229506 # number of misc regfile reads +system.cpu0.misc_regfile_reads 229503 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.replacements 294 # number of replacements -system.cpu0.icache.tagsinuse 244.353542 # Cycle average of tags in use -system.cpu0.icache.total_refs 4816 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 244.353680 # Cycle average of tags in use +system.cpu0.icache.total_refs 4810 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.289157 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 8.278830 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 244.353542 # Average occupied blocks per context +system.cpu0.icache.occ_blocks::0 244.353680 # Average occupied blocks per context system.cpu0.icache.occ_percent::0 0.477253 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 4816 # number of ReadReq hits -system.cpu0.icache.demand_hits 4816 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 4816 # number of overall hits +system.cpu0.icache.ReadReq_hits 4810 # number of ReadReq hits +system.cpu0.icache.demand_hits 4810 # number of demand (read+write) hits +system.cpu0.icache.overall_hits 4810 # number of overall hits system.cpu0.icache.ReadReq_misses 705 # number of ReadReq misses system.cpu0.icache.demand_misses 705 # number of demand (read+write) misses system.cpu0.icache.overall_misses 705 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 27621000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 27621000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 27621000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 5521 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 5521 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 5521 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.127694 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.127694 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.127694 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 39178.723404 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 39178.723404 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 39178.723404 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency 27622000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 27622000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 27622000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses 5515 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses 5515 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses 5515 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate 0.127833 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate 0.127833 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate 0.127833 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency 39180.141844 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency 39180.141844 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency 39180.141844 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -312,60 +312,60 @@ system.cpu0.icache.ReadReq_mshr_misses 582 # nu system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 21370500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 21370500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 21370500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 21369000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 21369000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 21369000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.105416 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate 0.105416 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0.105416 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.072165 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36719.072165 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36719.072165 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate 0.105530 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate 0.105530 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate 0.105530 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36716.494845 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 139.605252 # Cycle average of tags in use -system.cpu0.dcache.total_refs 97332 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 138.901719 # Cycle average of tags in use +system.cpu0.dcache.total_refs 97328 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 559.379310 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 559.356322 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 140.432639 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -0.827387 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.274282 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.001616 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 77006 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::0 140.432794 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -1.531076 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.274283 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.002990 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits 77005 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits 75125 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits -system.cpu0.dcache.demand_hits 152131 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 152131 # number of overall hits +system.cpu0.dcache.demand_hits 152130 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits 152130 # number of overall hits system.cpu0.dcache.ReadReq_misses 517 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses system.cpu0.dcache.demand_misses 1057 # number of demand (read+write) misses system.cpu0.dcache.overall_misses 1057 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 14689500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 24684984 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency 14734500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 24692984 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency 371000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 39374484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 39374484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 77523 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency 39427484 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 39427484 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses 77522 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses 75665 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 153188 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 153188 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses 153187 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses 153187 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate 0.006669 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate 0.007137 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate 0.452381 # miss rate for SwapReq accesses system.cpu0.dcache.demand_miss_rate 0.006900 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate 0.006900 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 28412.959381 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 45712.933333 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency 28500 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency 45727.748148 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 37251.167455 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 37251.167455 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency 37301.309366 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency 37301.309366 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked @@ -385,42 +385,42 @@ system.cpu0.dcache.SwapReq_mshr_misses 19 # nu system.cpu0.dcache.demand_mshr_misses 362 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses 362 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 5221000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6255000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency 5255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6251500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency 314000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 11476000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 11476000 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 11506500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 11506500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002451 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002273 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate 0.452381 # mshr miss rate for SwapReq accesses system.cpu0.dcache.demand_mshr_miss_rate 0.002363 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate 0.002363 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27478.947368 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36366.279070 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27657.894737 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36345.930233 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 31701.657459 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 31701.657459 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31785.911602 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 174299 # number of cpu cycles simulated +system.cpu1.numCycles 174305 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 52109 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 49472 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 52112 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 49475 # Number of conditional branches predicted system.cpu1.BPredUnit.condIncorrect 1085 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 48061 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 46077 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 48064 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 46080 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.usedRAS 697 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 26834 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 291727 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52109 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46774 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 102734 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.Insts 291745 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52112 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46777 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 102740 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 3160 # Number of cycles fetch has spent squashing system.cpu1.fetch.BlockedCycles 32953 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -428,67 +428,67 @@ system.cpu1.fetch.NoActiveThreadStallCycles 6397 # system.cpu1.fetch.PendingTrapStallCycles 670 # Number of stall cycles due to pending traps system.cpu1.fetch.CacheLines 18341 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 181 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 171592 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.700120 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.136214 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 171598 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.700166 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.136223 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::0 68858 40.13% 40.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52174 30.41% 70.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52177 30.41% 70.53% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 5705 3.32% 73.86% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 3354 1.95% 75.81% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::4 589 0.34% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36150 21.07% 97.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 36153 21.07% 97.22% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::6 1352 0.79% 98.01% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::7 417 0.24% 98.26% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::8 2993 1.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 171592 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.298963 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.673716 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::total 171598 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.298970 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.673762 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 31662 # Number of cycles decode is idle system.cpu1.decode.BlockedCycles 29517 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 97188 # Number of cycles decode is running +system.cpu1.decode.RunCycles 97194 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 4829 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 1999 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 288965 # Number of instructions handled by decode +system.cpu1.decode.DecodedInsts 288983 # Number of instructions handled by decode system.cpu1.rename.SquashCycles 1999 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 32299 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 14957 # Number of cycles rename is blocking system.cpu1.rename.serializeStallCycles 13738 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 92828 # Number of cycles rename is running +system.cpu1.rename.RunCycles 92834 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 9374 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 287067 # Number of instructions processed by rename +system.cpu1.rename.RenamedInsts 287085 # Number of instructions processed by rename system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 200824 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 551922 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 551922 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 191180 # Number of HB maps that are committed +system.cpu1.rename.RenamedOperands 200836 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 551958 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 551958 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 191192 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 9644 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 1080 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1209 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 11997 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 82177 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38952 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39303 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34405 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 238842 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.memDep0.insertedLoads 82183 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38955 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39306 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 34408 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 238857 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 6064 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 241475 # Number of instructions issued +system.cpu1.iq.iqInstsIssued 241490 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued system.cpu1.iq.iqSquashedInstsExamined 8361 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu1.iq.iqSquashedOperandsExamined 7490 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 171592 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.407263 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.310082 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::samples 171598 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.407301 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.310079 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::0 65840 38.37% 38.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21732 12.66% 51.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 38889 22.66% 73.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40378 23.53% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21732 12.66% 51.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 38892 22.66% 73.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 40381 23.53% 97.23% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 3339 1.95% 99.18% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 1157 0.67% 99.85% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 163 0.09% 99.95% # Number of insts issued each cycle @@ -497,7 +497,7 @@ system.cpu1.iq.issued_per_cycle::8 54 0.03% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 171592 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 171598 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 12 4.55% 4.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available @@ -533,7 +533,7 @@ system.cpu1.iq.fu_full::MemWrite 190 71.97% 100.00% # at system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 116586 48.28% 48.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 116592 48.28% 48.28% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.28% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.28% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.28% # Type of FU issued @@ -562,27 +562,27 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.28% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.28% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.28% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.28% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 86332 35.75% 84.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 38557 15.97% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 86338 35.75% 84.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 38560 15.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 241475 # Type of FU issued -system.cpu1.iq.rate 1.385407 # Inst issue rate +system.cpu1.iq.FU_type_0::total 241490 # Type of FU issued +system.cpu1.iq.rate 1.385445 # Inst issue rate system.cpu1.iq.fu_busy_cnt 264 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.001093 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 654809 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 253298 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 240376 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_reads 654845 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 253312 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 240391 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 241739 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 241754 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34273 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 34276 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 1784 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 31 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations system.cpu1.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding @@ -592,89 +592,89 @@ system.cpu1.iew.iewIdleCycles 0 # Nu system.cpu1.iew.iewSquashCycles 1999 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 1765 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 285192 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispatchedInsts 285210 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 302 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 82177 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38952 # Number of dispatched store instructions +system.cpu1.iew.iewDispLoadInsts 82183 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38955 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 1043 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu1.iew.memOrderViolationEvents 30 # Number of memory order violations system.cpu1.iew.predictedTakenIncorrect 599 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 655 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 1254 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 240736 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 81423 # Number of load instructions executed +system.cpu1.iew.iewExecutedInsts 240751 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 81429 # Number of load instructions executed system.cpu1.iew.iewExecSquashedInsts 739 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40286 # number of nop insts executed -system.cpu1.iew.exec_refs 119940 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49359 # Number of branches executed -system.cpu1.iew.exec_stores 38517 # Number of stores executed -system.cpu1.iew.exec_rate 1.381167 # Inst execution rate -system.cpu1.iew.wb_sent 240543 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 240376 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 136693 # num instructions producing a value -system.cpu1.iew.wb_consumers 141184 # num instructions consuming a value +system.cpu1.iew.exec_nop 40289 # number of nop insts executed +system.cpu1.iew.exec_refs 119949 # number of memory reference insts executed +system.cpu1.iew.exec_branches 49362 # Number of branches executed +system.cpu1.iew.exec_stores 38520 # Number of stores executed +system.cpu1.iew.exec_rate 1.381205 # Inst execution rate +system.cpu1.iew.wb_sent 240558 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 240391 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 136702 # num instructions producing a value +system.cpu1.iew.wb_consumers 141193 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.379101 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.968190 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.379140 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.968192 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 275649 # The number of committed instructions +system.cpu1.commit.commitCommittedInsts 275667 # The number of committed instructions system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 163197 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.689057 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.043019 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::samples 163203 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.689105 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.043033 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::0 64641 39.61% 39.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47584 29.16% 68.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 47587 29.16% 68.77% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 5957 3.65% 72.42% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::3 6309 3.87% 76.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.96% 77.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 34599 21.20% 98.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1571 0.96% 77.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 34602 21.20% 98.45% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 646 0.40% 98.84% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 1051 0.64% 99.49% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 839 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 163197 # Number of insts commited each cycle -system.cpu1.commit.count 275649 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 163203 # Number of insts commited each cycle +system.cpu1.commit.count 275667 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 118484 # Number of memory references committed -system.cpu1.commit.loads 80393 # Number of loads committed +system.cpu1.commit.refs 118493 # Number of memory references committed +system.cpu1.commit.loads 80399 # Number of loads committed system.cpu1.commit.membars 4716 # Number of memory barriers committed -system.cpu1.commit.branches 48770 # Number of branches committed +system.cpu1.commit.branches 48773 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 189379 # Number of committed integer instructions. +system.cpu1.commit.int_insts 189391 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. system.cpu1.commit.bw_lim_events 839 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 446953 # The number of ROB reads -system.cpu1.rob.rob_writes 572364 # The number of ROB writes +system.cpu1.rob.rob_reads 446977 # The number of ROB reads +system.cpu1.rob.rob_writes 572400 # The number of ROB writes system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 231370 # Number of Instructions Simulated -system.cpu1.committedInsts_total 231370 # Number of Instructions Simulated -system.cpu1.cpi 0.753334 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.753334 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.327432 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.327432 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 418038 # number of integer regfile reads -system.cpu1.int_regfile_writes 194832 # number of integer regfile writes +system.cpu1.committedInsts 231385 # Number of Instructions Simulated +system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated +system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.753312 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.327472 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.327472 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 418065 # number of integer regfile reads +system.cpu1.int_regfile_writes 194844 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 121491 # number of misc regfile reads +system.cpu1.misc_regfile_reads 121500 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 84.540462 # Cycle average of tags in use +system.cpu1.icache.tagsinuse 84.541118 # Cycle average of tags in use system.cpu1.icache.total_refs 17870 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 84.540462 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.165118 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::0 84.541118 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.165119 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits 17870 # number of ReadReq hits system.cpu1.icache.demand_hits 17870 # number of demand (read+write) hits system.cpu1.icache.overall_hits 17870 # number of overall hits @@ -724,45 +724,45 @@ system.cpu1.icache.mshr_cap_events 0 # nu system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 18.587934 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44079 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 18.588243 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44082 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1469.300000 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1469.400000 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 24.401402 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -5.813468 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::0 24.401572 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -5.813330 # Average occupied blocks per context system.cpu1.dcache.occ_percent::0 0.047659 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::1 -0.011354 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 46657 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 37902 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits 46660 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits 37905 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits 84559 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 84559 # number of overall hits +system.cpu1.dcache.demand_hits 84565 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits 84565 # number of overall hits system.cpu1.dcache.ReadReq_misses 478 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses 124 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses system.cpu1.dcache.demand_misses 602 # number of demand (read+write) misses system.cpu1.dcache.overall_misses 602 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 10263500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency 10261500 # number of ReadReq miss cycles system.cpu1.dcache.WriteReq_miss_latency 2943000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 1147500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 13206500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 13206500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 47135 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 38026 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_miss_latency 1149500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency 13204500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 13204500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses 47138 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses 38029 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses 65 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 85161 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 85161 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.010141 # miss rate for ReadReq accesses +system.cpu1.dcache.demand_accesses 85167 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses 85167 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate 0.010140 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate 0.003261 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.007069 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.007069 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 21471.757322 # average ReadReq miss latency +system.cpu1.dcache.demand_miss_rate 0.007068 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate 0.007068 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency 21467.573222 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency 23733.870968 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 22067.307692 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 21937.707641 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 21937.707641 # average overall miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency 22105.769231 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency 21934.385382 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency 21934.385382 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -782,110 +782,110 @@ system.cpu1.dcache.SwapReq_mshr_misses 52 # nu system.cpu1.dcache.demand_mshr_misses 261 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses 261 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2081000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency 2079000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency 1617000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 991500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3698000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3698000 # number of overall MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency 993500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 3696000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 3696000 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003288 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002788 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002787 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses system.cpu1.dcache.demand_mshr_miss_rate 0.003065 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate 0.003065 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13425.806452 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13412.903226 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15254.716981 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19067.307692 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14168.582375 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14168.582375 # average overall mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19105.769231 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 14160.919540 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14160.919540 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 174012 # number of cpu cycles simulated +system.cpu2.numCycles 174018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 49364 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 46732 # Number of conditional branches predicted +system.cpu2.BPredUnit.lookups 49365 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 46733 # Number of conditional branches predicted system.cpu2.BPredUnit.condIncorrect 1149 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 45640 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 43565 # Number of BTB hits +system.cpu2.BPredUnit.BTBLookups 45641 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 43566 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.BPredUnit.usedRAS 657 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu2.fetch.icacheStallCycles 27807 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 273927 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 49364 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 44222 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 97488 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.Insts 273933 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 49365 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 44223 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 97490 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 3286 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 34436 # Number of cycles fetch has spent blocked +system.cpu2.fetch.BlockedCycles 34440 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 6393 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 776 # Number of stall cycles due to pending traps system.cpu2.fetch.CacheLines 19059 # Number of cache lines fetched system.cpu2.fetch.IcacheSquashes 204 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 168964 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.621215 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.105359 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 168970 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.621193 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.105353 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 71476 42.30% 42.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 49527 29.31% 71.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 71480 42.30% 42.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 49528 29.31% 71.62% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 6067 3.59% 75.21% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 3620 2.14% 77.35% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::4 727 0.43% 77.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 32912 19.48% 97.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 32913 19.48% 97.26% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::6 1356 0.80% 98.06% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::7 430 0.25% 98.31% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::8 2849 1.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 168964 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.283682 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.574185 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::total 168970 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.283678 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.574165 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 32851 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 30934 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 91695 # Number of cycles decode is running +system.cpu2.decode.BlockedCycles 30938 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 91697 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 5032 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 2059 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 271116 # Number of instructions handled by decode +system.cpu2.decode.DecodedInsts 271122 # Number of instructions handled by decode system.cpu2.rename.SquashCycles 2059 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 33552 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 15710 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14408 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 87161 # Number of cycles rename is running +system.cpu2.rename.serializeStallCycles 14412 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 87163 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 9681 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 268912 # Number of instructions processed by rename +system.cpu2.rename.RenamedInsts 268918 # Number of instructions processed by rename system.cpu2.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full system.cpu2.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 188421 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 514106 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 514106 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 178126 # Number of HB maps that are committed +system.cpu2.rename.RenamedOperands 188425 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 514118 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 514118 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 178130 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 10295 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 1067 # count of serializing insts renamed system.cpu2.rename.tempSerializingInsts 1200 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 12338 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 75825 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 35625 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 36244 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31069 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 223185 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6329 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 225866 # Number of instructions issued +system.cpu2.rename.skidInsts 12339 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 75827 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 35627 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 36245 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 31070 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 223191 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6330 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 225872 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8708 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedInstsExamined 8710 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu2.iq.iqSquashedOperandsExamined 8050 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 168964 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.336770 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.306398 # Number of insts issued each cycle +system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 168970 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.336758 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.306399 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 68732 40.68% 40.68% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 22583 13.37% 54.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 35943 21.27% 75.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 37102 21.96% 97.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 68735 40.68% 40.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 22585 13.37% 54.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 35942 21.27% 75.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 37104 21.96% 97.28% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::4 3355 1.99% 99.26% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::5 981 0.58% 99.84% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::6 168 0.10% 99.94% # Number of insts issued each cycle @@ -894,7 +894,7 @@ system.cpu2.iq.issued_per_cycle::8 58 0.03% 100.00% # Nu system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 168964 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 168970 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 19 7.04% 7.04% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available @@ -930,7 +930,7 @@ system.cpu2.iq.fu_full::MemWrite 190 70.37% 100.00% # at system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 110492 48.92% 48.92% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 110495 48.92% 48.92% # Type of FU issued system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.92% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.92% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.92% # Type of FU issued @@ -959,28 +959,28 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.92% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.92% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.92% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.92% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 80155 35.49% 84.41% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 35219 15.59% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 80157 35.49% 84.41% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 35220 15.59% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 225866 # Type of FU issued -system.cpu2.iq.rate 1.297991 # Inst issue rate +system.cpu2.iq.FU_type_0::total 225872 # Type of FU issued +system.cpu2.iq.rate 1.297981 # Inst issue rate system.cpu2.iq.fu_busy_cnt 270 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.001195 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 620969 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 238254 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 224626 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_reads 620987 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 238263 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 224632 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 226136 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 226142 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 30939 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 30940 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu2.iew.lsq.thread0.squashedLoads 1843 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu2.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 851 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedStores 852 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled @@ -989,89 +989,89 @@ system.cpu2.iew.iewIdleCycles 0 # Nu system.cpu2.iew.iewSquashCycles 2059 # Number of cycles IEW is squashing system.cpu2.iew.iewBlockCycles 1941 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 266778 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispatchedInsts 266786 # Number of instructions dispatched to IQ system.cpu2.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 75825 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 35625 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1017 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewDispLoadInsts 75827 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 35627 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1018 # Number of dispatched non-speculative instructions system.cpu2.iew.iewIQFullEvents 57 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu2.iew.memOrderViolationEvents 32 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 683 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 611 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.branchMispredicts 1294 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 225033 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 74984 # Number of load instructions executed +system.cpu2.iew.iewExecutedInsts 225039 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 74986 # Number of load instructions executed system.cpu2.iew.iewExecSquashedInsts 833 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 37264 # number of nop insts executed -system.cpu2.iew.exec_refs 110168 # number of memory reference insts executed -system.cpu2.iew.exec_branches 46372 # Number of branches executed -system.cpu2.iew.exec_stores 35184 # Number of stores executed -system.cpu2.iew.exec_rate 1.293204 # Inst execution rate -system.cpu2.iew.wb_sent 224799 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 224626 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 127004 # num instructions producing a value -system.cpu2.iew.wb_consumers 131415 # num instructions consuming a value +system.cpu2.iew.exec_nop 37265 # number of nop insts executed +system.cpu2.iew.exec_refs 110171 # number of memory reference insts executed +system.cpu2.iew.exec_branches 46373 # Number of branches executed +system.cpu2.iew.exec_stores 35185 # Number of stores executed +system.cpu2.iew.exec_rate 1.293194 # Inst execution rate +system.cpu2.iew.wb_sent 224805 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 224632 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 127007 # num instructions producing a value +system.cpu2.iew.wb_consumers 131418 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.290865 # insts written-back per cycle +system.cpu2.iew.wb_rate 1.290855 # insts written-back per cycle system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 256702 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 10072 # The number of squashed insts skipped by commit +system.cpu2.commit.commitCommittedInsts 256708 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 10074 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 160513 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.599260 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.012930 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::samples 160519 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.599237 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.012927 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 67920 42.31% 42.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 44667 27.83% 70.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 67924 42.32% 42.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 44668 27.83% 70.14% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::2 6005 3.74% 73.88% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::3 6542 4.08% 77.96% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::4 1606 1.00% 78.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 31384 19.55% 98.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 31385 19.55% 98.51% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::6 504 0.31% 98.83% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::7 1049 0.65% 99.48% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::8 836 0.52% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 160513 # Number of insts commited each cycle -system.cpu2.commit.count 256702 # Number of instructions committed +system.cpu2.commit.committed_per_cycle::total 160519 # Number of insts commited each cycle +system.cpu2.commit.count 256708 # Number of instructions committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 108756 # Number of memory references committed -system.cpu2.commit.loads 73982 # Number of loads committed +system.cpu2.commit.refs 108759 # Number of memory references committed +system.cpu2.commit.loads 73984 # Number of loads committed system.cpu2.commit.membars 4966 # Number of memory barriers committed -system.cpu2.commit.branches 45703 # Number of branches committed +system.cpu2.commit.branches 45704 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 176575 # Number of committed integer instructions. +system.cpu2.commit.int_insts 176579 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. system.cpu2.commit.bw_lim_events 836 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 425864 # The number of ROB reads -system.cpu2.rob.rob_writes 535611 # The number of ROB writes +system.cpu2.rob.rob_reads 425878 # The number of ROB reads +system.cpu2.rob.rob_writes 535627 # The number of ROB writes system.cpu2.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.committedInsts 215249 # Number of Instructions Simulated -system.cpu2.committedInsts_total 215249 # Number of Instructions Simulated -system.cpu2.cpi 0.808422 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.808422 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.236978 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.236978 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 389041 # number of integer regfile reads -system.cpu2.int_regfile_writes 181914 # number of integer regfile writes +system.cpu2.committedInsts 215254 # Number of Instructions Simulated +system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated +system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.808431 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.236964 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.236964 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 389052 # number of integer regfile reads +system.cpu2.int_regfile_writes 181919 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 111743 # number of misc regfile reads +system.cpu2.misc_regfile_reads 111746 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes system.cpu2.icache.replacements 321 # number of replacements -system.cpu2.icache.tagsinuse 85.226905 # Cycle average of tags in use +system.cpu2.icache.tagsinuse 85.227474 # Cycle average of tags in use system.cpu2.icache.total_refs 18578 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 85.226905 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.166459 # Average percentage of cache occupancy +system.cpu2.icache.occ_blocks::0 85.227474 # Average occupied blocks per context +system.cpu2.icache.occ_percent::0 0.166460 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits 18578 # number of ReadReq hits system.cpu2.icache.demand_hits 18578 # number of demand (read+write) hits system.cpu2.icache.overall_hits 18578 # number of overall hits @@ -1121,45 +1121,45 @@ system.cpu2.icache.mshr_cap_events 0 # nu system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 19.370562 # Cycle average of tags in use -system.cpu2.dcache.total_refs 40685 # Total number of references to valid blocks. +system.cpu2.dcache.tagsinuse 19.370911 # Cycle average of tags in use +system.cpu2.dcache.total_refs 40686 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1356.166667 # Average number of references to valid blocks. +system.cpu2.dcache.avg_refs 1356.200000 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 26.582675 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -7.212113 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.051919 # Average percentage of cache occupancy +system.cpu2.dcache.occ_blocks::0 26.582846 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -7.211935 # Average occupied blocks per context +system.cpu2.dcache.occ_percent::0 0.051920 # Average percentage of cache occupancy system.cpu2.dcache.occ_percent::1 -0.014086 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 43568 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 34580 # number of WriteReq hits +system.cpu2.dcache.ReadReq_hits 43569 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits 34581 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits 78148 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 78148 # number of overall hits +system.cpu2.dcache.demand_hits 78150 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits 78150 # number of overall hits system.cpu2.dcache.ReadReq_misses 459 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses 120 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses 61 # number of SwapReq misses system.cpu2.dcache.demand_misses 579 # number of demand (read+write) misses system.cpu2.dcache.overall_misses 579 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 10996500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency 10999500 # number of ReadReq miss cycles system.cpu2.dcache.WriteReq_miss_latency 2980500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 1342500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 13977000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 13977000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 44027 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 34700 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_miss_latency 1343500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency 13980000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency 13980000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses 44028 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses 34701 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses 74 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 78727 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 78727 # number of overall (read+write) accesses +system.cpu2.dcache.demand_accesses 78729 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses 78729 # number of overall (read+write) accesses system.cpu2.dcache.ReadReq_miss_rate 0.010425 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate 0.003458 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate 0.824324 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.007355 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.007355 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 23957.516340 # average ReadReq miss latency +system.cpu2.dcache.demand_miss_rate 0.007354 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate 0.007354 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency 23964.052288 # average ReadReq miss latency system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 22008.196721 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 24139.896373 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 24139.896373 # average overall miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 22024.590164 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency 24145.077720 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency 24145.077720 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1179,42 +1179,42 @@ system.cpu2.dcache.SwapReq_mshr_misses 61 # nu system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2379000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency 2380000 # number of ReadReq MSHR miss cycles system.cpu2.dcache.WriteReq_mshr_miss_latency 1660000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 1159500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 4039000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 4039000 # number of overall MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 1160500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency 4040000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency 4040000 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003680 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003679 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002939 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate 0.824324 # mshr miss rate for SwapReq accesses system.cpu2.dcache.demand_mshr_miss_rate 0.003353 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate 0.003353 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14685.185185 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14691.358025 # average ReadReq mshr miss latency system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19008.196721 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 15299.242424 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 15299.242424 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19024.590164 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173746 # number of cpu cycles simulated +system.cpu3.numCycles 173752 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 43971 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 41359 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 43974 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 41362 # Number of conditional branches predicted system.cpu3.BPredUnit.condIncorrect 1065 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 40215 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 38240 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 40218 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 38243 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.BPredUnit.usedRAS 627 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu3.fetch.icacheStallCycles 31228 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 238324 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 43971 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 38867 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 88896 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.Insts 238342 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 43974 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 38870 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 88902 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.SquashCycles 3085 # Number of cycles fetch has spent squashing system.cpu3.fetch.BlockedCycles 41810 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs @@ -1222,67 +1222,67 @@ system.cpu3.fetch.NoActiveThreadStallCycles 6387 # system.cpu3.fetch.PendingTrapStallCycles 706 # Number of stall cycles due to pending traps system.cpu3.fetch.CacheLines 22959 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 170976 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.393903 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.001998 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 170982 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.393960 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.002021 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::0 82080 48.01% 48.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 46270 27.06% 75.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 46273 27.06% 75.07% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::2 8028 4.70% 79.76% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::3 3581 2.09% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 661 0.39% 82.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 25731 15.05% 97.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 661 0.39% 82.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 25734 15.05% 97.30% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::6 1333 0.78% 98.07% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::7 378 0.22% 98.30% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::8 2914 1.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 170976 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.253076 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.371680 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::total 170982 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.253085 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.371737 # Number of inst fetches per cycle system.cpu3.decode.IdleCycles 38250 # Number of cycles decode is idle system.cpu3.decode.BlockedCycles 36210 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 81243 # Number of cycles decode is running +system.cpu3.decode.RunCycles 81249 # Number of cycles decode is running system.cpu3.decode.UnblockCycles 6942 # Number of cycles decode is unblocking system.cpu3.decode.SquashCycles 1944 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 235564 # Number of instructions handled by decode +system.cpu3.decode.DecodedInsts 235582 # Number of instructions handled by decode system.cpu3.rename.SquashCycles 1944 # Number of cycles rename is squashing system.cpu3.rename.IdleCycles 38898 # Number of cycles rename is idle system.cpu3.rename.BlockCycles 21197 # Number of cycles rename is blocking system.cpu3.rename.serializeStallCycles 14171 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 74835 # Number of cycles rename is running +system.cpu3.rename.RunCycles 74841 # Number of cycles rename is running system.cpu3.rename.UnblockCycles 13544 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 233632 # Number of instructions processed by rename +system.cpu3.rename.RenamedInsts 233650 # Number of instructions processed by rename system.cpu3.rename.IQFullEvents 34 # Number of times rename has blocked due to IQ full system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 161364 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 435904 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 435904 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 151913 # Number of HB maps that are committed +system.cpu3.rename.RenamedOperands 161376 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 435940 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 435940 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 151925 # Number of HB maps that are committed system.cpu3.rename.UndoneMaps 9451 # Number of HB maps that are undone due to squashing system.cpu3.rename.serializingInsts 1060 # count of serializing insts renamed system.cpu3.rename.tempSerializingInsts 1201 # count of temporary serializing insts renamed system.cpu3.rename.skidInsts 16222 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 63587 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 28570 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31149 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24015 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 191265 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.memDep0.insertedLoads 63593 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 28573 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 31152 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 24018 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 191280 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqNonSpecInstsAdded 8270 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 196039 # Number of instructions issued +system.cpu3.iq.iqInstsIssued 196054 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued system.cpu3.iq.iqSquashedInstsExamined 8200 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu3.iq.iqSquashedOperandsExamined 7610 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 629 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 170976 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.146588 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.276389 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::samples 170982 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.146635 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.276395 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::0 79237 46.34% 46.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28336 16.57% 62.92% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 28714 16.79% 79.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30132 17.62% 97.33% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28336 16.57% 62.91% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 28717 16.80% 79.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30135 17.62% 97.33% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::4 3289 1.92% 99.26% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::5 1034 0.60% 99.86% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::6 139 0.08% 99.94% # Number of insts issued each cycle @@ -1291,7 +1291,7 @@ system.cpu3.iq.issued_per_cycle::8 54 0.03% 100.00% # Nu system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 170976 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 170982 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IntAlu 11 4.49% 4.49% # attempts to use FU when none available system.cpu3.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available @@ -1327,7 +1327,7 @@ system.cpu3.iq.fu_full::MemWrite 190 77.55% 100.00% # at system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 97956 49.97% 49.97% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 97962 49.97% 49.97% # Type of FU issued system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.97% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.97% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.97% # Type of FU issued @@ -1356,27 +1356,27 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.97% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.97% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.97% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.97% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 69913 35.66% 85.63% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 28170 14.37% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 69919 35.66% 85.63% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 28173 14.37% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 196039 # Type of FU issued -system.cpu3.iq.rate 1.128308 # Inst issue rate +system.cpu3.iq.FU_type_0::total 196054 # Type of FU issued +system.cpu3.iq.rate 1.128355 # Inst issue rate system.cpu3.iq.fu_busy_cnt 245 # FU busy when requested system.cpu3.iq.fu_busy_rate 0.001250 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 563302 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 207766 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 194919 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_reads 563338 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 207780 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 194934 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 196284 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 196299 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 23896 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 23899 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread0.squashedLoads 1728 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 31 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations system.cpu3.iew.lsq.thread0.squashedStores 841 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding @@ -1386,89 +1386,89 @@ system.cpu3.iew.iewIdleCycles 0 # Nu system.cpu3.iew.iewSquashCycles 1944 # Number of cycles IEW is squashing system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 231697 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispatchedInsts 231715 # Number of instructions dispatched to IQ system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 63587 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 28570 # Number of dispatched store instructions +system.cpu3.iew.iewDispLoadInsts 63593 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 28573 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 992 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu3.iew.memOrderViolationEvents 30 # Number of memory order violations system.cpu3.iew.predictedTakenIncorrect 631 # Number of branches that were predicted taken incorrectly system.cpu3.iew.predictedNotTakenIncorrect 549 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.branchMispredicts 1180 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 195258 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 62772 # Number of load instructions executed +system.cpu3.iew.iewExecutedInsts 195273 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 62778 # Number of load instructions executed system.cpu3.iew.iewExecSquashedInsts 781 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32162 # number of nop insts executed -system.cpu3.iew.exec_refs 90911 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41188 # Number of branches executed -system.cpu3.iew.exec_stores 28139 # Number of stores executed -system.cpu3.iew.exec_rate 1.123813 # Inst execution rate -system.cpu3.iew.wb_sent 195076 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 194919 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 107666 # num instructions producing a value -system.cpu3.iew.wb_consumers 111983 # num instructions consuming a value +system.cpu3.iew.exec_nop 32165 # number of nop insts executed +system.cpu3.iew.exec_refs 90920 # number of memory reference insts executed +system.cpu3.iew.exec_branches 41191 # Number of branches executed +system.cpu3.iew.exec_stores 28142 # Number of stores executed +system.cpu3.iew.exec_rate 1.123860 # Inst execution rate +system.cpu3.iew.wb_sent 195091 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 194934 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 107675 # num instructions producing a value +system.cpu3.iew.wb_consumers 111992 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.121862 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961450 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.121909 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.961453 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 222278 # The number of committed instructions +system.cpu3.commit.commitCommittedInsts 222296 # The number of committed instructions system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 162646 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.366637 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.912094 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::samples 162652 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.366697 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.912123 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::0 80351 49.40% 49.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 39427 24.24% 73.64% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 39430 24.24% 73.64% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::2 6019 3.70% 77.34% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::3 8502 5.23% 82.57% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::4 1632 1.00% 83.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24254 14.91% 98.49% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 24257 14.91% 98.49% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::6 559 0.34% 98.83% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::7 1061 0.65% 99.48% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 841 0.52% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 162646 # Number of insts commited each cycle -system.cpu3.commit.count 222278 # Number of instructions committed +system.cpu3.commit.committed_per_cycle::total 162652 # Number of insts commited each cycle +system.cpu3.commit.count 222296 # Number of instructions committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 89588 # Number of memory references committed -system.cpu3.commit.loads 61859 # Number of loads committed +system.cpu3.commit.refs 89597 # Number of memory references committed +system.cpu3.commit.loads 61865 # Number of loads committed system.cpu3.commit.membars 6925 # Number of memory barriers committed -system.cpu3.commit.branches 40615 # Number of branches committed +system.cpu3.commit.branches 40618 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 152323 # Number of committed integer instructions. +system.cpu3.commit.int_insts 152335 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 841 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 392905 # The number of ROB reads -system.cpu3.rob.rob_writes 465320 # The number of ROB writes +system.cpu3.rob.rob_reads 392929 # The number of ROB reads +system.cpu3.rob.rob_writes 465356 # The number of ROB writes system.cpu3.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.committedInsts 183950 # Number of Instructions Simulated -system.cpu3.committedInsts_total 183950 # Number of Instructions Simulated -system.cpu3.cpi 0.944528 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.944528 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.058729 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.058729 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 330902 # number of integer regfile reads -system.cpu3.int_regfile_writes 155336 # number of integer regfile writes +system.cpu3.committedInsts 183965 # Number of Instructions Simulated +system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated +system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.944484 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.058779 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.058779 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 330929 # number of integer regfile reads +system.cpu3.int_regfile_writes 155348 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 92466 # number of misc regfile reads +system.cpu3.misc_regfile_reads 92475 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.005311 # Cycle average of tags in use +system.cpu3.icache.tagsinuse 80.006059 # Cycle average of tags in use system.cpu3.icache.total_refs 22493 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 52.800469 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 80.005311 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.156260 # Average percentage of cache occupancy +system.cpu3.icache.occ_blocks::0 80.006059 # Average occupied blocks per context +system.cpu3.icache.occ_percent::0 0.156262 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits 22493 # number of ReadReq hits system.cpu3.icache.demand_hits 22493 # number of demand (read+write) hits system.cpu3.icache.overall_hits 22493 # number of overall hits @@ -1518,20 +1518,20 @@ system.cpu3.icache.mshr_cap_events 0 # nu system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 13.455114 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33581 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 13.455705 # Cycle average of tags in use +system.cpu3.dcache.total_refs 33584 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1157.965517 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1158.068966 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 23.407144 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -9.952030 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.045717 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.019438 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 38409 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 27534 # number of WriteReq hits +system.cpu3.dcache.occ_blocks::0 23.407477 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -9.951772 # Average occupied blocks per context +system.cpu3.dcache.occ_percent::0 0.045718 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::1 -0.019437 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits 38412 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits 27537 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits 65943 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 65943 # number of overall hits +system.cpu3.dcache.demand_hits 65949 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits 65949 # number of overall hits system.cpu3.dcache.ReadReq_misses 448 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses 125 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses 56 # number of SwapReq misses @@ -1542,11 +1542,11 @@ system.cpu3.dcache.WriteReq_miss_latency 2911000 # nu system.cpu3.dcache.SwapReq_miss_latency 1350500 # number of SwapReq miss cycles system.cpu3.dcache.demand_miss_latency 12269000 # number of demand (read+write) miss cycles system.cpu3.dcache.overall_miss_latency 12269000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 38857 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 27659 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses 38860 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses 27662 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 66516 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 66516 # number of overall (read+write) accesses +system.cpu3.dcache.demand_accesses 66522 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses 66522 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate 0.011529 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate 0.004519 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate 0.800000 # miss rate for SwapReq accesses @@ -1583,7 +1583,7 @@ system.cpu3.dcache.demand_mshr_miss_latency 3842500 # system.cpu3.dcache.overall_mshr_miss_latency 3842500 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004349 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003905 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003904 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate 0.800000 # mshr miss rate for SwapReq accesses system.cpu3.dcache.demand_mshr_miss_rate 0.004164 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate 0.004164 # mshr miss rate for overall accesses @@ -1597,16 +1597,16 @@ system.cpu3.dcache.mshr_cap_events 0 # nu system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 428.230348 # Cycle average of tags in use +system.l2c.tagsinuse 428.231635 # Cycle average of tags in use system.l2c.total_refs 1446 # Total number of references to valid blocks. system.l2c.sampled_refs 527 # Sample count of references to valid blocks. system.l2c.avg_refs 2.743833 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 347.173687 # Average occupied blocks per context -system.l2c.occ_blocks::1 11.269498 # Average occupied blocks per context -system.l2c.occ_blocks::2 63.254207 # Average occupied blocks per context -system.l2c.occ_blocks::3 1.567246 # Average occupied blocks per context -system.l2c.occ_blocks::4 4.965709 # Average occupied blocks per context +system.l2c.occ_blocks::0 347.174574 # Average occupied blocks per context +system.l2c.occ_blocks::1 11.269547 # Average occupied blocks per context +system.l2c.occ_blocks::2 63.254631 # Average occupied blocks per context +system.l2c.occ_blocks::3 1.567259 # Average occupied blocks per context +system.l2c.occ_blocks::4 4.965624 # Average occupied blocks per context system.l2c.occ_percent::0 0.005297 # Average percentage of cache occupancy system.l2c.occ_percent::1 0.000172 # Average percentage of cache occupancy system.l2c.occ_percent::2 0.000965 # Average percentage of cache occupancy |