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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:40 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:40 -0800 |
commit | ab2f864af2fd38cbf141708550409f3ca72c675f (patch) | |
tree | 75b861a290240275d872a58d393a6d6f7e5598d5 /tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt | |
parent | ceae8383ffeebdc2c12d9a383941c62653471de1 (diff) | |
download | gem5-ab2f864af2fd38cbf141708550409f3ca72c675f.tar.xz |
m5: Regression Tester Update
This patch includes the necessary regression updates to test the new ruby
configuration system. The patch includes support for multiple ruby protocols
and adds the ruby random tester. The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses. These tests can be
added back in when ruby supports atomic mode for real.
--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
Diffstat (limited to 'tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt')
-rw-r--r-- | tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt new file mode 100644 index 000000000..f29c9ce28 --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_mem_usage 344972 # Number of bytes of host memory used +host_seconds 51.38 # Real time elapsed on the host +host_tick_rate 72178 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks +sim_seconds 0.003709 # Number of seconds simulated +sim_ticks 3708588 # Number of ticks simulated +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu0.num_reads 98991 # number of read accesses completed +system.cpu0.num_writes 53491 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 53368 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 98059 # number of read accesses completed +system.cpu2.num_writes 52566 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 97980 # number of read accesses completed +system.cpu3.num_writes 52705 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 98000 # number of read accesses completed +system.cpu4.num_writes 52774 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 97409 # number of read accesses completed +system.cpu5.num_writes 52453 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 96358 # number of read accesses completed +system.cpu6.num_writes 51488 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 95731 # number of read accesses completed +system.cpu7.num_writes 51690 # number of write accesses completed + +---------- End Simulation Statistics ---------- |