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author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:11 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-07 19:23:11 -0800 |
commit | 1b64bfa933745294667158d0ce22180780b2a22e (patch) | |
tree | 11822ba69a5ec4c1c4b7ad72fcf08c87e143e4fe /tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt | |
parent | 44e5e7e0533ba2544f2d37f8e051a0422966bd9b (diff) | |
download | gem5-1b64bfa933745294667158d0ce22180780b2a22e.tar.xz |
Stats: Back out broken update.
Diffstat (limited to 'tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt')
-rw-r--r-- | tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index e69de29bb..ce3cfcb57 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_mem_usage 290548 # Number of bytes of host memory used +host_seconds 82.41 # Real time elapsed on the host +host_tick_rate 45509 # Simulator tick rate (ticks/s) +sim_freq 1000000000 # Frequency of simulated ticks +sim_seconds 0.003750 # Number of seconds simulated +sim_ticks 3750455 # Number of ticks simulated +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54108 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99918 # number of read accesses completed +system.cpu1.num_writes 53757 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99521 # number of read accesses completed +system.cpu2.num_writes 53948 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 98786 # number of read accesses completed +system.cpu3.num_writes 53362 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 98631 # number of read accesses completed +system.cpu4.num_writes 52746 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 98242 # number of read accesses completed +system.cpu5.num_writes 52924 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 97407 # number of read accesses completed +system.cpu6.num_writes 52658 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 96638 # number of read accesses completed +system.cpu7.num_writes 51757 # number of write accesses completed + +---------- End Simulation Statistics ---------- |