summaryrefslogtreecommitdiff
path: root/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
diff options
context:
space:
mode:
authorBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:40 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:40 -0800
commitab2f864af2fd38cbf141708550409f3ca72c675f (patch)
tree75b861a290240275d872a58d393a6d6f7e5598d5 /tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
parentceae8383ffeebdc2c12d9a383941c62653471de1 (diff)
downloadgem5-ab2f864af2fd38cbf141708550409f3ca72c675f.tar.xz
m5: Regression Tester Update
This patch includes the necessary regression updates to test the new ruby configuration system. The patch includes support for multiple ruby protocols and adds the ruby random tester. The patch removes atomic mode test for ruby since ruby does not support atomic mode acceses. These tests can be added back in when ruby supports atomic mode for real. --HG-- rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
Diffstat (limited to 'tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt')
-rw-r--r--tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt42
1 files changed, 21 insertions, 21 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 83402b5fb..e2300d357 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -1,34 +1,34 @@
---------- Begin Simulation Statistics ----------
-host_mem_usage 1414304 # Number of bytes of host memory used
-host_seconds 219.48 # Real time elapsed on the host
-host_tick_rate 20525 # Simulator tick rate (ticks/s)
-sim_freq 1000000000000 # Frequency of simulated ticks
-sim_seconds 0.000005 # Number of seconds simulated
-sim_ticks 4504972 # Number of ticks simulated
+host_mem_usage 344584 # Number of bytes of host memory used
+host_seconds 85.64 # Real time elapsed on the host
+host_tick_rate 128940 # Simulator tick rate (ticks/s)
+sim_freq 1000000000 # Frequency of simulated ticks
+sim_seconds 0.011043 # Number of seconds simulated
+sim_ticks 11043028 # Number of ticks simulated
system.cpu0.num_copies 0 # number of copy accesses completed
system.cpu0.num_reads 100000 # number of read accesses completed
-system.cpu0.num_writes 54115 # number of write accesses completed
+system.cpu0.num_writes 53371 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 92132 # number of read accesses completed
-system.cpu1.num_writes 49991 # number of write accesses completed
+system.cpu1.num_reads 99516 # number of read accesses completed
+system.cpu1.num_writes 53857 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 93521 # number of read accesses completed
-system.cpu2.num_writes 50418 # number of write accesses completed
+system.cpu2.num_reads 99479 # number of read accesses completed
+system.cpu2.num_writes 53903 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 89205 # number of read accesses completed
-system.cpu3.num_writes 48106 # number of write accesses completed
+system.cpu3.num_reads 99825 # number of read accesses completed
+system.cpu3.num_writes 53546 # number of write accesses completed
system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 97961 # number of read accesses completed
-system.cpu4.num_writes 52598 # number of write accesses completed
+system.cpu4.num_reads 99698 # number of read accesses completed
+system.cpu4.num_writes 53673 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 92452 # number of read accesses completed
-system.cpu5.num_writes 49744 # number of write accesses completed
+system.cpu5.num_reads 99797 # number of read accesses completed
+system.cpu5.num_writes 53574 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 91570 # number of read accesses completed
-system.cpu6.num_writes 49935 # number of write accesses completed
+system.cpu6.num_reads 99782 # number of read accesses completed
+system.cpu6.num_writes 53589 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 96862 # number of read accesses completed
-system.cpu7.num_writes 51935 # number of write accesses completed
+system.cpu7.num_reads 99603 # number of read accesses completed
+system.cpu7.num_writes 53767 # number of write accesses completed
---------- End Simulation Statistics ----------