diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-05-19 00:24:34 -0400 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-05-19 00:24:34 -0400 |
| commit | 0305159abf40765c6b8c506c777e3f62f3b6227e (patch) | |
| tree | 9e6f19f64d626708141076ebbb4daa44fbe513ba /tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini | |
| parent | a8278c3bde2ba9abc2820afafa9d0e766e36b2c8 (diff) | |
| download | gem5-0305159abf40765c6b8c506c777e3f62f3b6227e.tar.xz | |
PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py:
PhysicalMemory has vector of uniform ports instead of one special one.
Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
Add comment.
--HG--
extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
Diffstat (limited to 'tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini')
| -rw-r--r-- | tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index bf66a6947..a6e3a8480 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -22,7 +22,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.port +functional=system.funcmem.port[0] test=system.cpu0.l1c.cpu_side [system.cpu0.l1c] @@ -82,7 +82,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[1] test=system.cpu1.l1c.cpu_side [system.cpu1.l1c] @@ -142,7 +142,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[2] test=system.cpu2.l1c.cpu_side [system.cpu2.l1c] @@ -202,7 +202,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[3] test=system.cpu3.l1c.cpu_side [system.cpu3.l1c] @@ -262,7 +262,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[4] test=system.cpu4.l1c.cpu_side [system.cpu4.l1c] @@ -322,7 +322,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[5] test=system.cpu5.l1c.cpu_side [system.cpu5.l1c] @@ -382,7 +382,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[6] test=system.cpu6.l1c.cpu_side [system.cpu6.l1c] @@ -442,7 +442,7 @@ percent_source_unaligned=50 percent_uncacheable=10 progress_interval=10000 trace_addr=0 -functional=system.funcmem.functional +functional=system.funcmem.port[7] test=system.cpu7.l1c.cpu_side [system.cpu7.l1c] @@ -495,8 +495,7 @@ file= latency=1 range=0:134217727 zero=false -functional=system.cpu7.functional -port=system.cpu0.functional +port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional [system.l2c] type=BaseCache @@ -543,7 +542,7 @@ bus_id=0 clock=2 responder_set=false width=16 -port=system.l2c.mem_side system.physmem.port +port=system.l2c.mem_side system.physmem.port[0] [system.physmem] type=PhysicalMemory |