Reference updates. Since split cache is gone, a lot of config.ini changes, and minor changes to stats that are likely due to the decoupling of insertions/evictions in the cache.

4 files changed, 10 insertions, 36 deletions

diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
index ce3301742..3ae48f3b4 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -33,7 +33,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -51,8 +50,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -85,7 +82,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -103,8 +99,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -137,7 +131,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -155,8 +148,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -189,7 +180,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -207,8 +197,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -241,7 +229,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -259,8 +246,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -293,7 +278,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -311,8 +295,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -345,7 +327,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -363,8 +344,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -397,7 +376,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=12
@@ -415,8 +393,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=32768
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=8
 trace_addr=0
@@ -443,7 +419,6 @@ block_size=64
 cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
-lifo=false
 max_miss_count=0
 mem_side_filter_ranges=
 mshrs=92
@@ -461,8 +436,6 @@ prefetcher_size=100
 prioritizeRequests=false
 repl=Null
 size=65536
-split=false
-split_size=0
 subblock_size=0
 tgts_per_mshr=16
 trace_addr=0
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
index c4e841ee5..765a44d97 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
@@ -1,8 +1,8 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 323512                       # Number of bytes of host memory used
-host_seconds                                   193.82                       # Real time elapsed on the host
-host_tick_rate                                1387453                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 324448                       # Number of bytes of host memory used
+host_seconds                                   222.79                       # Real time elapsed on the host
+host_tick_rate                                1207024                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000269                       # Number of seconds simulated
 sim_ticks                                   268915439                       # Number of ticks simulated
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
index a93b081cc..507652626 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
@@ -1,4 +1,3 @@
-warn: Entering event queue @ 0.  Starting simulation...
 system.cpu3: completed 10000 read accesses @26226880
 system.cpu6: completed 10000 read accesses @26416342
 system.cpu2: completed 10000 read accesses @26427251
@@ -72,3 +71,4 @@ system.cpu5: completed 90000 read accesses @243633950
 system.cpu4: completed 90000 read accesses @243710816
 system.cpu2: completed 90000 read accesses @243974160
 system.cpu6: completed 100000 read accesses @268915439
+warn: be nice to actually delete the event here
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
index 0fc21b2ef..048969ee8 100755
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
@@ -5,11 +5,12 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Sep 27 2008 21:08:21
-M5 revision 5571:7f81bb1690686883c5b93e8343068a001faf5083
-M5 commit date Sat Sep 27 21:03:50 2008 -0700
-M5 started Sep 27 2008 21:09:08
-M5 executing on piton
+M5 compiled Nov  5 2008 18:30:06
+M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69
+M5 commit date Wed Nov 05 16:19:17 2008 -0500
+M5 started Nov  5 2008 19:01:52
+M5 executing on zizzer
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re --stdout-file stdout --stderr-file stderr tests/run.py quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 268915439 because maximum number of loads reached