diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-12 19:43:55 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-08-12 19:43:55 -0400 |
| commit | d114e5fae6ffb83a1145208532def7654cc9dd75 (patch) | |
| tree | d54b53635428baefbb0ef25715e1059a2bad1185 /tests/quick/50.memtest | |
| parent | 02353a60ee6ce831302067aae38bc31b739f14e5 (diff) | |
| download | gem5-d114e5fae6ffb83a1145208532def7654cc9dd75.tar.xz | |
Regression: Update stats for cache changes.
--HG--
extra : convert_revision : 005672e722dec00cb4c38501b5189b4eb7515ca1
Diffstat (limited to 'tests/quick/50.memtest')
4 files changed, 594 insertions, 576 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini index 8bac0dec4..c73e5910f 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini @@ -30,10 +30,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -80,10 +82,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -130,10 +134,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -180,10 +186,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -230,10 +238,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -280,10 +290,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -330,10 +342,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -380,10 +394,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=4 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=1000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=12 prefetch_access=false prefetch_cache_check_push=true @@ -422,10 +438,12 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=8 block_size=64 +cpu_side_filter_ranges= hash_delay=1 latency=10000 lifo=false max_miss_count=0 +mem_side_filter_ranges= mshrs=92 prefetch_access=false prefetch_cache_check_push=true diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt index c54bfdce4..ba0757e28 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt @@ -1,70 +1,70 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 318912 # Number of bytes of host memory used -host_seconds 272.84 # Real time elapsed on the host -host_tick_rate 598087 # Simulator tick rate (ticks/s) +host_mem_usage 368532 # Number of bytes of host memory used +host_seconds 160.06 # Real time elapsed on the host +host_tick_rate 1018563 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000163 # Number of seconds simulated -sim_ticks 163182312 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 44955 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 22713.586650 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 22705.587882 # average ReadReq mshr miss latency +sim_ticks 163028791 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44866 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 23548.187676 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 22546.401324 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7621 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 847989044 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.830475 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37334 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 847690418 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.830475 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37334 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 517943783 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24357 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 24775.291654 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 24768.103842 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7557 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 878559334 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.831565 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37309 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 841183687 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.831565 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37309 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 470726871 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24129 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 28316.559940 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 27314.645519 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 956 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 579766600 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.960751 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23401 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 579598398 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.960751 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23401 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 315492846 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles_no_mshrs 2283.512556 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 864 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 658784767 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.964192 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23265 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 635475228 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.964192 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23265 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 289831424 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles_no_mshrs 2291.330126 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.411295 # Average number of references to valid blocks. -system.cpu0.l1c.blocked_no_mshrs 69290 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.411975 # Average number of references to valid blocks. +system.cpu0.l1c.blocked_no_mshrs 69625 # number of cycles access was blocked system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles_no_mshrs 158224585 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles_no_mshrs 159533860 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69312 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 23507.954952 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 23500.268642 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8577 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 1427755644 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.876255 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60735 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68995 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 25379.603477 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 24377.767937 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8421 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 1537344101 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.877948 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60574 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 1427288816 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.876255 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60735 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 1476658915 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.877948 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60574 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.overall_accesses 69312 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 23507.954952 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 23500.268642 # average overall mshr miss latency +system.cpu0.l1c.overall_accesses 68995 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 25379.603477 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 24377.767937 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8577 # number of overall hits -system.cpu0.l1c.overall_miss_latency 1427755644 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.876255 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60735 # number of overall misses +system.cpu0.l1c.overall_hits 8421 # number of overall hits +system.cpu0.l1c.overall_miss_latency 1537344101 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.877948 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60574 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 1427288816 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.876255 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60735 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 833436629 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 1476658915 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.877948 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60574 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 760558295 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -75,75 +75,75 @@ system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l1c.replacements 28052 # number of replacements -system.cpu0.l1c.sampled_refs 28403 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 27647 # number of replacements +system.cpu0.l1c.sampled_refs 27992 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 348.576200 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11682 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 346.649245 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11532 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 11146 # number of writebacks +system.cpu0.l1c.writebacks 10949 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99892 # number of read accesses completed -system.cpu0.num_writes 54159 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44788 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 22745.661074 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 22737.662205 # average ReadReq mshr miss latency +system.cpu0.num_reads 99664 # number of read accesses completed +system.cpu0.num_writes 53877 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44752 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 23635.008165 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 22633.168292 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7659 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 844523650 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.828994 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37129 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 844226660 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.828994 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37129 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 524670355 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24323 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 24767.283276 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 24760.081804 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7519 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 880002259 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.831985 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37233 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 842700755 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831985 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37233 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 466627047 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24332 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 28314.022230 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 27312.235893 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 950 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 578885712 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.960942 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23373 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 578717392 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.960942 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23373 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 319087206 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles_no_mshrs 2291.446711 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 940 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 662321608 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.961368 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23392 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 638887822 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961368 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23392 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 282776699 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles_no_mshrs 2295.997672 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.414757 # Average number of references to valid blocks. -system.cpu1.l1c.blocked_no_mshrs 69358 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.414619 # Average number of references to valid blocks. +system.cpu1.l1c.blocked_no_mshrs 69602 # number of cycles access was blocked system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles_no_mshrs 158930161 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles_no_mshrs 159806030 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 69111 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 23526.649731 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 23518.958910 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8609 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 1423409362 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.875432 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60502 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 69084 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 25440.393682 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 24438.574466 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8459 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 1542323867 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.877555 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60625 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 1422944052 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.875432 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60502 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 1481588577 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.877555 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60625 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.overall_accesses 69111 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 23526.649731 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 23518.958910 # average overall mshr miss latency +system.cpu1.l1c.overall_accesses 69084 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 25440.393682 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 24438.574466 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8609 # number of overall hits -system.cpu1.l1c.overall_miss_latency 1423409362 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.875432 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60502 # number of overall misses +system.cpu1.l1c.overall_hits 8459 # number of overall hits +system.cpu1.l1c.overall_miss_latency 1542323867 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.877555 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60625 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 1422944052 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.875432 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60502 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 843757561 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 1481588577 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.877555 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60625 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 749403746 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -154,75 +154,75 @@ system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l1c.replacements 27765 # number of replacements -system.cpu1.l1c.sampled_refs 28108 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27644 # number of replacements +system.cpu1.l1c.sampled_refs 28004 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 346.327274 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11658 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 346.128231 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11611 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10962 # number of writebacks +system.cpu1.l1c.writebacks 10912 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99692 # number of read accesses completed -system.cpu1.num_writes 53844 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 45045 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 22675.185062 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 22667.185702 # average ReadReq mshr miss latency +system.cpu1.num_reads 99711 # number of read accesses completed +system.cpu1.num_writes 53813 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44908 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 23697.485035 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 22695.564679 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7544 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 850342115 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832523 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37501 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 850042131 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832523 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37501 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 526690736 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 23975 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 24810.638326 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 24803.479873 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7655 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 882802410 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.829540 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37253 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 845477871 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.829540 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37253 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 465312435 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24367 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 28178.781659 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 27176.866738 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 946 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 571364190 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.960542 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23029 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 571199338 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.960542 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23029 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 314108208 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles_no_mshrs 2295.331392 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 977 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 659101703 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.959905 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23390 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 635666913 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.959905 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23390 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 291069881 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles_no_mshrs 2292.851688 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.417132 # Average number of references to valid blocks. -system.cpu2.l1c.blocked_no_mshrs 69383 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.415602 # Average number of references to valid blocks. +system.cpu2.l1c.blocked_no_mshrs 69421 # number of cycles access was blocked system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles_no_mshrs 159256978 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles_no_mshrs 159172057 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 69020 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 23487.631009 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 23479.951578 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8490 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 1421706305 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.876992 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60530 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 69275 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 25425.920766 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 24424.002506 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8632 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 1541904113 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.875395 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60643 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 1421241469 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.876992 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 1481144784 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.875395 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60643 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.overall_accesses 69020 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 23487.631009 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 23479.951578 # average overall mshr miss latency +system.cpu2.l1c.overall_accesses 69275 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 25425.920766 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 24424.002506 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8490 # number of overall hits -system.cpu2.l1c.overall_miss_latency 1421706305 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.876992 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60530 # number of overall misses +system.cpu2.l1c.overall_hits 8632 # number of overall hits +system.cpu2.l1c.overall_miss_latency 1541904113 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.875395 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60643 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 1421241469 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.876992 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60530 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 840798944 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 1481144784 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.875395 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60643 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 756382316 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -233,75 +233,75 @@ system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu2.l1c.replacements 27570 # number of replacements -system.cpu2.l1c.sampled_refs 27912 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27925 # number of replacements +system.cpu2.l1c.sampled_refs 28265 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 346.579014 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11643 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 348.298398 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11747 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10678 # number of writebacks +system.cpu2.l1c.writebacks 11043 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99982 # number of read accesses completed -system.cpu2.num_writes 53451 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 45026 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 22627.689991 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 22619.691218 # average ReadReq mshr miss latency +system.cpu2.num_reads 99614 # number of read accesses completed +system.cpu2.num_writes 54181 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44867 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 23550.912053 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 22549.071641 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7540 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 848221587 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.832541 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37486 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 847921745 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.832541 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37486 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 521058272 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24496 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 24499.134103 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 24491.950730 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7458 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 881016069 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.833775 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 37409 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 843538221 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833775 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 37409 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 469382996 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24208 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 28215.610982 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 27213.782676 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 932 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 577297596 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.961953 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23564 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 577128327 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961953 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23564 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 316556554 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles_no_mshrs 2277.071019 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 934 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 656690130 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.961418 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23274 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 633373578 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961418 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23274 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 292909328 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles_no_mshrs 2286.071306 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.408241 # Average number of references to valid blocks. -system.cpu3.l1c.blocked_no_mshrs 69700 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.400684 # Average number of references to valid blocks. +system.cpu3.l1c.blocked_no_mshrs 69658 # number of cycles access was blocked system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles_no_mshrs 158711850 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles_no_mshrs 159243155 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69522 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 23350.027568 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 23342.343522 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8472 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 1425519183 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.878139 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 61050 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 69075 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 25339.983175 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 24338.147405 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8392 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 1537706199 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.878509 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60683 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 1425050072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.878139 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 61050 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 1476911799 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.878509 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60683 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.overall_accesses 69522 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 23350.027568 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 23342.343522 # average overall mshr miss latency +system.cpu3.l1c.overall_accesses 69075 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 25339.983175 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 24338.147405 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8472 # number of overall hits -system.cpu3.l1c.overall_miss_latency 1425519183 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.878139 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 61050 # number of overall misses +system.cpu3.l1c.overall_hits 8392 # number of overall hits +system.cpu3.l1c.overall_miss_latency 1537706199 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.878509 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60683 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 1425050072 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.878139 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 61050 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 837614826 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 1476911799 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.878509 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60683 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 762292324 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -312,75 +312,75 @@ system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu3.l1c.replacements 28153 # number of replacements -system.cpu3.l1c.sampled_refs 28515 # Sample count of references to valid blocks. +system.cpu3.l1c.replacements 28024 # number of replacements +system.cpu3.l1c.sampled_refs 28379 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 348.493440 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11641 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 347.503603 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11371 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 11085 # number of writebacks +system.cpu3.l1c.writebacks 10929 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99697 # number of read accesses completed -system.cpu3.num_writes 54254 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44695 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 22595.724111 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 22587.725051 # average ReadReq mshr miss latency +system.cpu3.num_reads 99752 # number of read accesses completed +system.cpu3.num_writes 53813 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 45052 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 23676.379185 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 22674.538283 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7459 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 841374383 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.833113 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37236 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 841076530 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833113 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37236 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 521925270 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24320 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 24976.967619 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 24969.752460 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7503 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 889024362 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.833459 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37549 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 851406238 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833459 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37549 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 464076918 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 23965 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 28402.408395 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 27400.538398 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 942 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 583911549 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.961266 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23378 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 583742873 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.961266 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23378 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 314744590 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles_no_mshrs 2286.910395 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 904 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 654987940 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.962278 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23061 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 631883816 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.962278 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23061 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 290473799 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles_no_mshrs 2297.684951 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.401516 # Average number of references to valid blocks. -system.cpu4.l1c.blocked_no_mshrs 69382 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.405770 # Average number of references to valid blocks. +system.cpu4.l1c.blocked_no_mshrs 69513 # number of cycles access was blocked system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles_no_mshrs 158670417 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles_no_mshrs 159718974 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 69015 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 23514.137526 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 23506.440806 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8401 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 1425285932 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.878273 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60614 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 69017 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 25474.547137 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 24472.695166 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8407 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 1544012302 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.878189 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60610 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 1424819403 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.878273 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60614 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 1483290054 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.878189 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60610 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.overall_accesses 69015 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 23514.137526 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 23506.440806 # average overall mshr miss latency +system.cpu4.l1c.overall_accesses 69017 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 25474.547137 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 24472.695166 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8401 # number of overall hits -system.cpu4.l1c.overall_miss_latency 1425285932 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.878273 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60614 # number of overall misses +system.cpu4.l1c.overall_hits 8407 # number of overall hits +system.cpu4.l1c.overall_miss_latency 1544012302 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.878189 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60610 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 1424819403 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.878273 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60614 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 836669860 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 1483290054 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.878189 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60610 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 754550717 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -391,75 +391,75 @@ system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu4.l1c.replacements 28031 # number of replacements -system.cpu4.l1c.sampled_refs 28370 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 27817 # number of replacements +system.cpu4.l1c.sampled_refs 28144 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 347.544315 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11391 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 346.514694 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11420 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 11138 # number of writebacks +system.cpu4.l1c.writebacks 10757 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99375 # number of read accesses completed -system.cpu4.num_writes 53856 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44846 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 22795.859807 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 22787.860584 # average ReadReq mshr miss latency +system.cpu4.num_reads 99082 # number of read accesses completed +system.cpu4.num_writes 53389 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44738 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 23469.170166 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 22467.276917 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7526 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 850741488 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.832181 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37320 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 850442957 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832181 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37320 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 518680326 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24378 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 24686.676265 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 24679.493004 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7633 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 870823559 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.829384 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37105 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 833648310 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.829384 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37105 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 475305988 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 24369 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 28200.397532 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 27198.611178 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 936 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 578705065 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.961605 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23442 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 578536675 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961605 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23442 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 315478251 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles_no_mshrs 2288.071694 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 947 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 660509711 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.961139 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23422 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 637045871 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961139 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23422 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 288432414 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles_no_mshrs 2288.248839 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.412333 # Average number of references to valid blocks. -system.cpu5.l1c.blocked_no_mshrs 69434 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.414858 # Average number of references to valid blocks. +system.cpu5.l1c.blocked_no_mshrs 69575 # number of cycles access was blocked system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles_no_mshrs 158869970 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles_no_mshrs 159204913 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 69224 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 23525.337431 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 23517.653007 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8462 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 1429446553 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.877759 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60762 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 69107 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 25300.002809 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 24298.150924 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8580 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 1531333270 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.875845 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60527 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 1428979632 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.877759 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60762 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 1470694181 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.875845 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60527 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.overall_accesses 69224 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 23525.337431 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 23517.653007 # average overall mshr miss latency +system.cpu5.l1c.overall_accesses 69107 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 25300.002809 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 24298.150924 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8462 # number of overall hits -system.cpu5.l1c.overall_miss_latency 1429446553 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.877759 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60762 # number of overall misses +system.cpu5.l1c.overall_hits 8580 # number of overall hits +system.cpu5.l1c.overall_miss_latency 1531333270 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.875845 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60527 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 1428979632 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.877759 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60762 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 834158577 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 1470694181 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.875845 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60527 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 763738402 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -470,75 +470,75 @@ system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu5.l1c.replacements 27718 # number of replacements -system.cpu5.l1c.sampled_refs 28055 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 27804 # number of replacements +system.cpu5.l1c.sampled_refs 28147 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 345.552063 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11568 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 347.082479 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11677 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10910 # number of writebacks +system.cpu5.l1c.writebacks 11050 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99402 # number of read accesses completed -system.cpu5.num_writes 54123 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 45284 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 22614.833240 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 22606.834542 # average ReadReq mshr miss latency +system.cpu5.num_reads 99598 # number of read accesses completed +system.cpu5.num_writes 53839 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44535 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 23610.393004 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 22608.500040 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7625 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 851652005 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.831618 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37659 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 851350782 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831618 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37659 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 513879090 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24033 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 25148.091805 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 25140.890430 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7370 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 877480256 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.834512 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 37165 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 840244904 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834512 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 37165 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 465545805 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24347 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 28528.225110 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 27526.396266 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 897 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 581826252 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.962676 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23136 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 581659641 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962676 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23136 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 312525316 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles_no_mshrs 2288.777328 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 994 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 666219641 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.959174 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23353 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 642823932 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.959174 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23353 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 284792998 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles_no_mshrs 2301.549644 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.407927 # Average number of references to valid blocks. -system.cpu6.l1c.blocked_no_mshrs 69380 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.409026 # Average number of references to valid blocks. +system.cpu6.l1c.blocked_no_mshrs 69474 # number of cycles access was blocked system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles_no_mshrs 158795371 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles_no_mshrs 159897860 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 69317 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 23578.884069 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 23571.188798 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8522 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 1433478257 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.877058 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60795 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68882 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 25508.111587 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 24506.243366 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8364 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 1543699897 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.878575 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60518 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 1433010423 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.877058 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60795 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 1483068836 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.878575 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60518 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.overall_accesses 69317 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 23578.884069 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 23571.188798 # average overall mshr miss latency +system.cpu6.l1c.overall_accesses 68882 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 25508.111587 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 24506.243366 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8522 # number of overall hits -system.cpu6.l1c.overall_miss_latency 1433478257 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.877058 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60795 # number of overall misses +system.cpu6.l1c.overall_hits 8364 # number of overall hits +system.cpu6.l1c.overall_miss_latency 1543699897 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.878575 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60518 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 1433010423 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.877058 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60795 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 826404406 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 1483068836 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.878575 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60518 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 750338803 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -549,75 +549,75 @@ system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu6.l1c.replacements 27931 # number of replacements -system.cpu6.l1c.sampled_refs 28282 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 27670 # number of replacements +system.cpu6.l1c.sampled_refs 28030 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 346.778818 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11537 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 347.050394 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11465 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 10819 # number of writebacks +system.cpu6.l1c.writebacks 10922 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53600 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44617 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 22791.302160 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 22783.302456 # average ReadReq mshr miss latency +system.cpu6.num_reads 98586 # number of read accesses completed +system.cpu6.num_writes 53530 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 45060 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 23572.973322 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 22571.079447 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7491 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 846149884 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.832104 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37126 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 845852887 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.832104 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37126 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 523016698 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24432 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 24654.748978 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 24647.585464 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7689 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 880945586 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.829361 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37371 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 843503810 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.829361 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37371 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 464745135 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24261 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 28282.937385 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 27281.151106 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 960 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 578696268 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.960707 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23472 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 578528126 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.960707 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23472 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 310262407 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles_no_mshrs 2294.299163 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 880 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 661283359 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.963728 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23381 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 637860594 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.963728 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23381 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 291455406 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles_no_mshrs 2290.612942 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.417293 # Average number of references to valid blocks. -system.cpu7.l1c.blocked_no_mshrs 69407 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.415259 # Average number of references to valid blocks. +system.cpu7.l1c.blocked_no_mshrs 69540 # number of cycles access was blocked system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles_no_mshrs 159240422 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles_no_mshrs 159289224 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 69049 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 23513.088749 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 23505.412934 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8451 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 1424846152 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.877609 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60598 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 69321 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 25385.648950 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 24383.796484 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8569 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 1542228945 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.876387 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60752 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 1424381013 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.877609 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60598 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 1481364404 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.876387 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60752 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.overall_accesses 69049 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 23513.088749 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 23505.412934 # average overall mshr miss latency +system.cpu7.l1c.overall_accesses 69321 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 25385.648950 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 24383.796484 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8451 # number of overall hits -system.cpu7.l1c.overall_miss_latency 1424846152 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.877609 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60598 # number of overall misses +system.cpu7.l1c.overall_hits 8569 # number of overall hits +system.cpu7.l1c.overall_miss_latency 1542228945 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.876387 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60752 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 1424381013 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.877609 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60598 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 833279105 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 1481364404 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.876387 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60752 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 756200541 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -628,91 +628,91 @@ system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu7.l1c.replacements 27613 # number of replacements -system.cpu7.l1c.sampled_refs 27942 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 27776 # number of replacements +system.cpu7.l1c.sampled_refs 28127 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 345.414592 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11660 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 346.455947 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11680 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10955 # number of writebacks +system.cpu7.l1c.writebacks 10920 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98933 # number of read accesses completed -system.cpu7.num_writes 53679 # number of write accesses completed -system.l2c.ReadExReq_accesses 74732 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency 10058.723893 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 10012.709549 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 751708554 # number of ReadExReq miss cycles +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 53888 # number of write accesses completed +system.l2c.ReadExReq_accesses 74532 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency 20118.794759 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 10011.874108 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 1499494011 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses 74732 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 486 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 748269810 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_misses 74532 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 478 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 746205001 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74732 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses 138119 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency 10093.112454 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 10012.902949 # average ReadReq mshr miss latency +system.l2c.ReadExReq_mshr_misses 74532 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses 137656 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency 20204.255734 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 10011.528670 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits 62746 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 760748165 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate 0.545711 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses 75373 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 858 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 754702534 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate 0.545711 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 75373 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 792432163 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses 18312 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency 5090.815258 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 10012.622433 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 93223009 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits 62664 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 1515157546 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate 0.544778 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses 74992 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 876 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 750784558 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate 0.544778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 74992 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 792812009 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses 18194 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency 10193.188359 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 10011.231065 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 185454869 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses 18312 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 25 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 183351142 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_misses 18194 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 33 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 182144338 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18312 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 18194 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 430029394 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses 86893 # number of Writeback accesses(hits+misses) +system.l2c.WriteReq_mshr_uncacheable_latency 429976462 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses 86637 # number of Writeback accesses(hits+misses) system.l2c.Writeback_miss_rate 1 # miss rate for Writeback accesses -system.l2c.Writeback_misses 86893 # number of Writeback misses +system.l2c.Writeback_misses 86637 # number of Writeback misses system.l2c.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses -system.l2c.Writeback_mshr_misses 86893 # number of Writeback MSHR misses -system.l2c.avg_blocked_cycles_no_mshrs 3278 # average number of cycles each access was blocked +system.l2c.Writeback_mshr_misses 86637 # number of Writeback MSHR misses +system.l2c.avg_blocked_cycles_no_mshrs 2919.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.l2c.avg_refs 3.318198 # Average number of references to valid blocks. -system.l2c.blocked_no_mshrs 3 # number of cycles access was blocked +system.l2c.avg_refs 3.347484 # Average number of references to valid blocks. +system.l2c.blocked_no_mshrs 6 # number of cycles access was blocked system.l2c.blocked_no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles_no_mshrs 9834 # number of cycles access was blocked +system.l2c.blocked_cycles_no_mshrs 17517 # number of cycles access was blocked system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses 212851 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency 10075.991599 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 10012.806662 # average overall mshr miss latency -system.l2c.demand_hits 62746 # number of demand (read+write) hits -system.l2c.demand_miss_latency 1512456719 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate 0.705212 # miss rate for demand accesses -system.l2c.demand_misses 150105 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1344 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 1502972344 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate 0.705212 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 150105 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses 212188 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency 20161.656704 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 10011.700857 # average overall mshr miss latency +system.l2c.demand_hits 62664 # number of demand (read+write) hits +system.l2c.demand_miss_latency 3014651557 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate 0.704677 # miss rate for demand accesses +system.l2c.demand_misses 149524 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1354 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 1496989559 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate 0.704677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 149524 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.overall_accesses 212851 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency 10075.991599 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 10012.806662 # average overall mshr miss latency +system.l2c.overall_accesses 212188 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency 20161.656704 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 10011.700857 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits 62746 # number of overall hits -system.l2c.overall_miss_latency 1512456719 # number of overall miss cycles -system.l2c.overall_miss_rate 0.705212 # miss rate for overall accesses -system.l2c.overall_misses 150105 # number of overall misses -system.l2c.overall_mshr_hits 1344 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 1502972344 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate 0.705212 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 150105 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1222461557 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits 62664 # number of overall hits +system.l2c.overall_miss_latency 3014651557 # number of overall miss cycles +system.l2c.overall_miss_rate 0.704677 # miss rate for overall accesses +system.l2c.overall_misses 149524 # number of overall misses +system.l2c.overall_mshr_hits 1354 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 1496989559 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate 0.704677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 149524 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1222788471 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr @@ -723,11 +723,11 @@ system.l2c.prefetcher.num_hwpf_issued 0 # nu system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.l2c.replacements 31000 # number of replacements -system.l2c.sampled_refs 31427 # Sample count of references to valid blocks. +system.l2c.replacements 30644 # number of replacements +system.l2c.sampled_refs 31095 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 461.978673 # Cycle average of tags in use -system.l2c.total_refs 104281 # Total number of references to valid blocks. +system.l2c.tagsinuse 460.797785 # Cycle average of tags in use +system.l2c.total_refs 104090 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.writebacks 0 # number of writebacks diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr index 87bef1427..9486d3e24 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr @@ -1,74 +1,74 @@ warn: Entering event queue @ 0. Starting simulation... -system.cpu7: completed 10000 read accesses @15607088 -system.cpu1: completed 10000 read accesses @15686239 -system.cpu5: completed 10000 read accesses @15771479 -system.cpu4: completed 10000 read accesses @15772513 -system.cpu0: completed 10000 read accesses @15778178 -system.cpu6: completed 10000 read accesses @15791633 -system.cpu2: completed 10000 read accesses @15841990 -system.cpu3: completed 10000 read accesses @15878600 -system.cpu2: completed 20000 read accesses @31878727 -system.cpu7: completed 20000 read accesses @32026154 -system.cpu6: completed 20000 read accesses @32057190 -system.cpu1: completed 20000 read accesses @32240417 -system.cpu0: completed 20000 read accesses @32270672 -system.cpu3: completed 20000 read accesses @32335938 -system.cpu5: completed 20000 read accesses @32480722 -system.cpu4: completed 20000 read accesses @32490454 -system.cpu2: completed 30000 read accesses @48060100 -system.cpu6: completed 30000 read accesses @48167196 -system.cpu4: completed 30000 read accesses @48520588 -system.cpu7: completed 30000 read accesses @48646309 -system.cpu0: completed 30000 read accesses @48740616 -system.cpu1: completed 30000 read accesses @48766857 -system.cpu3: completed 30000 read accesses @48959010 -system.cpu5: completed 30000 read accesses @49028132 -system.cpu6: completed 40000 read accesses @64421948 -system.cpu4: completed 40000 read accesses @64637670 -system.cpu2: completed 40000 read accesses @64868400 -system.cpu1: completed 40000 read accesses @64925788 -system.cpu0: completed 40000 read accesses @64956331 -system.cpu3: completed 40000 read accesses @65406565 -system.cpu5: completed 40000 read accesses @65517578 -system.cpu7: completed 40000 read accesses @65556693 -system.cpu6: completed 50000 read accesses @80917227 -system.cpu2: completed 50000 read accesses @80917444 -system.cpu4: completed 50000 read accesses @81159816 -system.cpu1: completed 50000 read accesses @81373401 -system.cpu3: completed 50000 read accesses @81540449 -system.cpu0: completed 50000 read accesses @81577912 -system.cpu5: completed 50000 read accesses @81975441 -system.cpu7: completed 50000 read accesses @82285501 -system.cpu2: completed 60000 read accesses @96985412 -system.cpu4: completed 60000 read accesses @97174738 -system.cpu6: completed 60000 read accesses @97530786 -system.cpu0: completed 60000 read accesses @97671589 -system.cpu3: completed 60000 read accesses @97821937 -system.cpu1: completed 60000 read accesses @97822818 -system.cpu5: completed 60000 read accesses @98044596 -system.cpu7: completed 60000 read accesses @98812006 -system.cpu2: completed 70000 read accesses @113400661 -system.cpu4: completed 70000 read accesses @113949415 -system.cpu1: completed 70000 read accesses @114120869 -system.cpu3: completed 70000 read accesses @114207385 -system.cpu0: completed 70000 read accesses @114307850 -system.cpu6: completed 70000 read accesses @114393410 -system.cpu5: completed 70000 read accesses @114714609 -system.cpu7: completed 70000 read accesses @115286783 -system.cpu2: completed 80000 read accesses @130149084 -system.cpu0: completed 80000 read accesses @130494872 -system.cpu4: completed 80000 read accesses @130604588 -system.cpu6: completed 80000 read accesses @130741327 -system.cpu1: completed 80000 read accesses @130791488 -system.cpu3: completed 80000 read accesses @130805400 -system.cpu5: completed 80000 read accesses @130975948 -system.cpu7: completed 80000 read accesses @131555733 -system.cpu2: completed 90000 read accesses @146468442 -system.cpu6: completed 90000 read accesses @146616353 -system.cpu1: completed 90000 read accesses @146926939 -system.cpu3: completed 90000 read accesses @147059543 -system.cpu0: completed 90000 read accesses @147067458 -system.cpu5: completed 90000 read accesses @147440946 -system.cpu4: completed 90000 read accesses @147560717 -system.cpu7: completed 90000 read accesses @148115904 -system.cpu6: completed 100000 read accesses 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accesses @81653617 +system.cpu4: completed 50000 read accesses @81787398 +system.cpu1: completed 50000 read accesses @81868780 +system.cpu6: completed 50000 read accesses @82227342 +system.cpu7: completed 60000 read accesses @97291732 +system.cpu5: completed 60000 read accesses @97361345 +system.cpu2: completed 60000 read accesses @97621191 +system.cpu3: completed 60000 read accesses @97673986 +system.cpu1: completed 60000 read accesses @97950396 +system.cpu0: completed 60000 read accesses @98086520 +system.cpu4: completed 60000 read accesses @98139060 +system.cpu6: completed 60000 read accesses @98866267 +system.cpu7: completed 70000 read accesses @113775234 +system.cpu5: completed 70000 read accesses @114027734 +system.cpu3: completed 70000 read accesses @114107654 +system.cpu2: completed 70000 read accesses @114287447 +system.cpu1: completed 70000 read accesses @114429712 +system.cpu0: completed 70000 read accesses @114626666 +system.cpu4: completed 70000 read accesses @115046863 +system.cpu6: completed 70000 read accesses @115625699 +system.cpu7: completed 80000 read accesses @130041792 +system.cpu5: completed 80000 read accesses @130054396 +system.cpu1: completed 80000 read accesses @130640538 +system.cpu3: completed 80000 read accesses @130746631 +system.cpu0: completed 80000 read accesses @130757460 +system.cpu2: completed 80000 read accesses @130848004 +system.cpu4: completed 80000 read accesses @131798404 +system.cpu6: completed 80000 read accesses @132427801 +system.cpu7: completed 90000 read accesses @146399168 +system.cpu3: completed 90000 read accesses @146528404 +system.cpu0: completed 90000 read accesses @146893614 +system.cpu5: completed 90000 read accesses @147004410 +system.cpu1: completed 90000 read accesses @147082543 +system.cpu2: completed 90000 read accesses @147344874 +system.cpu4: completed 90000 read accesses @148040578 +system.cpu6: completed 90000 read accesses @149090244 +system.cpu7: completed 100000 read accesses @163028791 diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout index 29891e1e8..bb2428fbe 100644 --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 3 2007 03:56:47 -M5 started Fri Aug 3 04:17:16 2007 -M5 executing on zizzer.eecs.umich.edu +M5 compiled Aug 12 2007 00:26:55 +M5 started Sun Aug 12 12:13:31 2007 +M5 executing on zeep command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second -Exiting @ tick 163182312 because maximum number of loads reached +Exiting @ tick 163028791 because maximum number of loads reached |