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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-05-11 10:38:46 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2009-05-11 10:38:46 -0700 |
| commit | b174ec065e2b9f8ffa68c350b2563819eef5e9b1 (patch) | |
| tree | 247eaf664b887559a1575d0733daa2179741bcd2 /tests/quick/50.memtest | |
| parent | 6df61e1f2409e336dc4ae68eaeae7d0638e65a9d (diff) | |
| download | gem5-b174ec065e2b9f8ffa68c350b2563819eef5e9b1.tar.xz | |
ruby: Initial references for ruby regressions
Diffstat (limited to 'tests/quick/50.memtest')
5 files changed, 1614 insertions, 0 deletions
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini new file mode 100644 index 000000000..2c57f204c --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini @@ -0,0 +1,169 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem membus physmem +mem_mode=timing +physmem=system.physmem + +[system.cpu0] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[0] +test=system.membus.port[0] + +[system.cpu1] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[1] +test=system.membus.port[1] + +[system.cpu2] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[2] +test=system.membus.port[2] + +[system.cpu3] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[3] +test=system.membus.port[3] + +[system.cpu4] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[4] +test=system.membus.port[4] + +[system.cpu5] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[5] +test=system.membus.port[5] + +[system.cpu6] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[6] +test=system.membus.port[6] + +[system.cpu7] +type=MemTest +atomic=false +max_loads=100000 +memory_size=65536 +percent_dest_unaligned=50 +percent_functional=50 +percent_reads=65 +percent_source_unaligned=50 +percent_uncacheable=10 +progress_interval=10000 +trace_addr=0 +functional=system.funcmem.port[7] +test=system.membus.port[7] + +[system.funcmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=2 +header_cycles=1 +responder_set=false +width=16 +port=system.cpu0.test system.cpu1.test system.cpu2.test system.cpu3.test system.cpu4.test system.cpu5.test system.cpu6.test system.cpu7.test system.physmem.port[0] + +[system.physmem] +type=RubyMemory +clock=1 +config_file= +config_options= +debug=false +debug_file= +file= +latency=30000 +latency_var=0 +null=false +num_cpus=8 +phase=0 +range=0:134217727 +stats_file=ruby.stats +zero=false +port=system.membus.port[8] + diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats new file mode 100644 index 000000000..a3c4dfb4e --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -0,0 +1,1315 @@ + +================ Begin RubySystem Configuration Print ================ + +Ruby Configuration +------------------ +protocol: MOSI_SMP_bcast +compiled_at: 22:51:11, May 4 2009 +RUBY_DEBUG: false +hostname: piton +g_RANDOM_SEED: 1 +g_DEADLOCK_THRESHOLD: 500000 +RANDOMIZATION: false +g_SYNTHETIC_DRIVER: false +g_DETERMINISTIC_DRIVER: false +g_FILTERING_ENABLED: false +g_DISTRIBUTED_PERSISTENT_ENABLED: true +g_DYNAMIC_TIMEOUT_ENABLED: true +g_RETRY_THRESHOLD: 1 +g_FIXED_TIMEOUT_LATENCY: 300 +g_trace_warmup_length: 1000000 +g_bash_bandwidth_adaptive_threshold: 0.75 +g_tester_length: 0 +g_synthetic_locks: 2048 +g_deterministic_addrs: 1 +g_SpecifiedGenerator: DetermInvGenerator +g_callback_counter: 0 +g_NUM_COMPLETIONS_BEFORE_PASS: 0 +g_NUM_SMT_THREADS: 1 +g_think_time: 5 +g_hold_time: 5 +g_wait_time: 5 +PROTOCOL_DEBUG_TRACE: true +DEBUG_FILTER_STRING: none +DEBUG_VERBOSITY_STRING: none +DEBUG_START_TIME: 0 +DEBUG_OUTPUT_FILENAME: none +SIMICS_RUBY_MULTIPLIER: 4 +OPAL_RUBY_MULTIPLIER: 1 +TRANSACTION_TRACE_ENABLED: false +USER_MODE_DATA_ONLY: false +PROFILE_HOT_LINES: false +PROFILE_ALL_INSTRUCTIONS: false +PRINT_INSTRUCTION_TRACE: false +g_DEBUG_CYCLE: 0 +BLOCK_STC: false +PERFECT_MEMORY_SYSTEM: false +PERFECT_MEMORY_SYSTEM_LATENCY: 0 +DATA_BLOCK: false +REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false +L1_CACHE_ASSOC: 4 +L1_CACHE_NUM_SETS_BITS: 8 +L2_CACHE_ASSOC: 4 +L2_CACHE_NUM_SETS_BITS: 16 +g_MEMORY_SIZE_BYTES: 4294967296 +g_DATA_BLOCK_BYTES: 64 +g_PAGE_SIZE_BYTES: 4096 +g_REPLACEMENT_POLICY: PSEDUO_LRU +g_NUM_PROCESSORS: 8 +g_NUM_L2_BANKS: 8 +g_NUM_MEMORIES: 8 +g_PROCS_PER_CHIP: 1 +g_NUM_CHIPS: 8 +g_NUM_CHIP_BITS: 3 +g_MEMORY_SIZE_BITS: 32 +g_DATA_BLOCK_BITS: 6 +g_PAGE_SIZE_BITS: 12 +g_NUM_PROCESSORS_BITS: 3 +g_PROCS_PER_CHIP_BITS: 0 +g_NUM_L2_BANKS_BITS: 3 +g_NUM_L2_BANKS_PER_CHIP_BITS: 0 +g_NUM_L2_BANKS_PER_CHIP: 1 +g_NUM_MEMORIES_BITS: 3 +g_NUM_MEMORIES_PER_CHIP: 1 +g_MEMORY_MODULE_BITS: 23 +g_MEMORY_MODULE_BLOCKS: 8388608 +MAP_L2BANKS_TO_LOWEST_BITS: false +DIRECTORY_CACHE_LATENCY: 6 +NULL_LATENCY: 1 +ISSUE_LATENCY: 2 +CACHE_RESPONSE_LATENCY: 12 +L2_RESPONSE_LATENCY: 6 +L2_TAG_LATENCY: 6 +L1_RESPONSE_LATENCY: 3 +MEMORY_RESPONSE_LATENCY_MINUS_2: 158 +DIRECTORY_LATENCY: 80 +NETWORK_LINK_LATENCY: 1 +COPY_HEAD_LATENCY: 4 +ON_CHIP_LINK_LATENCY: 1 +RECYCLE_LATENCY: 10 +L2_RECYCLE_LATENCY: 5 +TIMER_LATENCY: 10000 +TBE_RESPONSE_LATENCY: 1 +PERIODIC_TIMER_WAKEUPS: true +PROFILE_EXCEPTIONS: false +PROFILE_XACT: true +PROFILE_NONXACT: false +XACT_DEBUG: true +XACT_DEBUG_LEVEL: 1 +XACT_MEMORY: false +XACT_ENABLE_TOURMALINE: false +XACT_NUM_CURRENT: 0 +XACT_LAST_UPDATE: 0 +XACT_ISOLATION_CHECK: false +PERFECT_FILTER: true +READ_WRITE_FILTER: Perfect_ +PERFECT_VIRTUAL_FILTER: true +VIRTUAL_READ_WRITE_FILTER: Perfect_ +PERFECT_SUMMARY_FILTER: true +SUMMARY_READ_WRITE_FILTER: Perfect_ +XACT_EAGER_CD: true +XACT_LAZY_VM: false +XACT_CONFLICT_RES: BASE +XACT_VISUALIZER: false +XACT_COMMIT_TOKEN_LATENCY: 0 +XACT_NO_BACKOFF: false +XACT_LOG_BUFFER_SIZE: 0 +XACT_STORE_PREDICTOR_HISTORY: 256 +XACT_STORE_PREDICTOR_ENTRIES: 256 +XACT_STORE_PREDICTOR_THRESHOLD: 4 +XACT_FIRST_ACCESS_COST: 0 +XACT_FIRST_PAGE_ACCESS_COST: 0 +ENABLE_MAGIC_WAITING: false +ENABLE_WATCHPOINT: false +XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false +ATMTP_ENABLED: false +ATMTP_ABORT_ON_NON_XACT_INST: false +ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false +ATMTP_XACT_MAX_STORES: 32 +ATMTP_DEBUG_LEVEL: 0 +L1_REQUEST_LATENCY: 2 +L2_REQUEST_LATENCY: 4 +SINGLE_ACCESS_L2_BANKS: true +SEQUENCER_TO_CONTROLLER_LATENCY: 4 +L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 +L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 +DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32 +g_SEQUENCER_OUTSTANDING_REQUESTS: 16 +NUMBER_OF_TBES: 128 +NUMBER_OF_L1_TBES: 32 +NUMBER_OF_L2_TBES: 32 +FINITE_BUFFERING: false +FINITE_BUFFER_SIZE: 3 +PROCESSOR_BUFFER_SIZE: 10 +PROTOCOL_BUFFER_SIZE: 32 +TSO: false +g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH +g_CACHE_DESIGN: NUCA +g_endpoint_bandwidth: 10000 +g_adaptive_routing: true +NUMBER_OF_VIRTUAL_NETWORKS: 4 +FAN_OUT_DEGREE: 4 +g_PRINT_TOPOLOGY: true +XACT_LENGTH: 0 +XACT_SIZE: 0 +ABORT_RETRY_TIME: 0 +g_GARNET_NETWORK: false +g_DETAIL_NETWORK: false +g_NETWORK_TESTING: false +g_FLIT_SIZE: 16 +g_NUM_PIPE_STAGES: 4 +g_VCS_PER_CLASS: 4 +g_BUFFER_SIZE: 4 +MEM_BUS_CYCLE_MULTIPLIER: 10 +BANKS_PER_RANK: 8 +RANKS_PER_DIMM: 2 +DIMMS_PER_CHANNEL: 2 +BANK_BIT_0: 8 +RANK_BIT_0: 11 +DIMM_BIT_0: 12 +BANK_QUEUE_SIZE: 12 +BANK_BUSY_TIME: 11 +RANK_RANK_DELAY: 1 +READ_WRITE_DELAY: 2 +BASIC_BUS_BUSY_TIME: 2 +MEM_CTL_LATENCY: 12 +REFRESH_PERIOD: 1560 +TFAW: 0 +MEM_RANDOM_ARBITRATE: 0 +MEM_FIXED_DELAY: 0 + +Chip Config +----------- +Total_Chips: 8 + +L1Cache_TBEs numberPerChip: 1 +TBEs_per_TBETable: 128 + +L1Cache_L1IcacheMemory numberPerChip: 1 +Cache config: L1Cache_0_L1I + cache_associativity: 4 + num_cache_sets_bits: 8 + num_cache_sets: 256 + cache_set_size_bytes: 16384 + cache_set_size_Kbytes: 16 + cache_set_size_Mbytes: 0.015625 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 + +L1Cache_L1DcacheMemory numberPerChip: 1 +Cache config: L1Cache_0_L1D + cache_associativity: 4 + num_cache_sets_bits: 8 + num_cache_sets: 256 + cache_set_size_bytes: 16384 + cache_set_size_Kbytes: 16 + cache_set_size_Mbytes: 0.015625 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 + +L1Cache_L2cacheMemory numberPerChip: 1 +Cache config: L1Cache_0_L2 + cache_associativity: 4 + num_cache_sets_bits: 16 + num_cache_sets: 65536 + cache_set_size_bytes: 4194304 + cache_set_size_Kbytes: 4096 + cache_set_size_Mbytes: 4 + cache_size_bytes: 16777216 + cache_size_Kbytes: 16384 + cache_size_Mbytes: 16 + +L1Cache_mandatoryQueue numberPerChip: 1 + +L1Cache_sequencer numberPerChip: 1 +sequencer: Sequencer - SC + max_outstanding_requests: 16 + +L1Cache_storeBuffer numberPerChip: 1 +Store buffer entries: 128 (Only valid if TSO is enabled) + +Directory_directory numberPerChip: 1 +Memory config: + memory_bits: 32 + memory_size_bytes: 4294967296 + memory_size_Kbytes: 4.1943e+06 + memory_size_Mbytes: 4096 + memory_size_Gbytes: 4 + module_bits: 23 + module_size_lines: 8388608 + module_size_bytes: 536870912 + module_size_Kbytes: 524288 + module_size_Mbytes: 512 + + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: HIERARCHICAL_SWITCH + +virtual_net_0: active, ordered +virtual_net_1: active, unordered +virtual_net_2: inactive +virtual_net_3: inactive + +--- Begin Topology Print --- + +Topology print ONLY indicates the _NETWORK_ latency between two machines +It does NOT include the latency within the machines + +L1Cache-0 Network Latencies + L1Cache-0 -> L1Cache-1 net_lat: 9 + L1Cache-0 -> L1Cache-2 net_lat: 9 + L1Cache-0 -> L1Cache-3 net_lat: 9 + L1Cache-0 -> L1Cache-4 net_lat: 9 + L1Cache-0 -> L1Cache-5 net_lat: 9 + L1Cache-0 -> L1Cache-6 net_lat: 9 + L1Cache-0 -> L1Cache-7 net_lat: 9 + L1Cache-0 -> Directory-0 net_lat: 9 + L1Cache-0 -> Directory-1 net_lat: 9 + L1Cache-0 -> Directory-2 net_lat: 9 + L1Cache-0 -> Directory-3 net_lat: 9 + L1Cache-0 -> Directory-4 net_lat: 9 + L1Cache-0 -> Directory-5 net_lat: 9 + L1Cache-0 -> Directory-6 net_lat: 9 + L1Cache-0 -> Directory-7 net_lat: 9 + +L1Cache-1 Network Latencies + L1Cache-1 -> L1Cache-0 net_lat: 9 + L1Cache-1 -> L1Cache-2 net_lat: 9 + L1Cache-1 -> L1Cache-3 net_lat: 9 + L1Cache-1 -> L1Cache-4 net_lat: 9 + L1Cache-1 -> L1Cache-5 net_lat: 9 + L1Cache-1 -> L1Cache-6 net_lat: 9 + L1Cache-1 -> L1Cache-7 net_lat: 9 + L1Cache-1 -> Directory-0 net_lat: 9 + L1Cache-1 -> Directory-1 net_lat: 9 + L1Cache-1 -> Directory-2 net_lat: 9 + L1Cache-1 -> Directory-3 net_lat: 9 + L1Cache-1 -> Directory-4 net_lat: 9 + L1Cache-1 -> Directory-5 net_lat: 9 + L1Cache-1 -> Directory-6 net_lat: 9 + L1Cache-1 -> Directory-7 net_lat: 9 + +L1Cache-2 Network Latencies + L1Cache-2 -> L1Cache-0 net_lat: 9 + L1Cache-2 -> L1Cache-1 net_lat: 9 + L1Cache-2 -> L1Cache-3 net_lat: 9 + L1Cache-2 -> L1Cache-4 net_lat: 9 + L1Cache-2 -> L1Cache-5 net_lat: 9 + L1Cache-2 -> L1Cache-6 net_lat: 9 + L1Cache-2 -> L1Cache-7 net_lat: 9 + L1Cache-2 -> Directory-0 net_lat: 9 + L1Cache-2 -> Directory-1 net_lat: 9 + L1Cache-2 -> Directory-2 net_lat: 9 + L1Cache-2 -> Directory-3 net_lat: 9 + L1Cache-2 -> Directory-4 net_lat: 9 + L1Cache-2 -> Directory-5 net_lat: 9 + L1Cache-2 -> Directory-6 net_lat: 9 + L1Cache-2 -> Directory-7 net_lat: 9 + +L1Cache-3 Network Latencies + L1Cache-3 -> L1Cache-0 net_lat: 9 + L1Cache-3 -> L1Cache-1 net_lat: 9 + L1Cache-3 -> L1Cache-2 net_lat: 9 + L1Cache-3 -> L1Cache-4 net_lat: 9 + L1Cache-3 -> L1Cache-5 net_lat: 9 + L1Cache-3 -> L1Cache-6 net_lat: 9 + L1Cache-3 -> L1Cache-7 net_lat: 9 + L1Cache-3 -> Directory-0 net_lat: 9 + L1Cache-3 -> Directory-1 net_lat: 9 + L1Cache-3 -> Directory-2 net_lat: 9 + L1Cache-3 -> Directory-3 net_lat: 9 + L1Cache-3 -> Directory-4 net_lat: 9 + L1Cache-3 -> Directory-5 net_lat: 9 + L1Cache-3 -> Directory-6 net_lat: 9 + L1Cache-3 -> Directory-7 net_lat: 9 + +L1Cache-4 Network Latencies + L1Cache-4 -> L1Cache-0 net_lat: 9 + L1Cache-4 -> L1Cache-1 net_lat: 9 + L1Cache-4 -> L1Cache-2 net_lat: 9 + L1Cache-4 -> L1Cache-3 net_lat: 9 + L1Cache-4 -> L1Cache-5 net_lat: 9 + L1Cache-4 -> L1Cache-6 net_lat: 9 + L1Cache-4 -> L1Cache-7 net_lat: 9 + L1Cache-4 -> Directory-0 net_lat: 9 + L1Cache-4 -> Directory-1 net_lat: 9 + L1Cache-4 -> Directory-2 net_lat: 9 + L1Cache-4 -> Directory-3 net_lat: 9 + L1Cache-4 -> Directory-4 net_lat: 9 + L1Cache-4 -> Directory-5 net_lat: 9 + L1Cache-4 -> Directory-6 net_lat: 9 + L1Cache-4 -> Directory-7 net_lat: 9 + +L1Cache-5 Network Latencies + L1Cache-5 -> L1Cache-0 net_lat: 9 + L1Cache-5 -> L1Cache-1 net_lat: 9 + L1Cache-5 -> L1Cache-2 net_lat: 9 + L1Cache-5 -> L1Cache-3 net_lat: 9 + L1Cache-5 -> L1Cache-4 net_lat: 9 + L1Cache-5 -> L1Cache-6 net_lat: 9 + L1Cache-5 -> L1Cache-7 net_lat: 9 + L1Cache-5 -> Directory-0 net_lat: 9 + L1Cache-5 -> Directory-1 net_lat: 9 + L1Cache-5 -> Directory-2 net_lat: 9 + L1Cache-5 -> Directory-3 net_lat: 9 + L1Cache-5 -> Directory-4 net_lat: 9 + L1Cache-5 -> Directory-5 net_lat: 9 + L1Cache-5 -> Directory-6 net_lat: 9 + L1Cache-5 -> Directory-7 net_lat: 9 + +L1Cache-6 Network Latencies + L1Cache-6 -> L1Cache-0 net_lat: 9 + L1Cache-6 -> L1Cache-1 net_lat: 9 + L1Cache-6 -> L1Cache-2 net_lat: 9 + L1Cache-6 -> L1Cache-3 net_lat: 9 + L1Cache-6 -> L1Cache-4 net_lat: 9 + L1Cache-6 -> L1Cache-5 net_lat: 9 + L1Cache-6 -> L1Cache-7 net_lat: 9 + L1Cache-6 -> Directory-0 net_lat: 9 + L1Cache-6 -> Directory-1 net_lat: 9 + L1Cache-6 -> Directory-2 net_lat: 9 + L1Cache-6 -> Directory-3 net_lat: 9 + L1Cache-6 -> Directory-4 net_lat: 9 + L1Cache-6 -> Directory-5 net_lat: 9 + L1Cache-6 -> Directory-6 net_lat: 9 + L1Cache-6 -> Directory-7 net_lat: 9 + +L1Cache-7 Network Latencies + L1Cache-7 -> L1Cache-0 net_lat: 9 + L1Cache-7 -> L1Cache-1 net_lat: 9 + L1Cache-7 -> L1Cache-2 net_lat: 9 + L1Cache-7 -> L1Cache-3 net_lat: 9 + L1Cache-7 -> L1Cache-4 net_lat: 9 + L1Cache-7 -> L1Cache-5 net_lat: 9 + L1Cache-7 -> L1Cache-6 net_lat: 9 + L1Cache-7 -> Directory-0 net_lat: 9 + L1Cache-7 -> Directory-1 net_lat: 9 + L1Cache-7 -> Directory-2 net_lat: 9 + L1Cache-7 -> Directory-3 net_lat: 9 + L1Cache-7 -> Directory-4 net_lat: 9 + L1Cache-7 -> Directory-5 net_lat: 9 + L1Cache-7 -> Directory-6 net_lat: 9 + L1Cache-7 -> Directory-7 net_lat: 9 + +Directory-0 Network Latencies + Directory-0 -> L1Cache-0 net_lat: 9 + Directory-0 -> L1Cache-1 net_lat: 9 + Directory-0 -> L1Cache-2 net_lat: 9 + Directory-0 -> L1Cache-3 net_lat: 9 + Directory-0 -> L1Cache-4 net_lat: 9 + Directory-0 -> L1Cache-5 net_lat: 9 + Directory-0 -> L1Cache-6 net_lat: 9 + Directory-0 -> L1Cache-7 net_lat: 9 + Directory-0 -> Directory-1 net_lat: 9 + Directory-0 -> Directory-2 net_lat: 9 + Directory-0 -> Directory-3 net_lat: 9 + Directory-0 -> Directory-4 net_lat: 9 + Directory-0 -> Directory-5 net_lat: 9 + Directory-0 -> Directory-6 net_lat: 9 + Directory-0 -> Directory-7 net_lat: 9 + +Directory-1 Network Latencies + Directory-1 -> L1Cache-0 net_lat: 9 + Directory-1 -> L1Cache-1 net_lat: 9 + Directory-1 -> L1Cache-2 net_lat: 9 + Directory-1 -> L1Cache-3 net_lat: 9 + Directory-1 -> L1Cache-4 net_lat: 9 + Directory-1 -> L1Cache-5 net_lat: 9 + Directory-1 -> L1Cache-6 net_lat: 9 + Directory-1 -> L1Cache-7 net_lat: 9 + Directory-1 -> Directory-0 net_lat: 9 + Directory-1 -> Directory-2 net_lat: 9 + Directory-1 -> Directory-3 net_lat: 9 + Directory-1 -> Directory-4 net_lat: 9 + Directory-1 -> Directory-5 net_lat: 9 + Directory-1 -> Directory-6 net_lat: 9 + Directory-1 -> Directory-7 net_lat: 9 + +Directory-2 Network Latencies + Directory-2 -> L1Cache-0 net_lat: 9 + Directory-2 -> L1Cache-1 net_lat: 9 + Directory-2 -> L1Cache-2 net_lat: 9 + Directory-2 -> L1Cache-3 net_lat: 9 + Directory-2 -> L1Cache-4 net_lat: 9 + Directory-2 -> L1Cache-5 net_lat: 9 + Directory-2 -> L1Cache-6 net_lat: 9 + Directory-2 -> L1Cache-7 net_lat: 9 + Directory-2 -> Directory-0 net_lat: 9 + Directory-2 -> Directory-1 net_lat: 9 + Directory-2 -> Directory-3 net_lat: 9 + Directory-2 -> Directory-4 net_lat: 9 + Directory-2 -> Directory-5 net_lat: 9 + Directory-2 -> Directory-6 net_lat: 9 + Directory-2 -> Directory-7 net_lat: 9 + +Directory-3 Network Latencies + Directory-3 -> L1Cache-0 net_lat: 9 + Directory-3 -> L1Cache-1 net_lat: 9 + Directory-3 -> L1Cache-2 net_lat: 9 + Directory-3 -> L1Cache-3 net_lat: 9 + Directory-3 -> L1Cache-4 net_lat: 9 + Directory-3 -> L1Cache-5 net_lat: 9 + Directory-3 -> L1Cache-6 net_lat: 9 + Directory-3 -> L1Cache-7 net_lat: 9 + Directory-3 -> Directory-0 net_lat: 9 + Directory-3 -> Directory-1 net_lat: 9 + Directory-3 -> Directory-2 net_lat: 9 + Directory-3 -> Directory-4 net_lat: 9 + Directory-3 -> Directory-5 net_lat: 9 + Directory-3 -> Directory-6 net_lat: 9 + Directory-3 -> Directory-7 net_lat: 9 + +Directory-4 Network Latencies + Directory-4 -> L1Cache-0 net_lat: 9 + Directory-4 -> L1Cache-1 net_lat: 9 + Directory-4 -> L1Cache-2 net_lat: 9 + Directory-4 -> L1Cache-3 net_lat: 9 + Directory-4 -> L1Cache-4 net_lat: 9 + Directory-4 -> L1Cache-5 net_lat: 9 + Directory-4 -> L1Cache-6 net_lat: 9 + Directory-4 -> L1Cache-7 net_lat: 9 + Directory-4 -> Directory-0 net_lat: 9 + Directory-4 -> Directory-1 net_lat: 9 + Directory-4 -> Directory-2 net_lat: 9 + Directory-4 -> Directory-3 net_lat: 9 + Directory-4 -> Directory-5 net_lat: 9 + Directory-4 -> Directory-6 net_lat: 9 + Directory-4 -> Directory-7 net_lat: 9 + +Directory-5 Network Latencies + Directory-5 -> L1Cache-0 net_lat: 9 + Directory-5 -> L1Cache-1 net_lat: 9 + Directory-5 -> L1Cache-2 net_lat: 9 + Directory-5 -> L1Cache-3 net_lat: 9 + Directory-5 -> L1Cache-4 net_lat: 9 + Directory-5 -> L1Cache-5 net_lat: 9 + Directory-5 -> L1Cache-6 net_lat: 9 + Directory-5 -> L1Cache-7 net_lat: 9 + Directory-5 -> Directory-0 net_lat: 9 + Directory-5 -> Directory-1 net_lat: 9 + Directory-5 -> Directory-2 net_lat: 9 + Directory-5 -> Directory-3 net_lat: 9 + Directory-5 -> Directory-4 net_lat: 9 + Directory-5 -> Directory-6 net_lat: 9 + Directory-5 -> Directory-7 net_lat: 9 + +Directory-6 Network Latencies + Directory-6 -> L1Cache-0 net_lat: 9 + Directory-6 -> L1Cache-1 net_lat: 9 + Directory-6 -> L1Cache-2 net_lat: 9 + Directory-6 -> L1Cache-3 net_lat: 9 + Directory-6 -> L1Cache-4 net_lat: 9 + Directory-6 -> L1Cache-5 net_lat: 9 + Directory-6 -> L1Cache-6 net_lat: 9 + Directory-6 -> L1Cache-7 net_lat: 9 + Directory-6 -> Directory-0 net_lat: 9 + Directory-6 -> Directory-1 net_lat: 9 + Directory-6 -> Directory-2 net_lat: 9 + Directory-6 -> Directory-3 net_lat: 9 + Directory-6 -> Directory-4 net_lat: 9 + Directory-6 -> Directory-5 net_lat: 9 + Directory-6 -> Directory-7 net_lat: 9 + +Directory-7 Network Latencies + Directory-7 -> L1Cache-0 net_lat: 9 + Directory-7 -> L1Cache-1 net_lat: 9 + Directory-7 -> L1Cache-2 net_lat: 9 + Directory-7 -> L1Cache-3 net_lat: 9 + Directory-7 -> L1Cache-4 net_lat: 9 + Directory-7 -> L1Cache-5 net_lat: 9 + Directory-7 -> L1Cache-6 net_lat: 9 + Directory-7 -> L1Cache-7 net_lat: 9 + Directory-7 -> Directory-0 net_lat: 9 + Directory-7 -> Directory-1 net_lat: 9 + Directory-7 -> Directory-2 net_lat: 9 + Directory-7 -> Directory-3 net_lat: 9 + Directory-7 -> Directory-4 net_lat: 9 + Directory-7 -> Directory-5 net_lat: 9 + Directory-7 -> Directory-6 net_lat: 9 + +--- End Topology Print --- + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: May/05/2009 07:44:03 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 600 +Elapsed_time_in_minutes: 10 +Elapsed_time_in_hours: 0.166667 +Elapsed_time_in_days: 0.00694444 + +Virtual_time_in_seconds: 600.33 +Virtual_time_in_minutes: 10.0055 +Virtual_time_in_hours: 0.166758 +Virtual_time_in_days: 0.166758 + +Ruby_current_time: 4446777 +Ruby_start_time: 1 +Ruby_cycles: 4446776 + +mbytes_resident: 168.625 +mbytes_total: 457.891 +resident_ratio: 0.368273 + +Total_misses: 721271 +total_misses: 721271 [ 90191 90177 90170 90159 90144 90184 90135 90111 ] +user_misses: 721271 [ 90191 90177 90170 90159 90144 90184 90135 90111 ] +supervisor_misses: 0 [ 0 0 0 0 0 0 0 0 ] + +instruction_executed: 8 [ 1 1 1 1 1 1 1 1 ] +cycles_executed: 8 [ 1 1 1 1 1 1 1 1 ] +cycles_per_instruction: 4.44678e+06 [ 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 4.44678e+06 ] +misses_per_thousand_instructions: 9.01589e+07 [ 9.0191e+07 9.0177e+07 9.017e+07 9.0159e+07 9.0144e+07 9.0184e+07 9.0135e+07 9.0111e+07 ] + +transactions_started: 0 [ 0 0 0 0 0 0 0 0 ] +transactions_ended: 0 [ 0 0 0 0 0 0 0 0 ] +instructions_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] +cycles_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] +misses_per_transaction: 0 [ 0 0 0 0 0 0 0 0 ] + +L1D_cache cache stats: + L1D_cache_total_misses: 745688 + L1D_cache_total_demand_misses: 745688 + L1D_cache_total_prefetches: 0 + L1D_cache_total_sw_prefetches: 0 + L1D_cache_total_hw_prefetches: 0 + L1D_cache_misses_per_transaction: 745688 + L1D_cache_misses_per_instruction: 745688 + L1D_cache_instructions_per_misses: 1.34104e-06 + + L1D_cache_request_type_LD: 65.1516% + L1D_cache_request_type_ST: 34.8484% + + L1D_cache_access_mode_type_UserMode: 745688 100% + L1D_cache_request_size: [binsize: log2 max: 1 count: 745688 average: 1 | standard deviation: 0 | 0 745688 ] + +L1I_cache cache stats: + L1I_cache_total_misses: 0 + L1I_cache_total_demand_misses: 0 + L1I_cache_total_prefetches: 0 + L1I_cache_total_sw_prefetches: 0 + L1I_cache_total_hw_prefetches: 0 + L1I_cache_misses_per_transaction: 0 + L1I_cache_misses_per_instruction: 0 + L1I_cache_instructions_per_misses: NaN + + L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +L2_cache cache stats: + L2_cache_total_misses: 721271 + L2_cache_total_demand_misses: 721271 + L2_cache_total_prefetches: 0 + L2_cache_total_sw_prefetches: 0 + L2_cache_total_hw_prefetches: 0 + L2_cache_misses_per_transaction: 721271 + L2_cache_misses_per_instruction: 721271 + L2_cache_instructions_per_misses: 1.38644e-06 + + L2_cache_request_type_LD: 63.9719% + L2_cache_request_type_ST: 36.0281% + + L2_cache_access_mode_type_UserMode: 721271 100% + L2_cache_request_size: [binsize: log2 max: 1 count: 721271 average: 1 | standard deviation: 0 | 0 721271 ] + + +Busy Controller Counts: +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 + +Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0 Directory-4:0 Directory-5:0 Directory-6:0 Directory-7:0 + + +Busy Bank Count:0 + +L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +L2TBE_usage: [binsize: 1 max: 15 count: 721271 average: 2.03629 | standard deviation: 2.34771 | 143227 223076 166564 88859 41156 18332 8540 4969 3538 3168 3367 3419 3399 3457 3198 3002 ] +StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 745688 average: 3.10967 | standard deviation: 2.34747 | 0 135014 224824 178310 98438 46220 20718 9529 5314 3675 3215 3360 3521 3368 3500 3258 3424 ] +store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 8 max: 1116 count: 745669 average: 106.682 | standard deviation: 99.0818 | 24417 622 615 521 35683 54628 61710 64752 61426 56993 50743 43645 37419 32707 28113 24160 20402 17446 15135 13054 11166 9337 8153 7202 6087 5203 4349 3878 3227 2804 2344 2092 1784 1513 1405 1207 1044 926 815 785 646 657 585 540 532 530 552 516 525 517 552 512 548 540 592 609 634 610 628 609 600 596 622 617 575 568 506 532 504 535 484 441 430 386 424 360 346 330 303 267 268 265 243 208 204 186 194 183 190 188 161 169 164 165 153 148 142 133 136 123 117 101 109 110 96 102 94 82 115 83 80 67 72 56 43 50 40 32 28 26 27 20 15 15 11 11 8 10 12 7 4 6 9 3 4 2 3 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 8 max: 1116 count: 485819 average: 105.451 | standard deviation: 99.9404 | 24417 0 0 0 22626 34580 39558 41559 39317 36732 32549 27946 23929 21013 18042 15529 13125 11165 9814 8327 7126 6019 5331 4661 3925 3326 2749 2527 2019 1814 1505 1387 1182 973 911 794 687 625 536 526 404 426 376 345 350 349 371 328 352 345 353 330 353 341 365 373 403 402 406 367 392 370 393 397 366 372 322 330 327 364 310 288 280 251 285 249 233 209 206 172 189 178 161 142 134 117 126 110 124 129 101 113 109 109 99 97 84 90 82 76 72 71 78 70 69 70 73 53 82 57 56 45 47 39 27 29 27 24 23 20 17 12 7 10 8 7 6 8 10 4 3 3 6 1 3 1 2 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 8 max: 1112 count: 259850 average: 108.983 | standard deviation: 97.4146 | 0 622 615 521 13057 20048 22152 23193 22109 20261 18194 15699 13490 11694 10071 8631 7277 6281 5321 4727 4040 3318 2822 2541 2162 1877 1600 1351 1208 990 839 705 602 540 494 413 357 301 279 259 242 231 209 195 182 181 181 188 173 172 199 182 195 199 227 236 231 208 222 242 208 226 229 220 209 196 184 202 177 171 174 153 150 135 139 111 113 121 97 95 79 87 82 66 70 69 68 73 66 59 60 56 55 56 54 51 58 43 54 47 45 30 31 40 27 32 21 29 33 26 24 22 25 17 16 21 13 8 5 6 10 8 8 5 3 4 2 2 2 3 1 3 3 2 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 8 max: 1116 count: 745669 average: 106.682 | standard deviation: 99.0818 | 24417 622 615 521 35683 54628 61710 64752 61426 56993 50743 43645 37419 32707 28113 24160 20402 17446 15135 13054 11166 9337 8153 7202 6087 5203 4349 3878 3227 2804 2344 2092 1784 1513 1405 1207 1044 926 815 785 646 657 585 540 532 530 552 516 525 517 552 512 548 540 592 609 634 610 628 609 600 596 622 617 575 568 506 532 504 535 484 441 430 386 424 360 346 330 303 267 268 265 243 208 204 186 194 183 190 188 161 169 164 165 153 148 142 133 136 123 117 101 109 110 96 102 94 82 115 83 80 67 72 56 43 50 40 32 28 26 27 20 15 15 11 11 8 10 12 7 4 6 9 3 4 2 3 2 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +conflicting_histogram: [binsize: log2 max: 4446776 count: 721271 average: 2.2084e+06 | standard deviation: 2.55884e+06 | 0 0 0 1 2 6 10 24 46 86 63 240 490 927 1836 3670 6574 12027 21272 42384 84410 168738 337705 40760 ] +conflicting_histogram_percent: [binsize: log2 max: 4446776 count: 721271 average: 2.2084e+06 | standard deviation: 2.55884e+06 | 0 0 0 0.000138644 0.000277288 0.000831865 0.00138644 0.00332746 0.00637763 0.0119234 0.00873458 0.0332746 0.0679356 0.128523 0.254551 0.508824 0.911447 1.66747 2.94924 5.87629 11.703 23.3945 46.8208 5.65114 ] + +Request vs. RubySystem State Profile +-------------------------------- + + I M GETS 163897 22.7234 + I M GETX 87421 12.1204 + I OS GETS 106703 14.7938 + I OS GETX 57217 7.93282 + I OSS GETS 174691 24.22 + I OSS GETX 93632 12.9816 + NP C GETS 2027 0.281032 + NP C GETX 1045 0.144884 + NP M GETS 4871 0.675337 + NP M GETX 2611 0.362001 + NP OS GETS 2755 0.381966 + NP OS GETX 1417 0.196459 + NP OSS GETS 3034 0.420647 + NP OSS GETX 1534 0.212681 + NP S GETS 1318 0.182733 + NP S GETX 704 0.0976057 + NP SS GETS 2114 0.293095 + NP SS GETX 1146 0.158887 + O OS GETX 11 0.00152509 + O OSS GETX 4695 0.650936 + S M GETX 9 0.0012478 + S OS GETX 1 0.000138645 + S OSS GETX 8239 1.14229 + S S GETX 5 0.000693223 + S SS GETX 172 0.0238469 + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 599 +system_time: 1 +page_reclaims: 43363 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 160 +MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:93207 full:0 +MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:93229 full:0 +MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:93192 full:0 +MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:93200 full:0 +MessageBuffer: [Chip 4 0, L1Cache, mandatoryQueue_in] stats - msgs:93207 full:0 +MessageBuffer: [Chip 5 0, L1Cache, mandatoryQueue_in] stats - msgs:93210 full:0 +MessageBuffer: [Chip 6 0, L1Cache, mandatoryQueue_in] stats - msgs:93209 full:0 +MessageBuffer: [Chip 7 0, L1Cache, mandatoryQueue_in] stats - msgs:93234 full:0 + +Network Stats +------------- + +switch_0_inlinks: 1 +switch_0_outlinks: 1 +links_utilized_percent_switch_0: 15.85 + links_utilized_percent_switch_0_link_0: 15.85 bw: 10000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Control: 90191 721528 [ 90191 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Data: 87870 6326640 [ 0 87870 0 0 ] base_latency: 1 + +switch_1_inlinks: 1 +switch_1_outlinks: 1 +links_utilized_percent_switch_1: 16.1391 + links_utilized_percent_switch_1_link_0: 16.1391 bw: 10000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 90177 721416 [ 90177 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 89657 6455304 [ 0 89657 0 0 ] base_latency: 1 + +switch_2_inlinks: 1 +switch_2_outlinks: 1 +links_utilized_percent_switch_2: 15.956 + links_utilized_percent_switch_2_link_0: 15.956 bw: 10000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 90169 721352 [ 90169 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Data: 88527 6373944 [ 0 88527 0 0 ] base_latency: 1 + +switch_3_inlinks: 1 +switch_3_outlinks: 1 +links_utilized_percent_switch_3: 15.9235 + links_utilized_percent_switch_3_link_0: 15.9235 bw: 10000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Control: 90158 721264 [ 90158 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Data: 88327 6359544 [ 0 88327 0 0 ] base_latency: 1 + +switch_4_inlinks: 1 +switch_4_outlinks: 1 +links_utilized_percent_switch_4: 15.9062 + links_utilized_percent_switch_4_link_0: 15.9062 bw: 10000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Control: 90144 721152 [ 90144 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Data: 88222 6351984 [ 0 88222 0 0 ] base_latency: 1 + +switch_5_inlinks: 1 +switch_5_outlinks: 1 +links_utilized_percent_switch_5: 15.8852 + links_utilized_percent_switch_5_link_0: 15.8852 bw: 10000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Control: 90184 721472 [ 90184 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Data: 88088 6342336 [ 0 88088 0 0 ] base_latency: 1 + +switch_6_inlinks: 1 +switch_6_outlinks: 1 +links_utilized_percent_switch_6: 15.8419 + links_utilized_percent_switch_6_link_0: 15.8419 bw: 10000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Control: 90135 721080 [ 90135 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Data: 87826 6323472 [ 0 87826 0 0 ] base_latency: 1 + +switch_7_inlinks: 1 +switch_7_outlinks: 1 +links_utilized_percent_switch_7: 16.1135 + links_utilized_percent_switch_7_link_0: 16.1135 bw: 10000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Control: 90111 720888 [ 90111 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Data: 89506 6444432 [ 0 89506 0 0 ] base_latency: 1 + +switch_8_inlinks: 1 +switch_8_outlinks: 1 +links_utilized_percent_switch_8: 0.167582 + links_utilized_percent_switch_8_link_0: 0.167582 bw: 10000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Data: 1035 74520 [ 0 1035 0 0 ] base_latency: 1 + +switch_9_inlinks: 1 +switch_9_outlinks: 1 +links_utilized_percent_switch_9: 0.165477 + links_utilized_percent_switch_9_link_0: 0.165477 bw: 10000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Data: 1022 73584 [ 0 1022 0 0 ] base_latency: 1 + +switch_10_inlinks: 1 +switch_10_outlinks: 1 +links_utilized_percent_switch_10: 0.167258 + links_utilized_percent_switch_10_link_0: 0.167258 bw: 10000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Data: 1033 74376 [ 0 1033 0 0 ] base_latency: 1 + +switch_11_inlinks: 1 +switch_11_outlinks: 1 +links_utilized_percent_switch_11: 0.173735 + links_utilized_percent_switch_11_link_0: 0.173735 bw: 10000 base_latency: 1 + + outgoing_messages_switch_11_link_0_Data: 1073 77256 [ 0 1073 0 0 ] base_latency: 1 + +switch_12_inlinks: 1 +switch_12_outlinks: 1 +links_utilized_percent_switch_12: 0.181507 + links_utilized_percent_switch_12_link_0: 0.181507 bw: 10000 base_latency: 1 + + outgoing_messages_switch_12_link_0_Data: 1121 80712 [ 0 1121 0 0 ] base_latency: 1 + +switch_13_inlinks: 1 +switch_13_outlinks: 1 +links_utilized_percent_switch_13: 0.184097 + links_utilized_percent_switch_13_link_0: 0.184097 bw: 10000 base_latency: 1 + + outgoing_messages_switch_13_link_0_Data: 1137 81864 [ 0 1137 0 0 ] base_latency: 1 + +switch_14_inlinks: 1 +switch_14_outlinks: 1 +links_utilized_percent_switch_14: 0.170011 + links_utilized_percent_switch_14_link_0: 0.170011 bw: 10000 base_latency: 1 + + outgoing_messages_switch_14_link_0_Data: 1050 75600 [ 0 1050 0 0 ] base_latency: 1 + +switch_15_inlinks: 1 +switch_15_outlinks: 1 +links_utilized_percent_switch_15: 0.17163 + links_utilized_percent_switch_15_link_0: 0.17163 bw: 10000 base_latency: 1 + + outgoing_messages_switch_15_link_0_Data: 1060 76320 [ 0 1060 0 0 ] base_latency: 1 + +switch_16_inlinks: 4 +switch_16_outlinks: 1 +links_utilized_percent_switch_16: 63.8683 + links_utilized_percent_switch_16_link_0: 63.8683 bw: 10000 base_latency: 1 + + outgoing_messages_switch_16_link_0_Control: 360695 2885560 [ 360695 0 0 0 ] base_latency: 1 + outgoing_messages_switch_16_link_0_Data: 354379 25515288 [ 0 354379 0 0 ] base_latency: 1 + +switch_17_inlinks: 4 +switch_17_outlinks: 1 +links_utilized_percent_switch_17: 63.7469 + links_utilized_percent_switch_17_link_0: 63.7469 bw: 10000 base_latency: 1 + + outgoing_messages_switch_17_link_0_Control: 360574 2884592 [ 360574 0 0 0 ] base_latency: 1 + outgoing_messages_switch_17_link_0_Data: 353642 25462224 [ 0 353642 0 0 ] base_latency: 1 + +switch_18_inlinks: 4 +switch_18_outlinks: 1 +links_utilized_percent_switch_18: 0.674052 + links_utilized_percent_switch_18_link_0: 0.674052 bw: 10000 base_latency: 1 + + outgoing_messages_switch_18_link_0_Data: 4163 299736 [ 0 4163 0 0 ] base_latency: 1 + +switch_19_inlinks: 4 +switch_19_outlinks: 1 +links_utilized_percent_switch_19: 0.707245 + links_utilized_percent_switch_19_link_0: 0.707245 bw: 10000 base_latency: 1 + + outgoing_messages_switch_19_link_0_Data: 4368 314496 [ 0 4368 0 0 ] base_latency: 1 + +switch_20_inlinks: 4 +switch_20_outlinks: 4 +links_utilized_percent_switch_20: 38.737 + links_utilized_percent_switch_20_link_0: 71.0033 bw: 10000 base_latency: 1 + links_utilized_percent_switch_20_link_1: 70.9688 bw: 10000 base_latency: 1 + links_utilized_percent_switch_20_link_2: 6.48531 bw: 10000 base_latency: 1 + links_utilized_percent_switch_20_link_3: 6.49072 bw: 10000 base_latency: 1 + + outgoing_messages_switch_20_link_0_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1 + outgoing_messages_switch_20_link_0_Data: 358382 25803504 [ 0 358382 0 0 ] base_latency: 1 + outgoing_messages_switch_20_link_1_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1 + outgoing_messages_switch_20_link_1_Data: 358170 25788240 [ 0 358170 0 0 ] base_latency: 1 + outgoing_messages_switch_20_link_2_Control: 360484 2883872 [ 360484 0 0 0 ] base_latency: 1 + outgoing_messages_switch_20_link_3_Control: 360785 2886280 [ 360785 0 0 0 ] base_latency: 1 + +switch_21_inlinks: 1 +switch_21_outlinks: 4 +links_utilized_percent_switch_21: 27.4829 + links_utilized_percent_switch_21_link_0: 27.4857 bw: 10000 base_latency: 1 + links_utilized_percent_switch_21_link_1: 27.4791 bw: 10000 base_latency: 1 + links_utilized_percent_switch_21_link_2: 27.4873 bw: 10000 base_latency: 1 + links_utilized_percent_switch_21_link_3: 27.4793 bw: 10000 base_latency: 1 + + outgoing_messages_switch_21_link_0_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1 + outgoing_messages_switch_21_link_0_Data: 89613 6452136 [ 0 89613 0 0 ] base_latency: 1 + outgoing_messages_switch_21_link_1_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1 + outgoing_messages_switch_21_link_1_Data: 89572 6449184 [ 0 89572 0 0 ] base_latency: 1 + outgoing_messages_switch_21_link_2_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1 + outgoing_messages_switch_21_link_2_Data: 89623 6452856 [ 0 89623 0 0 ] base_latency: 1 + outgoing_messages_switch_21_link_3_Control: 721269 5770152 [ 721269 0 0 0 ] base_latency: 1 + outgoing_messages_switch_21_link_3_Data: 89573 6449256 [ 0 89573 0 0 ] base_latency: 1 + +switch_22_inlinks: 1 +switch_22_outlinks: 4 +links_utilized_percent_switch_22: 27.474 + links_utilized_percent_switch_22_link_0: 27.4713 bw: 10000 base_latency: 1 + links_utilized_percent_switch_22_link_1: 27.4807 bw: 10000 base_latency: 1 + links_utilized_percent_switch_22_link_2: 27.4725 bw: 10000 base_latency: 1 + links_utilized_percent_switch_22_link_3: 27.4715 bw: 10000 base_latency: 1 + + outgoing_messages_switch_22_link_0_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1 + outgoing_messages_switch_22_link_0_Data: 89526 6445872 [ 0 89526 0 0 ] base_latency: 1 + outgoing_messages_switch_22_link_1_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1 + outgoing_messages_switch_22_link_1_Data: 89584 6450048 [ 0 89584 0 0 ] base_latency: 1 + outgoing_messages_switch_22_link_2_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1 + outgoing_messages_switch_22_link_2_Data: 89533 6446376 [ 0 89533 0 0 ] base_latency: 1 + outgoing_messages_switch_22_link_3_Control: 721252 5770016 [ 721252 0 0 0 ] base_latency: 1 + outgoing_messages_switch_22_link_3_Data: 89527 6445944 [ 0 89527 0 0 ] base_latency: 1 + +switch_23_inlinks: 1 +switch_23_outlinks: 4 +links_utilized_percent_switch_23: 1.62133 + links_utilized_percent_switch_23_link_0: 1.6212 bw: 10000 base_latency: 1 + links_utilized_percent_switch_23_link_1: 1.62023 bw: 10000 base_latency: 1 + links_utilized_percent_switch_23_link_2: 1.62027 bw: 10000 base_latency: 1 + links_utilized_percent_switch_23_link_3: 1.62361 bw: 10000 base_latency: 1 + + outgoing_messages_switch_23_link_0_Control: 90114 720912 [ 90114 0 0 0 ] base_latency: 1 + outgoing_messages_switch_23_link_1_Control: 90060 720480 [ 90060 0 0 0 ] base_latency: 1 + outgoing_messages_switch_23_link_2_Control: 90062 720496 [ 90062 0 0 0 ] base_latency: 1 + outgoing_messages_switch_23_link_3_Control: 90248 721984 [ 90248 0 0 0 ] base_latency: 1 + +switch_24_inlinks: 1 +switch_24_outlinks: 4 +links_utilized_percent_switch_24: 1.62268 + links_utilized_percent_switch_24_link_0: 1.62295 bw: 10000 base_latency: 1 + links_utilized_percent_switch_24_link_1: 1.62417 bw: 10000 base_latency: 1 + links_utilized_percent_switch_24_link_2: 1.62052 bw: 10000 base_latency: 1 + links_utilized_percent_switch_24_link_3: 1.62309 bw: 10000 base_latency: 1 + + outgoing_messages_switch_24_link_0_Control: 90211 721688 [ 90211 0 0 0 ] base_latency: 1 + outgoing_messages_switch_24_link_1_Control: 90279 722232 [ 90279 0 0 0 ] base_latency: 1 + outgoing_messages_switch_24_link_2_Control: 90076 720608 [ 90076 0 0 0 ] base_latency: 1 + outgoing_messages_switch_24_link_3_Control: 90219 721752 [ 90219 0 0 0 ] base_latency: 1 + + +Chip Stats +---------- + + --- L1Cache --- + - Event Counts - +Load 485828 +Ifetch 0 +Store 259860 +L1_to_L2 737242 +L2_to_L1D 720852 +L2_to_L1I 0 +L2_Replacement 0 +Own_GETS 461405 +Own_GET_INSTR 0 +Own_GETX 259855 +Own_PUTX 0 +Other_GETS 3229843 +Other_GET_INSTR 0 +Other_GETX 1818981 +Other_PUTX 0 +Data 716551 + + - Transitions - +NP Load 16119 +NP Ifetch 0 <-- +NP Store 8457 +NP Other_GETS 58716 +NP Other_GET_INSTR 0 <-- +NP Other_GETX 31715 +NP Other_PUTX 0 <-- + +I Load 445292 +I Ifetch 0 <-- +I Store 238271 +I L1_to_L2 409661 +I L2_to_L1D 683358 +I L2_to_L1I 0 <-- +I L2_Replacement 0 <-- +I Other_GETS 2030822 +I Other_GET_INSTR 0 <-- +I Other_GETX 1087031 +I Other_PUTX 0 <-- + +S Load 15687 +S Ifetch 0 <-- +S Store 8426 +S L1_to_L2 209306 +S L2_to_L1D 24075 +S L2_to_L1I 0 <-- +S L2_Replacement 0 <-- +S Other_GETS 682440 +S Other_GET_INSTR 0 <-- +S Other_GETX 447103 +S Other_PUTX 0 <-- + +O Load 8725 +O Ifetch 0 <-- +O Store 4706 +O L1_to_L2 89987 +O L2_to_L1D 13414 +O L2_to_L1I 0 <-- +O L2_Replacement 0 <-- +O Other_GETS 287176 +O Other_GET_INSTR 0 <-- +O Other_GETX 162038 +O Other_PUTX 0 <-- + +M Load 5 +M Ifetch 0 <-- +M Store 0 <-- +M L1_to_L2 28282 +M L2_to_L1D 5 +M L2_to_L1I 0 <-- +M L2_Replacement 0 <-- +M Other_GETS 168458 +M Other_GET_INSTR 0 <-- +M Other_GETX 89842 +M Other_PUTX 0 <-- + +IS_AD Load 0 <-- +IS_AD Ifetch 0 <-- +IS_AD Store 0 <-- +IS_AD L1_to_L2 0 <-- +IS_AD L2_to_L1D 0 <-- +IS_AD L2_to_L1I 0 <-- +IS_AD L2_Replacement 0 <-- +IS_AD Own_GETS 408918 +IS_AD Own_GET_INSTR 0 <-- +IS_AD Other_GETS 753 +IS_AD Other_GET_INSTR 0 <-- +IS_AD Other_GETX 445 +IS_AD Other_PUTX 0 <-- +IS_AD Data 52490 + +IM_AD Load 0 <-- +IM_AD Ifetch 0 <-- +IM_AD Store 0 <-- +IM_AD L1_to_L2 0 <-- +IM_AD L2_to_L1D 0 <-- +IM_AD L2_to_L1I 0 <-- +IM_AD L2_Replacement 0 <-- +IM_AD Own_GETX 218774 +IM_AD Other_GETS 401 +IM_AD Other_GET_INSTR 0 <-- +IM_AD Other_GETX 262 +IM_AD Other_PUTX 0 <-- +IM_AD Data 27960 + +SM_AD Load 0 <-- +SM_AD Ifetch 0 <-- +SM_AD Store 0 <-- +SM_AD L1_to_L2 0 <-- +SM_AD L2_to_L1D 0 <-- +SM_AD L2_to_L1I 0 <-- +SM_AD L2_Replacement 0 <-- +SM_AD Own_GETX 7503 +SM_AD Other_GETS 2 +SM_AD Other_GET_INSTR 0 <-- +SM_AD Other_GETX 9 +SM_AD Other_PUTX 0 <-- +SM_AD Data 914 + +OM_A Load 0 <-- +OM_A Ifetch 0 <-- +OM_A Store 0 <-- +OM_A L1_to_L2 0 <-- +OM_A L2_to_L1D 0 <-- +OM_A L2_to_L1I 0 <-- +OM_A L2_Replacement 0 <-- +OM_A Own_GETX 4705 +OM_A Other_GETS 4 +OM_A Other_GET_INSTR 0 <-- +OM_A Other_GETX 0 <-- +OM_A Other_PUTX 0 <-- +OM_A Data 0 <-- + +IS_A Load 0 <-- +IS_A Ifetch 0 <-- +IS_A Store 0 <-- +IS_A L1_to_L2 0 <-- +IS_A L2_to_L1D 0 <-- +IS_A L2_to_L1I 0 <-- +IS_A L2_Replacement 0 <-- +IS_A Own_GETS 52487 +IS_A Own_GET_INSTR 0 <-- +IS_A Other_GETS 95 +IS_A Other_GET_INSTR 0 <-- +IS_A Other_GETX 14 +IS_A Other_PUTX 0 <-- + +IM_A Load 0 <-- +IM_A Ifetch 0 <-- +IM_A Store 0 <-- +IM_A L1_to_L2 0 <-- +IM_A L2_to_L1D 0 <-- +IM_A L2_to_L1I 0 <-- +IM_A L2_Replacement 0 <-- +IM_A Own_GETX 27959 +IM_A Other_GETS 53 +IM_A Other_GET_INSTR 0 <-- +IM_A Other_GETX 12 +IM_A Other_PUTX 0 <-- + +SM_A Load 0 <-- +SM_A Ifetch 0 <-- +SM_A Store 0 <-- +SM_A L1_to_L2 0 <-- +SM_A L2_to_L1D 0 <-- +SM_A L2_to_L1I 0 <-- +SM_A L2_Replacement 0 <-- +SM_A Own_GETX 914 +SM_A Other_GETS 2 +SM_A Other_GET_INSTR 0 <-- +SM_A Other_GETX 0 <-- +SM_A Other_PUTX 0 <-- + +MI_A Load 0 <-- +MI_A Ifetch 0 <-- +MI_A Store 0 <-- +MI_A L1_to_L2 0 <-- +MI_A L2_to_L1D 0 <-- +MI_A L2_to_L1I 0 <-- +MI_A L2_Replacement 0 <-- +MI_A Own_PUTX 0 <-- +MI_A Other_GETS 0 <-- +MI_A Other_GET_INSTR 0 <-- +MI_A Other_GETX 0 <-- +MI_A Other_PUTX 0 <-- + +OI_A Load 0 <-- +OI_A Ifetch 0 <-- +OI_A Store 0 <-- +OI_A L1_to_L2 0 <-- +OI_A L2_to_L1D 0 <-- +OI_A L2_to_L1I 0 <-- +OI_A L2_Replacement 0 <-- +OI_A Own_PUTX 0 <-- +OI_A Other_GETS 0 <-- +OI_A Other_GET_INSTR 0 <-- +OI_A Other_GETX 0 <-- +OI_A Other_PUTX 0 <-- + +II_A Load 0 <-- +II_A Ifetch 0 <-- +II_A Store 0 <-- +II_A L1_to_L2 0 <-- +II_A L2_to_L1D 0 <-- +II_A L2_to_L1I 0 <-- +II_A L2_Replacement 0 <-- +II_A Own_PUTX 0 <-- +II_A Other_GETS 0 <-- +II_A Other_GET_INSTR 0 <-- +II_A Other_GETX 0 <-- +II_A Other_PUTX 0 <-- + +IS_D Load 0 <-- +IS_D Ifetch 0 <-- +IS_D Store 0 <-- +IS_D L1_to_L2 6 +IS_D L2_to_L1D 0 <-- +IS_D L2_to_L1I 0 <-- +IS_D L2_Replacement 0 <-- +IS_D Other_GETS 611 +IS_D Other_GET_INSTR 0 <-- +IS_D Other_GETX 314 +IS_D Other_PUTX 0 <-- +IS_D Data 408601 + +IS_D_I Load 0 <-- +IS_D_I Ifetch 0 <-- +IS_D_I Store 0 <-- +IS_D_I L1_to_L2 0 <-- +IS_D_I L2_to_L1D 0 <-- +IS_D_I L2_to_L1I 0 <-- +IS_D_I L2_Replacement 0 <-- +IS_D_I Other_GETS 0 <-- +IS_D_I Other_GET_INSTR 0 <-- +IS_D_I Other_GETX 0 <-- +IS_D_I Other_PUTX 0 <-- +IS_D_I Data 314 + +IM_D Load 0 <-- +IM_D Ifetch 0 <-- +IM_D Store 0 <-- +IM_D L1_to_L2 0 <-- +IM_D L2_to_L1D 0 <-- +IM_D L2_to_L1I 0 <-- +IM_D L2_Replacement 0 <-- +IM_D Other_GETS 302 +IM_D Other_GET_INSTR 0 <-- +IM_D Other_GETX 188 +IM_D Other_PUTX 0 <-- +IM_D Data 218279 + +IM_D_O Load 0 <-- +IM_D_O Ifetch 0 <-- +IM_D_O Store 0 <-- +IM_D_O L1_to_L2 0 <-- +IM_D_O L2_to_L1D 0 <-- +IM_D_O L2_to_L1I 0 <-- +IM_D_O L2_Replacement 0 <-- +IM_D_O Other_GETS 0 <-- +IM_D_O Other_GET_INSTR 0 <-- +IM_D_O Other_GETX 0 <-- +IM_D_O Other_PUTX 0 <-- +IM_D_O Data 302 + +IM_D_I Load 0 <-- +IM_D_I Ifetch 0 <-- +IM_D_I Store 0 <-- +IM_D_I L1_to_L2 0 <-- +IM_D_I L2_to_L1D 0 <-- +IM_D_I L2_to_L1I 0 <-- +IM_D_I L2_Replacement 0 <-- +IM_D_I Other_GETS 1 +IM_D_I Other_GET_INSTR 0 <-- +IM_D_I Other_GETX 0 <-- +IM_D_I Other_PUTX 0 <-- +IM_D_I Data 196 + +IM_D_OI Load 0 <-- +IM_D_OI Ifetch 0 <-- +IM_D_OI Store 0 <-- +IM_D_OI L1_to_L2 0 <-- +IM_D_OI L2_to_L1D 0 <-- +IM_D_OI L2_to_L1I 0 <-- +IM_D_OI L2_Replacement 0 <-- +IM_D_OI Other_GETS 0 <-- +IM_D_OI Other_GET_INSTR 0 <-- +IM_D_OI Other_GETX 0 <-- +IM_D_OI Other_PUTX 0 <-- +IM_D_OI Data 0 <-- + +SM_D Load 0 <-- +SM_D Ifetch 0 <-- +SM_D Store 0 <-- +SM_D L1_to_L2 0 <-- +SM_D L2_to_L1D 0 <-- +SM_D L2_to_L1I 0 <-- +SM_D L2_Replacement 0 <-- +SM_D Other_GETS 7 +SM_D Other_GET_INSTR 0 <-- +SM_D Other_GETX 8 +SM_D Other_PUTX 0 <-- +SM_D Data 7488 + +SM_D_O Load 0 <-- +SM_D_O Ifetch 0 <-- +SM_D_O Store 0 <-- +SM_D_O L1_to_L2 0 <-- +SM_D_O L2_to_L1D 0 <-- +SM_D_O L2_to_L1I 0 <-- +SM_D_O L2_Replacement 0 <-- +SM_D_O Other_GETS 0 <-- +SM_D_O Other_GET_INSTR 0 <-- +SM_D_O Other_GETX 0 <-- +SM_D_O Other_PUTX 0 <-- +SM_D_O Data 7 + + --- Directory --- + - Event Counts - +OtherAddress 0 +GETS 461410 +GET_INSTR 0 +GETX 259859 +PUTX_Owner 0 +PUTX_NotOwner 0 + + - Transitions - +C OtherAddress 0 <-- +C GETS 2027 +C GET_INSTR 0 <-- +C GETX 1045 + +I GETS 0 <-- +I GET_INSTR 0 <-- +I GETX 0 <-- +I PUTX_NotOwner 0 <-- + +S GETS 1318 +S GET_INSTR 0 <-- +S GETX 709 +S PUTX_NotOwner 0 <-- + +SS GETS 2114 +SS GET_INSTR 0 <-- +SS GETX 1318 +SS PUTX_NotOwner 0 <-- + +OS GETS 109458 +OS GET_INSTR 0 <-- +OS GETX 58646 +OS PUTX_Owner 0 <-- +OS PUTX_NotOwner 0 <-- + +OSS GETS 177725 +OSS GET_INSTR 0 <-- +OSS GETX 108100 +OSS PUTX_Owner 0 <-- +OSS PUTX_NotOwner 0 <-- + +M GETS 168768 +M GET_INSTR 0 <-- +M GETX 90041 +M PUTX_Owner 0 <-- +M PUTX_NotOwner 0 <-- + diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr new file mode 100755 index 000000000..328821d4a --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr @@ -0,0 +1,74 @@ +system.cpu7: completed 10000 read accesses @483405 +system.cpu1: completed 10000 read accesses @489648 +system.cpu2: completed 10000 read accesses @489706 +system.cpu5: completed 10000 read accesses @490354 +system.cpu0: completed 10000 read accesses @492776 +system.cpu4: completed 10000 read accesses @495396 +system.cpu6: completed 10000 read accesses @497104 +system.cpu3: completed 10000 read accesses @497952 +system.cpu7: completed 20000 read accesses @923382 +system.cpu5: completed 20000 read accesses @926026 +system.cpu1: completed 20000 read accesses @927265 +system.cpu2: completed 20000 read accesses @930725 +system.cpu3: completed 20000 read accesses @933398 +system.cpu6: completed 20000 read accesses @936538 +system.cpu0: completed 20000 read accesses @938376 +system.cpu4: completed 20000 read accesses @941944 +system.cpu5: completed 30000 read accesses @1362075 +system.cpu1: completed 30000 read accesses @1364620 +system.cpu7: completed 30000 read accesses @1365206 +system.cpu2: completed 30000 read accesses @1372346 +system.cpu3: completed 30000 read accesses @1372730 +system.cpu6: completed 30000 read accesses @1377457 +system.cpu0: completed 30000 read accesses @1377608 +system.cpu4: completed 30000 read accesses @1384598 +system.cpu7: completed 40000 read accesses @1798226 +system.cpu1: completed 40000 read accesses @1802550 +system.cpu5: completed 40000 read accesses @1803508 +system.cpu2: completed 40000 read accesses @1813044 +system.cpu0: completed 40000 read accesses @1813249 +system.cpu6: completed 40000 read accesses @1814460 +system.cpu3: completed 40000 read accesses @1816124 +system.cpu4: completed 40000 read accesses @1829214 +system.cpu7: completed 50000 read accesses @2240501 +system.cpu0: completed 50000 read accesses @2243543 +system.cpu1: completed 50000 read accesses @2245806 +system.cpu5: completed 50000 read accesses @2246126 +system.cpu2: completed 50000 read accesses @2254021 +system.cpu3: completed 50000 read accesses @2256564 +system.cpu6: completed 50000 read accesses @2258894 +system.cpu4: completed 50000 read accesses @2271354 +system.cpu7: completed 60000 read accesses @2684820 +system.cpu5: completed 60000 read accesses @2685946 +system.cpu0: completed 60000 read accesses @2687254 +system.cpu1: completed 60000 read accesses @2688183 +system.cpu6: completed 60000 read accesses @2690040 +system.cpu2: completed 60000 read accesses @2690996 +system.cpu3: completed 60000 read accesses @2703034 +system.cpu4: completed 60000 read accesses @2716020 +system.cpu7: completed 70000 read accesses @3125991 +system.cpu0: completed 70000 read accesses @3129042 +system.cpu1: completed 70000 read accesses @3129110 +system.cpu6: completed 70000 read accesses @3130362 +system.cpu5: completed 70000 read accesses @3131396 +system.cpu2: completed 70000 read accesses @3139286 +system.cpu3: completed 70000 read accesses @3141858 +system.cpu4: completed 70000 read accesses @3162690 +system.cpu0: completed 80000 read accesses @3563564 +system.cpu1: completed 80000 read accesses @3566188 +system.cpu7: completed 80000 read accesses @3566291 +system.cpu6: completed 80000 read accesses @3571624 +system.cpu5: completed 80000 read accesses @3574146 +system.cpu3: completed 80000 read accesses @3580572 +system.cpu2: completed 80000 read accesses @3586246 +system.cpu4: completed 80000 read accesses @3599364 +system.cpu0: completed 90000 read accesses @4000938 +system.cpu7: completed 90000 read accesses @4005441 +system.cpu1: completed 90000 read accesses @4006993 +system.cpu5: completed 90000 read accesses @4009374 +system.cpu6: completed 90000 read accesses @4017392 +system.cpu3: completed 90000 read accesses @4018754 +system.cpu2: completed 90000 read accesses @4031534 +system.cpu4: completed 90000 read accesses @4042150 +system.cpu1: completed 100000 read accesses @4446776 +hack: be nice to actually delete the event here diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout new file mode 100755 index 000000000..02f5b1fde --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -0,0 +1,22 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled May 5 2009 07:34:00 +M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff +M5 started May 5 2009 07:34:03 +M5 executing on piton +command line: /n/piton/z/nate/build/xgem5/build/ALPHA_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby +Global frequency set at 1000000000000 ticks per second +Ruby Timing Mode +Creating event queue... +Creating event queue done +Creating system... + Processors: 8 +Creating system done +Ruby initialization complete +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 4446776 because maximum number of loads reached diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt new file mode 100644 index 000000000..d6d174c7f --- /dev/null +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -0,0 +1,34 @@ + +---------- Begin Simulation Statistics ---------- +host_mem_usage 468884 # Number of bytes of host memory used +host_seconds 600.21 # Real time elapsed on the host +host_tick_rate 7409 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_seconds 0.000004 # Number of seconds simulated +sim_ticks 4446776 # Number of ticks simulated +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu0.num_reads 99923 # number of read accesses completed +system.cpu0.num_writes 53542 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 100000 # number of read accesses completed +system.cpu1.num_writes 53649 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99460 # number of read accesses completed +system.cpu2.num_writes 53552 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99751 # number of read accesses completed +system.cpu3.num_writes 53614 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99278 # number of read accesses completed +system.cpu4.num_writes 53437 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99949 # number of read accesses completed +system.cpu5.num_writes 53857 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 99812 # number of read accesses completed +system.cpu6.num_writes 53539 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 99962 # number of read accesses completed +system.cpu7.num_writes 53947 # number of write accesses completed + +---------- End Simulation Statistics ---------- |