diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt | 940 |
1 files changed, 470 insertions, 470 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 98f92d27e..b9451bcf6 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,170 +1,170 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870336 # Number of seconds simulated -sim_ticks 1870335522500 # Number of ticks simulated -final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.870325 # Number of seconds simulated +sim_ticks 1870325497500 # Number of ticks simulated +final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3051606 # Simulator instruction rate (inst/s) -host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90374561583 # Simulator tick rate (ticks/s) -host_mem_usage 305448 # Number of bytes of host memory used -host_seconds 20.70 # Real time elapsed on the host -sim_insts 63154034 # Number of instructions simulated -sim_ops 63154034 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory +host_inst_rate 2529303 # Simulator instruction rate (inst/s) +host_op_rate 2529302 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74909435310 # Simulator tick rate (ticks/s) +host_mem_usage 298360 # Number of bytes of host memory used +host_seconds 24.97 # Real time elapsed on the host +sim_insts 63151114 # Number of instructions simulated +sim_ops 63151114 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66666560 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory -system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory -system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 111168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 681792 # Number of bytes read from this memory +system.physmem.bytes_read::total 70870016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 760896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 111168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7852480 # Number of bytes written to this memory +system.physmem.bytes_written::total 7852480 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1041665 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 1000626 # number of replacements -system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use -system.l2c.total_refs 2464737 # Total number of references to valid blocks. -system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.312639 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1.inst 1737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10653 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1107344 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122695 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122695 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 406825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35644362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1416652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 364531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37891809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 406825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59438 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4198456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4198456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 406825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35644362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1416652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42090265 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 1000406 # number of replacements +system.l2c.tagsinuse 65381.817479 # Cycle average of tags in use +system.l2c.total_refs 2465974 # Total number of references to valid blocks. +system.l2c.sampled_refs 1065550 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.314273 # Average number of references to valid blocks. system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 56158.126687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4894.240577 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4135.004263 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 174.436812 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 20.009142 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.856905 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.063095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002662 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits -system.l2c.Writeback_hits::total 816653 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # 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number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816811 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816811 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2579 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 612 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3191 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 81 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 193 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281716 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 24162 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305878 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 884613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971544 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 104648 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61969 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3022774 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971544 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 104648 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61969 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3022774 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.016599 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024281 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346467 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.946491 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939542 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945158 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.827160 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.919643 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.880829 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.409214 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.408162 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409130 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.016599 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.173958 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352808 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.016599 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.173958 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352808 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,34 +173,34 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81316 # number of writebacks -system.l2c.writebacks::total 81316 # number of writebacks +system.l2c.writebacks::writebacks 81175 # number of writebacks +system.l2c.writebacks::total 81175 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41695 # number of replacements -system.iocache.tagsinuse 0.435437 # Cycle average of tags in use +system.iocache.replacements 41694 # number of replacements +system.iocache.tagsinuse 0.435353 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.435353 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.027210 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.027210 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -236,22 +236,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154530 # DTB read hits +system.cpu0.dtb.read_hits 9148429 # DTB read hits system.cpu0.dtb.read_misses 7079 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936899 # DTB write hits +system.cpu0.dtb.write_hits 5932048 # DTB write hits system.cpu0.dtb.write_misses 726 # DTB write misses system.cpu0.dtb.write_acv 99 # DTB write access violations system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091429 # DTB hits +system.cpu0.dtb.data_hits 15080477 # DTB hits system.cpu0.dtb.data_misses 7805 # DTB misses system.cpu0.dtb.data_acv 251 # DTB access violations system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855556 # ITB hits +system.cpu0.itb.fetch_hits 3854196 # ITB hits system.cpu0.itb.fetch_misses 3485 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859041 # ITB accesses +system.cpu0.itb.fetch_accesses 3857681 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -264,55 +264,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670933 # number of cpu cycles simulated +system.cpu0.numCycles 3740650883 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222076 # Number of instructions committed -system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399585 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53249924 # number of integer instructions -system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135515 # number of memory refs -system.cpu0.num_load_insts 9184477 # Number of load instructions -system.cpu0.num_store_insts 5951038 # Number of store instructions -system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles -system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles +system.cpu0.committedInsts 57184467 # Number of instructions committed +system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 53214865 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses +system.cpu0.num_func_calls 1398025 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls +system.cpu0.num_int_insts 53214865 # number of integer instructions +system.cpu0.num_fp_insts 299670 # number of float instructions +system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39802131 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written +system.cpu0.num_mem_refs 15124548 # number of memory refs +system.cpu0.num_load_insts 9178366 # Number of load instructions +system.cpu0.num_store_insts 5946182 # Number of store instructions +system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles +system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks::31 17236468500 0.92% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684486 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808659 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed @@ -345,37 +345,37 @@ system.cpu0.kern.syscall::144 2 0.88% 99.12% # nu system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 226 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed +system.cpu0.kern.callpal::wripir 111 0.06% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3760 2.05% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed +system.cpu0.kern.callpal::swpipl 167897 91.68% 93.82% # number of callpals executed +system.cpu0.kern.callpal::rdps 6134 3.35% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.17% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183291 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches +system.cpu0.kern.callpal::total 183136 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7089 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1157 -system.cpu0.kern.mode_good::user 1158 +system.cpu0.kern.mode_good::kernel 1155 +system.cpu0.kern.mode_good::user 1156 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.162928 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1869368290000 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3763 # number of times the context was actually changed +system.cpu0.kern.swap_context 3761 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -407,39 +407,39 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 884404 # number of replacements -system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use -system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. +system.cpu0.icache.replacements 883989 # number of replacements +system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use +system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 884501 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 63.660632 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.244895 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits -system.cpu0.icache.overall_hits::total 56345132 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses -system.cpu0.icache.overall_misses::total 885000 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 56307893 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 56307893 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 56307893 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 56307893 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 56307893 # number of overall hits +system.cpu0.icache.overall_hits::total 56307893 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 884630 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 884630 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 884630 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 884630 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 884630 # number of overall misses +system.cpu0.icache.overall_misses::total 884630 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 57192523 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 57192523 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 57192523 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57192523 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 57192523 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015468 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015468 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015468 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015468 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015468 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,63 +449,63 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1978686 # number of replacements -system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1978242 # number of replacements +system.cpu0.dcache.tagsinuse 507.129590 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13113201 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1978754 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 6.626999 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses +system.cpu0.dcache.occ_blocks::cpu0.data 507.129590 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.990487 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7292600 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7292600 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5457787 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5457787 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 171977 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 171977 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186443 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 186443 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12750387 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12750387 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12750387 # number of overall hits +system.cpu0.dcache.overall_hits::total 12750387 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683130 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1683130 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285798 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 285798 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16152 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16152 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 726 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 726 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1968928 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1968928 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1968928 # number of overall misses +system.cpu0.dcache.overall_misses::total 1968928 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8975730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5743585 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 188129 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14719315 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14719315 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.187520 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049760 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085856 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003879 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133765 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.133765 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133765 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.133765 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -514,29 +514,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks -system.cpu0.dcache.writebacks::total 775641 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 775494 # number of writebacks +system.cpu0.dcache.writebacks::total 775494 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1163439 # DTB read hits +system.cpu1.dtb.read_hits 1169160 # DTB read hits system.cpu1.dtb.read_misses 3277 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 751446 # DTB write hits +system.cpu1.dtb.write_hits 755883 # DTB write hits system.cpu1.dtb.write_misses 415 # DTB write misses system.cpu1.dtb.write_acv 58 # DTB write access violations system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1914885 # DTB hits +system.cpu1.dtb.data_hits 1925043 # DTB hits system.cpu1.dtb.data_misses 3692 # DTB misses system.cpu1.dtb.data_acv 116 # DTB access violations system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1468399 # ITB hits +system.cpu1.itb.fetch_hits 1469677 # ITB hits system.cpu1.itb.fetch_misses 1539 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_accesses 1471216 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -549,51 +549,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248881 # number of cpu cycles simulated +system.cpu1.numCycles 3740237218 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931958 # Number of instructions committed -system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses -system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550578 # number of integer instructions -system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written -system.cpu1.num_mem_refs 1926244 # number of memory refs -system.cpu1.num_load_insts 1170888 # Number of load instructions -system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles -system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles +system.cpu1.committedInsts 5966647 # Number of instructions committed +system.cpu1.committedOps 5966647 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 5582916 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 28730 # Number of float alu accesses +system.cpu1.num_func_calls 184190 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 581489 # number of instructions that are conditional controls +system.cpu1.num_int_insts 5582916 # number of integer instructions +system.cpu1.num_fp_insts 28730 # number of float instructions +system.cpu1.num_int_register_reads 7700123 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4186358 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 17955 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 17751 # number of times the floating registers were written +system.cpu1.num_mem_refs 1936419 # number of memory refs +system.cpu1.num_load_insts 1176619 # Number of load instructions +system.cpu1.num_store_insts 759800 # Number of store instructions +system.cpu1.num_idle_cycles 3734265828.606121 # Number of idle cycles +system.cpu1.num_busy_cycles 5971389.393879 # Number of busy cycles +system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl +system.cpu1.kern.inst.quiesce 2208 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 39691 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 10388 33.53% 33.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1907 6.15% 39.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 111 0.36% 40.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 18579 59.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 30985 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 10378 45.79% 45.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1907 8.41% 54.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 111 0.49% 54.70% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 22663 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1859112376500 99.41% 99.41% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks::30 14176500 0.00% 99.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 10910041500 0.58% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1870118595500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.552613 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.731418 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed @@ -616,67 +616,67 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed +system.cpu1.kern.callpal::swpctx 472 1.46% 1.50% # number of callpals executed system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed +system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed +system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32131 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches +system.cpu1.kern.callpal::total 32267 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 612 +system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 613 system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 32 -system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 33 +system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.replacements 103091 # number of replacements -system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use -system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits -system.cpu1.icache.overall_hits::total 5832136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses -system.cpu1.icache.overall_misses::total 103630 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses +system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 473 # number of times the context was actually changed +system.cpu1.icache.replacements 104103 # number of replacements +system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use +system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits +system.cpu1.icache.overall_hits::total 5865807 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses +system.cpu1.icache.overall_misses::total 104648 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5970455 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -686,63 +686,63 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 62044 # number of replacements -system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses -system.cpu1.dcache.overall_misses::total 67292 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses +system.cpu1.dcache.replacements 62444 # number of replacements +system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits +system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses +system.cpu1.dcache.overall_misses::total 67742 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -751,8 +751,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks -system.cpu1.dcache.writebacks::total 41012 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks +system.cpu1.dcache.writebacks::total 41317 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |