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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | |
parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 066f6fce7..01a06923f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1630624 # Simulator instruction rate (inst/s) -host_op_rate 1630623 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49684114233 # Simulator tick rate (ticks/s) -host_mem_usage 305868 # Number of bytes of host memory used -host_seconds 36.82 # Real time elapsed on the host +host_inst_rate 1538182 # Simulator instruction rate (inst/s) +host_op_rate 1538181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46867449524 # Simulator tick rate (ticks/s) +host_mem_usage 350908 # Number of bytes of host memory used +host_seconds 39.03 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory @@ -129,7 +129,7 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664408 # number of cpu cycles simulated +system.cpu.numCycles 3658664517 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60038305 # Number of instructions committed @@ -147,8 +147,8 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 16115709 # number of memory refs system.cpu.num_load_insts 9747513 # Number of load instructions system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles -system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles +system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles +system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983585 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed |