diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt | 481 |
1 files changed, 286 insertions, 195 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 8a7bfd4c1..d02473de7 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,58 +1,90 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332049000 # Number of ticks simulated -final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829331993500 # Number of ticks simulated +final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2314619 # Simulator instruction rate (inst/s) -host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70524837278 # Simulator tick rate (ticks/s) -host_mem_usage 315304 # Number of bytes of host memory used -host_seconds 25.94 # Real time elapsed on the host -sim_insts 60038433 # Number of instructions simulated -sim_ops 60038433 # Number of ops (including micro ops) simulated +host_inst_rate 2920462 # Simulator instruction rate (inst/s) +host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88984410684 # Simulator tick rate (ticks/s) +host_mem_usage 366200 # Number of bytes of host memory used +host_seconds 20.56 # Real time elapsed on the host +sim_insts 60038469 # Number of instructions simulated +sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory +system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory +system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 41099809 # Throughput (bytes/s) -system.membus.data_through_bus 75185198 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 948404 # Transaction distribution +system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::WriteReq 9838 # Transaction distribution +system.membus.trans_dist::WriteResp 9838 # Transaction distribution +system.membus.trans_dist::Writeback 74279 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 116985 # Transaction distribution +system.membus.trans_dist::ReadExResp 116985 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1174168 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1174168 # Request fanout histogram system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -108,15 +140,15 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710428 # DTB read hits +system.cpu.dtb.read_hits 9710423 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352498 # DTB write hits +system.cpu.dtb.write_hits 6352496 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062926 # DTB hits +system.cpu.dtb.data_hits 16062919 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses @@ -136,32 +168,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664099 # number of cpu cycles simulated +system.cpu.numCycles 3658670345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038433 # Number of instructions committed -system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses +system.cpu.committedInsts 60038469 # Number of instructions committed +system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913650 # number of integer instructions +system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913692 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115710 # number of memory refs -system.cpu.num_load_insts 9747514 # Number of load instructions -system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles -system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles -system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983585 # Percentage of idle cycles -system.cpu.Branches 9064413 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction +system.cpu.num_mem_refs 16115703 # number of memory refs +system.cpu.num_load_insts 9747509 # Number of load instructions +system.cpu.num_store_insts 6368194 # Number of store instructions +system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles +system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles +system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983587 # Percentage of idle cycles +system.cpu.Branches 9064428 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction @@ -189,11 +221,11 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction -system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050271 # Class of executed instruction +system.cpu.op_class::total 60050307 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed @@ -207,11 +239,11 @@ system.cpu.kern.ipl_good::21 243 0.16% 49.46% # nu system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -275,9 +307,9 @@ system.cpu.kern.mode_switch_good::kernel 0.320726 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -310,15 +342,50 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1480181 # Throughput (bytes/s) -system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.tags.replacements 919591 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor +system.iobus.trans_dist::ReadReq 7358 # Transaction distribution +system.iobus.trans_dist::ReadResp 7358 # Transaction distribution +system.iobus.trans_dist::WriteReq 51390 # Transaction distribution +system.iobus.trans_dist::WriteResp 9838 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) +system.cpu.icache.tags.replacements 919603 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -326,26 +393,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits -system.cpu.icache.overall_hits::total 59130053 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses -system.cpu.icache.overall_misses::total 920218 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits +system.cpu.icache.overall_hits::total 59130077 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses +system.cpu.icache.overall_misses::total 920230 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -361,17 +428,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992295 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992289 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id @@ -381,64 +448,64 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,14 +514,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks -system.cpu.l2cache.writebacks::total 74285 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks +system.cpu.l2cache.writebacks::total 74279 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042683 # number of replacements +system.cpu.dcache.tags.replacements 2042707 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -464,52 +531,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits -system.cpu.dcache.overall_hits::total 13656011 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses -system.cpu.dcache.overall_misses::total 2026051 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits +system.cpu.dcache.overall_hits::total 13655981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,11 +585,35 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks -system.cpu.dcache.writebacks::total 833475 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks +system.cpu.dcache.writebacks::total 833484 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41883 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram ---------- End Simulation Statistics ---------- |