Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.

1 files changed, 226 insertions, 226 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index a50f49017..cf5c30619 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -1,132 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.829332                       # Number of seconds simulated
-sim_ticks                                1829332258000                       # Number of ticks simulated
-final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.829331                       # Number of seconds simulated
+sim_ticks                                1829330593000                       # Number of ticks simulated
+final_tick                               1829330593000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2962809                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2962806                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            90274916526                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302384                       # Number of bytes of host memory used
-host_seconds                                    20.26                       # Real time elapsed on the host
-sim_insts                                    60038305                       # Number of instructions simulated
-sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          66839424                       # Number of bytes read from this memory
+host_inst_rate                                2569577                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2569575                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            78294086451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295292                       # Number of bytes of host memory used
+host_seconds                                    23.37                       # Real time elapsed on the host
+sim_insts                                    60037737                       # Number of instructions simulated
+sim_ops                                      60037737                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            857856                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          66839296                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             70349696                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          857984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7411392                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7411392                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13406                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1044366                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             70349440                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       857856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          857856                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7411136                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7411136                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13404                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1044364                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1099214                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115803                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115803                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               469015                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             36537607                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1449867                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                38456489                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             469015                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4051419                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4051419                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4051419                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              469015                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            36537607                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1449867                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42507908                       # Total bandwidth to/from this memory (bytes/s)
-system.cpu.l2cache.replacements                        992301                       # number of replacements
-system.cpu.l2cache.tagsinuse                     65424.374305                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                         2433239                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                       1057464                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                          2.301014                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle                     614754000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks        56309.122439                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst           4867.329747                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data           4247.922119                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks           0.859209                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst             0.074270                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data             0.064818                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total                0.998297                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst              906797                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data              811229                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total                1718026                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks          833491                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total               833491                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data                4                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total                   4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data            187229                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total               187229                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst               906797                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data               998458                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total                 1905255                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst              906797                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data              998458                       # number of overall hits
-system.cpu.l2cache.overall_hits::total                1905255                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst             13406                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data            927640                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total               941046                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data             12                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total                12                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          117117                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total             117117                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst              13406                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data            1044757                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total               1058163                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst             13406                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data           1044757                       # number of overall misses
-system.cpu.l2cache.overall_misses::total              1058163                       # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          920203                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data         1738869                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total            2659072                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       833491                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total           833491                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total              16                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        304346                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total           304346                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst           920203                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          2043215                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total             2963418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          920203                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2043215                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total            2963418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst       0.014569                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data       0.533473                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total          0.353900                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total       0.750000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384815                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total        0.384815                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst        0.014569                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data        0.511330                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total           0.357075                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst       0.014569                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data       0.511330                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total          0.357075                       # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets                      0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                              0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                             0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks               74291                       # number of writebacks
-system.cpu.l2cache.writebacks::total                    74291                       # number of writebacks
-system.cpu.l2cache.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.physmem.num_reads::total               1099210                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115799                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115799                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               468945                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36537571                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1449868                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                38456384                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          468945                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             468945                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4051283                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4051283                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4051283                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              468945                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            36537571                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1449868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42507667                       # Total bandwidth to/from this memory (bytes/s)
 system.iocache.replacements                     41686                       # number of replacements
-system.iocache.tagsinuse                     1.225570                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.225558                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.225570                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.076598                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.076598                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1685780599067                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.225558                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.076597                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.076597                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -178,22 +98,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9710427                       # DTB read hits
+system.cpu.dtb.read_hits                      9710417                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
-system.cpu.dtb.write_hits                     6352498                       # DTB write hits
+system.cpu.dtb.write_hits                     6352487                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     16062925                       # DTB hits
+system.cpu.dtb.data_hits                     16062904                       # DTB hits
 system.cpu.dtb.data_misses                      11471                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
 system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.itb.fetch_hits                     4974648                       # ITB hits
+system.cpu.itb.fetch_hits                     4974615                       # ITB hits
 system.cpu.itb.fetch_misses                      5006                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4979654                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4979621                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -206,51 +126,51 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3658664408                       # number of cpu cycles simulated
+system.cpu.numCycles                       3658661078                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60038305                       # Number of instructions committed
-system.cpu.committedOps                      60038305                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
+system.cpu.committedInsts                    60037737                       # Number of instructions committed
+system.cpu.committedOps                      60037737                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              55912968                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7110746                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     55913521                       # number of integer instructions
+system.cpu.num_func_calls                     1484174                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7110641                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     55912968                       # number of integer instructions
 system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            76953934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           41740225                       # number of times the integer registers were written
+system.cpu.num_int_register_reads            76953007                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           41739788                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      16115709                       # number of memory refs
-system.cpu.num_load_insts                     9747513                       # Number of load instructions
-system.cpu.num_store_insts                    6368196                       # Number of store instructions
-system.cpu.num_idle_cycles               3598608979.180807                       # Number of idle cycles
-system.cpu.num_busy_cycles               60055428.819193                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.016415                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.983585                       # Percentage of idle cycles
+system.cpu.num_mem_refs                      16115688                       # number of memory refs
+system.cpu.num_load_insts                     9747503                       # Number of load instructions
+system.cpu.num_store_insts                    6368185                       # Number of store instructions
+system.cpu.num_idle_cycles               3598606247.544791                       # Number of idle cycles
+system.cpu.num_busy_cycles               60054830.455209                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.016414                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.983586                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211319                       # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei                     211316                       # number of hwrei instructions executed
 system.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105623     57.86%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182562                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105620     57.86%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182559                       # number of times we switched to this ipl
 system.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1811927407500     99.05%     99.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0             1811925911500     99.05%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
 system.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             17304295000      0.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1829332050500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             17304126000      0.95%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1829330385500                       # number of cycles we spent at this ipl
 system.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.695521                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.816353                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.695541                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.816366                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -289,7 +209,7 @@ system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # nu
 system.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175249     91.19%     93.40% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175246     91.19%     93.40% # number of callpals executed
 system.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
@@ -298,20 +218,20 @@ system.cpu.kern.callpal::whami                      2      0.00%     96.93% # nu
 system.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192180                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1909                      
-system.cpu.kern.mode_good::user                  1738                      
+system.cpu.kern.callpal::total                 192177                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5948                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1735                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2098                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1906                      
+system.cpu.kern.mode_good::user                  1735                      
 system.cpu.kern.mode_good::idle                   171                      
-system.cpu.kern.mode_switch_good::kernel     0.320894                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.320444                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.390229                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        26834202500      1.47%      1.47% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           1465074000      0.08%      1.55% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1801032773000     98.45%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.081506                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.389735                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        26832734500      1.47%      1.47% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           1465059000      0.08%      1.55% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1801032591000     98.45%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
@@ -344,33 +264,33 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                 919594                       # number of replacements
-system.cpu.icache.tagsinuse                511.215243                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59129922                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 920106                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  64.264250                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                 919577                       # number of replacements
+system.cpu.icache.tagsinuse                511.215229                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 59129371                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 920089                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  64.264839                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.215243                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     511.215229                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     59129922                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        59129922                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      59129922                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         59129922                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     59129922                       # number of overall hits
-system.cpu.icache.overall_hits::total        59129922                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       920221                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        920221                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       920221                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         920221                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       920221                       # number of overall misses
-system.cpu.icache.overall_misses::total        920221                       # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     60050143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     59129371                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        59129371                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      59129371                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         59129371                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     59129371                       # number of overall hits
+system.cpu.icache.overall_hits::total        59129371                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       920204                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        920204                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       920204                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         920204                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       920204                       # number of overall misses
+system.cpu.icache.overall_misses::total        920204                       # number of overall misses
+system.cpu.icache.ReadReq_accesses::cpu.inst     60049575                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     60049575                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     60049575                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     60049575                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60049575                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     60049575                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
@@ -386,55 +306,55 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2042702                       # number of replacements
+system.cpu.dcache.replacements                2042708                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14038431                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2043214                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   6.870759                       # Average number of references to valid blocks.
+system.cpu.dcache.total_refs                 14038404                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2043220                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.870726                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7807780                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807780                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848212                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848212                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655992                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655992                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655992                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655992                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721707                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721707                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304362                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
+system.cpu.dcache.ReadReq_hits::cpu.data      7807768                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807768                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848199                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848199                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199281                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13655967                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655967                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13655967                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655967                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1721710                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721710                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304365                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304365                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026069                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026069                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026069                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026069                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_misses::cpu.data      2026075                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026075                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2026075                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026075                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data      9529478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9529478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152564                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152564                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200302                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200302                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199281                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199281                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15682042                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15682042                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15682042                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15682042                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085681                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085681                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
@@ -450,5 +370,85 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
 system.cpu.dcache.writebacks::total            833491                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.l2cache.replacements                992297                       # number of replacements
+system.cpu.l2cache.tagsinuse             65424.375500                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 2433229                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs               1057460                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  2.301013                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle             614754000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 56309.097195                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   4867.351144                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   4247.927161                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.859209                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.074270                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.998297                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst       906782                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       811232                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1718014                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       833491                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       833491                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       187234                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       187234                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       906782                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       998466                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1905248                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       906782                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       998466                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1905248                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        13404                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       927640                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       941044                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           12                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           12                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       117115                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       117115                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        13404                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1044755                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1058159                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        13404                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1044755                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1058159                       # number of overall misses
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       920186                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1738872                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      2659058                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       833491                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       833491                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       304349                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       304349                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       920186                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2043221                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2963407                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       920186                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2043221                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2963407                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.014567                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.533472                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.353901                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.750000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.750000                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384805                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.384805                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.014567                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.511327                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.357075                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.014567                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.511327                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.357075                       # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks        74287                       # number of writebacks
+system.cpu.l2cache.writebacks::total            74287                       # number of writebacks
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------