stats: Update stats for regressions using SimpleDDR3

This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.

1 files changed, 67 insertions, 3 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 2435d9264..178493c15 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -187,7 +187,7 @@ system.physmem.avgRdBW                           0.00                       # Av
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MB/s
 system.physmem.avgConsumedRdBW                   0.00                       # Average consumed read bandwidth in MB/s
 system.physmem.avgConsumedWrBW                   0.00                       # Average consumed write bandwidth in MB/s
-system.physmem.peakBW                        16000.00                       # Theoretical peak bandwidth in MB/s
+system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MB/s
 system.physmem.busUtil                           0.00                       # Data bus utilization in percentage
 system.physmem.avgRdQLen                         0.00                       # Average read queue length over time
 system.physmem.avgWrQLen                         0.00                       # Average write queue length over time
@@ -302,8 +302,8 @@ system.cpu.num_fp_register_writes              166520                       # nu
 system.cpu.num_mem_refs                      16115688                       # number of memory refs
 system.cpu.num_load_insts                     9747503                       # Number of load instructions
 system.cpu.num_store_insts                    6368185                       # Number of store instructions
-system.cpu.num_idle_cycles               3598606250.520791                       # Number of idle cycles
-system.cpu.num_busy_cycles               60054827.479209                       # Number of busy cycles
+system.cpu.num_idle_cycles               3598606249.772791                       # Number of idle cycles
+system.cpu.num_busy_cycles               60054828.227209                       # Number of busy cycles
 system.cpu.not_idle_fraction                 0.016414                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.983586                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
@@ -608,5 +608,69 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
 system.cpu.dcache.writebacks::total            833491                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2042707                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14038405                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2043219                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.870729                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7807769                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807769                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848199                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848199                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199281                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13655968                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13655968                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1721709                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721709                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304365                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304365                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data      9529478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9529478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152564                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152564                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200302                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200302                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199281                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199281                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15682042                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15682042                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15682042                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15682042                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085681                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085681                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
+system.cpu.dcache.writebacks::total            833491                       # number of writebacks
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------