stats: Update stats to reflect SimpleDRAM changes

This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.

1 files changed, 12 insertions, 91 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 178493c15..2e73db07d 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829331                       # Nu
 sim_ticks                                1829330593000                       # Number of ticks simulated
 final_tick                               1829330593000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1133415                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1133413                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            34534714924                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 347332                       # Number of bytes of host memory used
-host_seconds                                    52.97                       # Real time elapsed on the host
+host_inst_rate                                3233953                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3233951                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            98537371937                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303612                       # Number of bytes of host memory used
+host_seconds                                    18.56                       # Real time elapsed on the host
 sim_insts                                    60037737                       # Number of instructions simulated
 sim_ops                                      60037737                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            857856                       # Number of bytes read from this memory
@@ -89,26 +89,13 @@ system.physmem.readPktSize::3                       0                       # Ca
 system.physmem.readPktSize::4                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::5                       0                       # Categorize read packet sizes
 system.physmem.readPktSize::6                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::7                       0                       # Categorize read packet sizes
-system.physmem.readPktSize::8                       0                       # Categorize read packet sizes
-system.physmem.writePktSize::0                      0                       # categorize write packet sizes
-system.physmem.writePktSize::1                      0                       # categorize write packet sizes
-system.physmem.writePktSize::2                      0                       # categorize write packet sizes
-system.physmem.writePktSize::3                      0                       # categorize write packet sizes
-system.physmem.writePktSize::4                      0                       # categorize write packet sizes
-system.physmem.writePktSize::5                      0                       # categorize write packet sizes
-system.physmem.writePktSize::6                      0                       # categorize write packet sizes
-system.physmem.writePktSize::7                      0                       # categorize write packet sizes
-system.physmem.writePktSize::8                      0                       # categorize write packet sizes
-system.physmem.neitherpktsize::0                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::1                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::2                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::3                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::4                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::5                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::6                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::7                    0                       # categorize neither packet sizes
-system.physmem.neitherpktsize::8                    0                       # categorize neither packet sizes
+system.physmem.writePktSize::0                      0                       # Categorize write packet sizes
+system.physmem.writePktSize::1                      0                       # Categorize write packet sizes
+system.physmem.writePktSize::2                      0                       # Categorize write packet sizes
+system.physmem.writePktSize::3                      0                       # Categorize write packet sizes
+system.physmem.writePktSize::4                      0                       # Categorize write packet sizes
+system.physmem.writePktSize::5                      0                       # Categorize write packet sizes
+system.physmem.writePktSize::6                      0                       # Categorize write packet sizes
 system.physmem.rdQLenPdf::0                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                         0                       # What read queue length does an incoming req see
@@ -141,7 +128,6 @@ system.physmem.rdQLenPdf::28                        0                       # Wh
 system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32                        0                       # What read queue length does an incoming req see
 system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
@@ -174,7 +160,6 @@ system.physmem.wrQLenPdf::28                        0                       # Wh
 system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
 system.physmem.totQLat                              0                       # Total cycles spent in queuing delays
 system.physmem.totMemAccLat                         0                       # Sum of mem lat for all requests
 system.physmem.totBusLat                            0                       # Total cycles spent in databus access
@@ -608,69 +593,5 @@ system.cpu.dcache.cache_copies                      0                       # nu
 system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
 system.cpu.dcache.writebacks::total            833491                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2042707                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14038405                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2043219                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   6.870729                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7807769                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807769                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848199                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848199                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199281                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655968                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655968                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655968                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721709                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721709                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304365                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304365                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529478                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529478                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152564                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152564                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200302                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200302                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199281                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199281                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682042                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682042                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682042                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682042                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085681                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085681                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
-system.cpu.dcache.writebacks::total            833491                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------