regressions: update stats due to branch predictor changes

The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

3 files changed, 216 insertions, 183 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 29a31b8cf..50088b4ab 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -8,17 +8,19 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
 init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
+mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -34,22 +36,21 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
+clock=1000
 delay=50000
-nack_delay=4000
 ranges=8796093022208:18446744073709551615
 req_size=16
 resp_size=16
-write_ack=false
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
 checker=Null
 clock=500
 cpu_id=0
-defer_registration=false
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
@@ -58,17 +59,18 @@ fastmem=false
 function_trace=false
 function_trace_start=0
 interrupts=system.cpu.interrupts
+isa=system.cpu.isa
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
-phase=0
 profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
+switched_out=false
 system=system
 tracer=system.cpu.tracer
 width=1
@@ -81,25 +83,22 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=4
 block_size=64
+clock=500
 forward_snoops=true
-hash_delay=1
+hit_latency=2
 is_top_level=true
-latency=1000
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
 size=32768
-subblock_size=0
 system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
 
 [system.cpu.dtb]
 type=AlphaTLB
@@ -110,33 +109,65 @@ type=BaseCache
 addr_ranges=0:18446744073709551615
 assoc=1
 block_size=64
+clock=500
 forward_snoops=true
-hash_delay=1
+hit_latency=2
 is_top_level=true
-latency=1000
 max_miss_count=0
 mshrs=4
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
 size=32768
-subblock_size=0
 system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
 
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
+[system.cpu.isa]
+type=AlphaISA
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
 
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
 [system.cpu.tracer]
 type=ExeTracer
 
@@ -157,7 +188,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -177,7 +208,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -197,52 +228,24 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
 assoc=8
 block_size=64
+clock=1000
 forward_snoops=false
-hash_delay=1
+hit_latency=50
 is_top_level=true
-latency=50000
 max_miss_count=0
 mshrs=20
 prefetch_on_access=false
 prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
 size=1024
-subblock_size=0
 system=system
 tgts_per_mshr=12
-trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
 [system.membus]
@@ -255,13 +258,14 @@ use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
 master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=0
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=true
 ret_data16=65535
@@ -274,14 +278,28 @@ warn_access=
 pio=system.membus.default
 
 [system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
 conf_table_reported=false
-file=
 in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
 null=false
+page_policy=open
 range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
 zero=false
 port=system.membus.master[1]
 
@@ -293,7 +311,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -303,16 +321,6 @@ number=0
 output=true
 port=3456
 
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
 [system.tsunami]
 type=Tsunami
 children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
@@ -321,10 +329,11 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
+clock=1000
 cpu=system.cpu
 disk=system.simple_disk
 pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
 platform=system.tsunami
 system=system
 terminal=system.terminal
@@ -332,8 +341,9 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
+clock=1000
 pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[0]
@@ -378,7 +388,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=0
+clock=2000
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -389,12 +399,10 @@ dma_write_delay=0
 dma_write_factor=0
 hardware_address=00:90:00:00:00:01
 intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
 pci_bus=0
 pci_dev=1
 pci_func=0
-pio_latency=1000
+pio_latency=30000
 platform=system.tsunami
 rss=false
 rx_delay=1000000
@@ -411,9 +419,10 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
 pio_size=393216
 ret_bad_addr=false
 ret_data16=65535
@@ -427,9 +436,10 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -443,9 +453,10 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -459,9 +470,10 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -475,9 +487,10 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -491,9 +504,10 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -507,9 +521,10 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -523,9 +538,10 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -539,9 +555,10 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -555,9 +572,10 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -571,9 +589,10 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -587,9 +606,10 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -603,9 +623,10 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -619,9 +640,10 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -635,9 +657,10 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -651,9 +674,10 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -667,9 +691,10 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -683,9 +708,10 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -699,9 +725,10 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
+clock=1000
 fake_mem=false
 pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
 pio_size=8
 ret_bad_addr=false
 ret_data16=65535
@@ -715,9 +742,10 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
+clock=1000
 devicename=FrameBuffer
 pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
 system=system
 pio=system.iobus.master[21]
 
@@ -761,16 +789,15 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
+clock=1000
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
 io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
 pci_bus=0
 pci_dev=0
 pci_func=0
-pio_latency=1000
+pio_latency=30000
 platform=system.tsunami
 system=system
 config=system.iobus.master[26]
@@ -779,9 +806,10 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
+clock=1000
 frequency=976562500
 pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
 system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
@@ -790,8 +818,9 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
+clock=1000
 pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
 system=system
 tsunami=system.tsunami
 pio=system.iobus.master[1]
@@ -799,7 +828,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
 platform=system.tsunami
 size=16777216
 system=system
@@ -807,8 +837,9 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
+clock=1000
 pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
 platform=system.tsunami
 system=system
 terminal=system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index ed03a48be..c4aa2f920 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:39:53
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:01:49
+gem5 executing on ribera.cs.wisc.edu
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1829332258000 because m5_exit instruction encountered
+Exiting @ tick 1829330593000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 99b74717c..2435d9264 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829331                       # Nu
 sim_ticks                                1829330593000                       # Number of ticks simulated
 final_tick                               1829330593000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1577718                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1577717                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            48072530632                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294780                       # Number of bytes of host memory used
-host_seconds                                    38.05                       # Real time elapsed on the host
+host_inst_rate                                1133415                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1133413                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            34534714924                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347332                       # Number of bytes of host memory used
+host_seconds                                    52.97                       # Real time elapsed on the host
 sim_insts                                    60037737                       # Number of instructions simulated
 sim_ops                                      60037737                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            857856                       # Number of bytes read from this memory
@@ -464,70 +464,6 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2042707                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14038405                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2043219                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   6.870729                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7807769                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7807769                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5848199                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5848199                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199281                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13655968                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13655968                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13655968                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13655968                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1721709                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1721709                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304365                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304365                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data      9529478                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9529478                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6152564                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6152564                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200302                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200302                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199281                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199281                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15682042                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15682042                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15682042                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15682042                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085681                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085681                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
-system.cpu.dcache.writebacks::total            833491                       # number of writebacks
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                992297                       # number of replacements
 system.cpu.l2cache.tagsinuse             65424.375500                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 2433228                       # Total number of references to valid blocks.
@@ -608,5 +544,69 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks::writebacks        74287                       # number of writebacks
 system.cpu.l2cache.writebacks::total            74287                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.dcache.replacements                2042707                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14038405                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2043219                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.870729                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7807769                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7807769                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848199                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5848199                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183140                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199281                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199281                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13655968                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13655968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13655968                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13655968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1721709                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1721709                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304365                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304365                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data      9529478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9529478                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152564                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6152564                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200302                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200302                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199281                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199281                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15682042                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15682042                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15682042                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15682042                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049470                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085681                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085681                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks       833491                       # number of writebacks
+system.cpu.dcache.writebacks::total            833491                       # number of writebacks
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------