diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 1702 |
1 files changed, 851 insertions, 851 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e92359043..9611b47c5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.958647 # Number of seconds simulated -sim_ticks 1958647095000 # Number of ticks simulated -final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.957578 # Number of seconds simulated +sim_ticks 1957577582000 # Number of ticks simulated +final_tick 1957577582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1245422 # Simulator instruction rate (inst/s) -host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41097010927 # Simulator tick rate (ticks/s) -host_mem_usage 295412 # Number of bytes of host memory used -host_seconds 47.66 # Real time elapsed on the host -sim_insts 59355643 # Number of instructions simulated -sim_ops 59355643 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory +host_inst_rate 1866861 # Simulator instruction rate (inst/s) +host_op_rate 1866860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61595044213 # Simulator tick rate (ticks/s) +host_mem_usage 296940 # Number of bytes of host memory used +host_seconds 31.78 # Real time elapsed on the host +sim_insts 59331415 # Number of instructions simulated +sim_ops 59331415 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 825984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24749824 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory -system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory -system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 37440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 398080 # Number of bytes read from this memory +system.physmem.bytes_read::total 28662144 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 825984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 37440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7684736 # Number of bytes written to this memory +system.physmem.bytes_written::total 7684736 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386716 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory -system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13254145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1353391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 239153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20618183 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 393576 # number of replacements -system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use -system.l2c.total_refs 2371449 # Total number of references to valid blocks. -system.l2c.sampled_refs 427769 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.543761 # Average number of references to valid blocks. -system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7139.593108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 100.838318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 99.145617 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.357359 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056890 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.108942 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001539 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.001513 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.526242 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 901389 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 758006 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86187 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33004 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816294 # number of Writeback hits -system.l2c.Writeback_hits::total 816294 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 53 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 170288 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12569 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 182857 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 901389 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 928294 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86187 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 45573 # number of demand (read+write) hits -system.l2c.demand_hits::total 1961443 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 901389 # number of overall hits -system.l2c.overall_hits::cpu0.data 928294 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86187 # number of overall hits -system.l2c.overall_hits::cpu1.data 45573 # number of overall hits -system.l2c.overall_hits::total 1961443 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 14371 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 288456 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 815 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1138 # number of ReadReq misses -system.l2c.ReadReq_misses::total 304780 # number of ReadReq misses +system.physmem.num_reads::cpu1.inst 585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6220 # Number of read requests responded to by this memory +system.physmem.num_reads::total 447846 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120074 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120074 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 421942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12643087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1354131 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 203353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14641639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 421942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441068 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3925635 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3925635 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3925635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 421942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12643087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1354131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 203353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18567274 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 340832 # number of replacements +system.l2c.tagsinuse 65295.945000 # Cycle average of tags in use +system.l2c.total_refs 2492123 # Total number of references to valid blocks. +system.l2c.sampled_refs 405944 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.139081 # Average number of references to valid blocks. +system.l2c.warmup_cycle 7739998000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55466.932424 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4795.907583 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4852.495880 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 163.850290 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 16.758824 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.846358 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073180 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.074043 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002500 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000256 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.996337 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 902441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 771400 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86210 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 33732 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1793783 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 821051 # number of Writeback hits +system.l2c.Writeback_hits::total 821051 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 34 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 172323 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 12709 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 185032 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 902441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 943723 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 86210 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 46441 # number of demand (read+write) hits +system.l2c.demand_hits::total 1978815 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 902441 # number of overall hits +system.l2c.overall_hits::cpu0.data 943723 # number of overall hits +system.l2c.overall_hits::cpu1.inst 86210 # number of overall hits +system.l2c.overall_hits::cpu1.data 46441 # number of overall hits +system.l2c.overall_hits::total 1978815 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 12906 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271613 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 596 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 192 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285307 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 2453 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 495 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2948 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 15 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 74 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 89 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117546 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6196 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123742 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 14371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 406002 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 815 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 7334 # number of demand (read+write) misses -system.l2c.demand_misses::total 428522 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 14371 # number of overall misses -system.l2c.overall_misses::cpu0.data 406002 # number of overall misses -system.l2c.overall_misses::cpu1.inst 815 # number of overall misses -system.l2c.overall_misses::cpu1.data 7334 # number of overall misses -system.l2c.overall_misses::total 428522 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 747344500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 15004707000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 42364500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 59224000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 15853640000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2244000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 780000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3024000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 104000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 312000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 416000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6112681000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 322197000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6434878000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 747344500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 21117388000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 42364500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 381421000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22288518000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 747344500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 21117388000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 42364500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 381421000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22288518000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915760 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1046462 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 87002 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 34142 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2083366 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816294 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816294 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2625 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 548 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3173 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 33 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 93 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 126 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 287834 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18765 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306599 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915760 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1334296 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 87002 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 52907 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2389965 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915760 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1334296 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 87002 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 52907 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2389965 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.146292 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.929089 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.706349 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.403596 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.179301 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.179301 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52016.667760 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1025.780190 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4674.157303 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52002.375911 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52012.540780 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52012.540780 # average overall miss latency +system.l2c.UpgradeReq_misses::cpu1.data 486 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2939 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 16 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 72 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 88 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115483 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6047 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 121530 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 12906 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387096 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 596 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6239 # number of demand (read+write) misses +system.l2c.demand_misses::total 406837 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12906 # number of overall misses +system.l2c.overall_misses::cpu0.data 387096 # number of overall misses +system.l2c.overall_misses::cpu1.inst 596 # number of overall misses +system.l2c.overall_misses::cpu1.data 6239 # number of overall misses +system.l2c.overall_misses::total 406837 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 671157500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 14128859000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 30971000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 10024000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 14841011500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2088000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 624000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 2712000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 260000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 468000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6005389000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 314450000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6319839000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 671157500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 20134248000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 30971000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 324474000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21160850500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 671157500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 20134248000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 30971000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 324474000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21160850500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 915347 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1043013 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 86806 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 33924 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2079090 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 821051 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 821051 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2619 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 540 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3159 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 30 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 122 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 287806 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18756 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 306562 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 915347 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1330819 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 86806 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 52680 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2385652 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 915347 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1330819 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 86806 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 52680 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2385652 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014100 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.260412 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.006866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.005660 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.137227 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.936617 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.900000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.930358 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.533333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.782609 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.721311 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.401253 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.322403 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.396429 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014100 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.290871 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.006866 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.118432 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.170535 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014100 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.290871 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.006866 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.118432 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.170535 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.525492 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.345955 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51964.765101 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52208.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52017.691469 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 851.202609 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1283.950617 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 922.762845 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16250 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2888.888889 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5318.181818 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.363984 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.992228 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52002.295729 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52013.092467 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52013.092467 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,119 +221,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 119935 # number of writebacks -system.l2c.writebacks::total 119935 # number of writebacks +system.l2c.writebacks::writebacks 78554 # number of writebacks +system.l2c.writebacks::total 78554 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 14371 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 288456 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 804 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1138 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 304769 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 12906 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271613 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 585 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 192 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285296 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 2453 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 495 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2948 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 15 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 74 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 89 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 117546 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6196 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123742 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 14371 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 406002 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 804 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 7334 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 428511 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 14371 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 406002 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 804 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 7334 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 428511 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574888000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11543235000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 32164000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 45568000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 12195855000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 98181000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19800000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 117981000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2960000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 3560000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4702129000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 247845000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4949974000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 574888000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 16245364000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 32164000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 293413000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17145829000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 574888000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 16245364000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 32164000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 293413000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17145829000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 792100000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_misses::cpu1.data 486 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2939 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 16 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 72 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 88 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115483 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6047 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 121530 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12906 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387096 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 585 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6239 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 406826 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12906 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387096 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 585 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6239 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 406826 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 516282000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10869503000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 23400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 7720000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 11416905000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 98186000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19446000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117632000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 640000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2880000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 3520000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4619593000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 241886000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4861479000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 516282000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 15489096000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 23400000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 249606000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16278384000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 516282000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15489096000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 23400000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 249606000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16278384000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 792098000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 10214500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 802314500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1122200000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 269211500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1391411500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914300000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279426000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 2193726000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.146287 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.929089 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706349 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.403596 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.179296 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.179296 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_mshr_uncacheable_latency::total 802312500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1122098500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 269224500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1391323000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914196500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279439000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2193635500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.260412 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005660 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.137222 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.936617 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.900000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930358 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.533333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.782609 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.721311 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401253 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.322403 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.396429 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290871 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.118432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170530 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290871 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.118432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170530 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.345955 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40208.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.753491 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.905830 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40012.345679 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40024.498129 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.363984 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.992228 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.295729 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.563721 # Cycle average of tags in use +system.iocache.tagsinuse 0.563379 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.563721 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035233 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035233 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1750565168000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.563379 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035211 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035211 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41726 # system.iocache.overall_misses::total 41726 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20052998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20052998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 5721783806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 5721783806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5741836804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5741836804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5741836804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5741836804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5719883806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5719883806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5739936804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5739936804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5739936804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5739936804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 137656.040768 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 137562.594162 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6179.373554 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726 system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3559028000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3570032998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3570032998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3570032998 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8633623 # DTB read hits +system.cpu0.dtb.read_hits 8630502 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 6044743 # DTB write hits +system.cpu0.dtb.write_hits 6043026 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14678366 # DTB hits +system.cpu0.dtb.data_hits 14673528 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3853057 # ITB hits +system.cpu0.itb.fetch_hits 3852973 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3856928 # ITB accesses +system.cpu0.itb.fetch_accesses 3856844 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3916023774 # number of cpu cycles simulated +system.cpu0.numCycles 3914070794 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54072652 # Number of instructions committed -system.cpu0.committedOps 54072652 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses +system.cpu0.committedInsts 54051547 # Number of instructions committed +system.cpu0.committedOps 54051547 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50023130 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses -system.cpu0.num_func_calls 1426863 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6237040 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50043234 # number of integer instructions +system.cpu0.num_func_calls 1426247 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6235141 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50023130 # number of integer instructions system.cpu0.num_fp_insts 293967 # number of float instructions -system.cpu0.num_int_register_reads 68528072 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37080372 # number of times the integer registers were written +system.cpu0.num_int_register_reads 68498295 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37064173 # number of times the integer registers were written system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written -system.cpu0.num_mem_refs 14724357 # number of memory refs -system.cpu0.num_load_insts 8664914 # Number of load instructions -system.cpu0.num_store_insts 6059443 # Number of store instructions -system.cpu0.num_idle_cycles 3680034047.555842 # Number of idle cycles -system.cpu0.num_busy_cycles 235989726.444158 # Number of busy cycles -system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.939737 # Percentage of idle cycles +system.cpu0.num_mem_refs 14719518 # number of memory refs +system.cpu0.num_load_insts 8661793 # Number of load instructions +system.cpu0.num_store_insts 6057725 # Number of store instructions +system.cpu0.num_idle_cycles 3679914036.735006 # Number of idle cycles +system.cpu0.num_busy_cycles 234156757.264994 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059824 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940176 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202972 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72739 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6362 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202969 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72743 40.62% 40.62% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.10% 41.80% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104211 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179062 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71372 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::31 104206 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179060 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71376 49.27% 49.27% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.36% 50.73% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71366 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144850 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899667899000 97.02% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 79058000 0.00% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565985500 0.03% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::31 71370 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144857 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898820258500 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 78970000 0.00% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 565865000 0.03% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 4687500 0.00% 97.06% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 57565586000 2.94% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1957035367000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981208 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684893 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808986 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -567,28 +567,28 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # nu system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172198 91.50% 93.64% # number of callpals executed -system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172198 91.50% 93.65% # number of callpals executed +system.cpu0.kern.callpal::rdps 6677 3.55% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4750 2.52% 99.73% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188203 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches +system.cpu0.kern.callpal::total 188201 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7301 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175729 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298928 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1953310949000 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3370111000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3895 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -622,51 +622,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 915147 # number of replacements -system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use -system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.800486 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53165471 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53165471 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53165471 # number of overall hits -system.cpu0.icache.overall_hits::total 53165471 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915781 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915781 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915781 # number of overall misses -system.cpu0.icache.overall_misses::total 915781 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13429132500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency +system.cpu0.icache.replacements 914734 # number of replacements +system.cpu0.icache.tagsinuse 508.814250 # Cycle average of tags in use +system.cpu0.icache.total_refs 53144779 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915246 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.066114 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 35914239000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.814250 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993778 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53144779 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53144779 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53144779 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53144779 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53144779 # number of overall hits +system.cpu0.icache.overall_hits::total 53144779 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915368 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915368 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915368 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915368 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915368 # number of overall misses +system.cpu0.icache.overall_misses::total 915368 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13361799000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13361799000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13361799000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13361799000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54060147 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54060147 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54060147 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54060147 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54060147 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016932 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016932 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016932 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016932 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016932 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14597.188235 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -677,112 +677,112 @@ system.cpu0.icache.fast_writes 0 # nu system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks::writebacks 55 # number of writebacks system.cpu0.icache.writebacks::total 55 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915368 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915368 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915368 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915368 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915368 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10614998000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10614998000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10614998000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016932 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016932 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016932 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1338438 # number of replacements -system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 1337419 # number of replacements +system.cpu0.dcache.tagsinuse 506.341163 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13344261 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1337832 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.974542 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7421006 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5560133 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176505 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191674 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12981139 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12981139 # number of overall hits -system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1036101 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291536 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16544 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 410 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1327637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1327637 # number of overall misses -system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9109954000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9109954000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234949000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 234949000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2973000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2973000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 35680233500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 35680233500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 35680233500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 35680233500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.122512 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049821 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002134 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.092785 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 506.341163 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.988948 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7419012 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7419012 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5558431 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5558431 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 176349 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191666 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191666 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12977443 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12977443 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12977443 # number of overall hits +system.cpu0.dcache.overall_hits::total 12977443 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1034980 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1034980 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291529 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291529 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16694 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16694 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 411 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 411 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326509 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326509 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326509 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326509 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 25827814500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9022984000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 234039000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2995000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34850798500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34850798500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34850798500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8453992 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5849960 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 193043 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14303952 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14303952 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122425 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049834 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086478 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092737 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092737 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092737 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092737 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7287.104623 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,62 +791,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks -system.cpu0.dcache.writebacks::total 786441 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1327637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327637 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1327637 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23461938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23461938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8235346000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8235346000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31697284500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 790358 # number of writebacks +system.cpu0.dcache.writebacks::total 790358 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1034980 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291529 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16694 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 411 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326509 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326509 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326509 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22722836500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8148397000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183957000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1762000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30871233500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30871233500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30871233500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1241998500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122425 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049834 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086478 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092737 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092737 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4287.104623 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -858,22 +858,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1050117 # DTB read hits +system.cpu1.dtb.read_hits 1049963 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 651208 # DTB write hits +system.cpu1.dtb.write_hits 651106 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1701325 # DTB hits +system.cpu1.dtb.data_hits 1701069 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1493438 # ITB hits +system.cpu1.itb.fetch_hits 1493400 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1494654 # ITB accesses +system.cpu1.itb.fetch_accesses 1494616 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -886,51 +886,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3917294190 # number of cpu cycles simulated +system.cpu1.numCycles 3915155164 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5282991 # Number of instructions committed -system.cpu1.committedOps 5282991 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses +system.cpu1.committedInsts 5279868 # Number of instructions committed +system.cpu1.committedOps 5279868 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4945263 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 158031 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 510974 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4948310 # number of integer instructions +system.cpu1.num_func_calls 157997 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 510441 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4945263 # number of integer instructions system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6886066 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3732878 # number of times the integer registers were written +system.cpu1.num_int_register_reads 6880916 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3730475 # number of times the integer registers were written system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1710778 # number of memory refs -system.cpu1.num_load_insts 1056124 # Number of load instructions -system.cpu1.num_store_insts 654654 # Number of store instructions -system.cpu1.num_idle_cycles 3898237020.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 19057169.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995135 # Percentage of idle cycles +system.cpu1.num_mem_refs 1710522 # number of memory refs +system.cpu1.num_load_insts 1055970 # Number of load instructions +system.cpu1.num_store_insts 654552 # Number of store instructions +system.cpu1.num_idle_cycles 3896226886.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 18928277.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004835 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995165 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2318 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36191 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9289 32.15% 32.15% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2314 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 36187 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9288 32.15% 32.15% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.30% 39.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17551 60.74% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28897 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9279 45.20% 45.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::30 88 0.30% 39.27% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17548 60.73% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28893 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9278 45.20% 45.20% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.43% 55.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9191 44.78% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20527 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917878582000 97.92% 97.92% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good::30 88 0.43% 55.23% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9190 44.77% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20525 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917614123000 97.96% 97.96% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 507941000 0.03% 97.98% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 53691000 0.00% 97.99% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 39401069000 2.01% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1957576824000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.523706 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.710380 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -952,7 +952,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # nu system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24309 82.25% 83.46% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24305 82.25% 83.46% # number of callpals executed system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed @@ -961,66 +961,66 @@ system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # nu system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29554 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 804 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 477 -system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.callpal::total 29550 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 476 +system.cpu1.kern.mode_good::user 463 system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.592777 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.285800 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3531821000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1727088000 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1952317913000 99.73% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86457 # number of replacements -system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use -system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.807616 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5199349 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5199349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5199349 # number of overall hits -system.cpu1.icache.overall_hits::total 5199349 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 87005 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 87005 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 87005 # number of overall misses -system.cpu1.icache.overall_misses::total 87005 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1260607500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.016458 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.016458 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14488.908683 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14488.908683 # average overall miss latency +system.cpu1.icache.replacements 86261 # number of replacements +system.cpu1.icache.tagsinuse 419.419440 # Cycle average of tags in use +system.cpu1.icache.total_refs 5196422 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 86773 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.885241 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1941709468000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 419.419440 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819179 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819179 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5196422 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5196422 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5196422 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5196422 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5196422 # number of overall hits +system.cpu1.icache.overall_hits::total 5196422 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 86809 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 86809 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 86809 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 86809 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 86809 # number of overall misses +system.cpu1.icache.overall_misses::total 86809 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1248608500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1248608500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1248608500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1248608500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1248608500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1248608500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5283231 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5283231 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5283231 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5283231 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5283231 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5283231 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016431 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016431 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016431 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016431 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016431 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016431 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14383.399187 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14383.399187 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14383.399187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14383.399187 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1031,112 +1031,112 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 14 # number of writebacks system.cpu1.icache.writebacks::total 14 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 87005 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11488.517901 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86809 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 86809 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 86809 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 86809 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 86809 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 86809 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 988145500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 988145500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 988145500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 988145500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 988145500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 988145500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016431 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016431 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016431 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11382.984483 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11382.984483 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11382.984483 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 52960 # number of replacements -system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use -system.cpu1.dcache.total_refs 1644934 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 389.521271 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.760784 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.760784 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1003161 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1003161 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 616899 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 616899 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11784 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11784 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11526 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11526 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1620060 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1620060 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1620060 # number of overall hits -system.cpu1.dcache.overall_hits::total 1620060 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 37113 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 37113 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 20421 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 20421 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 982 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 982 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 505 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 505 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 57534 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 57534 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 57534 # number of overall misses -system.cpu1.dcache.overall_misses::total 57534 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 533263000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 533263000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 556796000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 556796000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13079000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 13079000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6416000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6416000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1090059000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 1090059000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 1090059000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 1090059000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040274 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1040274 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 637320 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 637320 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12766 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12031 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1677594 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035676 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.032042 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.041975 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.034296 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034296 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14368.630938 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27265.853778 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13318.737271 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12704.950495 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18946.344770 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18946.344770 # average overall miss latency +system.cpu1.dcache.replacements 52782 # number of replacements +system.cpu1.dcache.tagsinuse 416.168626 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1644833 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53294 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.863380 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1922770151000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 416.168626 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.812829 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.812829 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1003125 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1003125 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 616808 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 616808 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11818 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 11818 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11519 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11519 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1619933 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1619933 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1619933 # number of overall hits +system.cpu1.dcache.overall_hits::total 1619933 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 36999 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 36999 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 20414 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 20414 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 944 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 944 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 507 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 57413 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 57413 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 57413 # number of overall misses +system.cpu1.dcache.overall_misses::total 57413 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 492506000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 492506000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 549958000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 549958000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 11305000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 11305000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6352000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6352000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1042464000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1042464000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1042464000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1042464000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040124 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1040124 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 637222 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 637222 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 12762 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 12026 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 1677346 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1677346 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035572 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.073970 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042159 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034228 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034228 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26940.237092 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11975.635593 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11975.635593 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12528.599606 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12528.599606 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18157.281452 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18157.281452 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,62 +1145,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks -system.cpu1.dcache.writebacks::total 29784 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 982 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 982 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 505 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 505 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 57534 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 57534 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 57534 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 57534 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 421922000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 421922000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 495533000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 495533000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 10133000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 10133000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4901000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4901000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 917455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 917455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 917455000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 917455000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11413500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11413500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 30624 # number of writebacks +system.cpu1.dcache.writebacks::total 30624 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 36999 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20414 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 944 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57413 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57413 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57413 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 381507000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 488716000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8473000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4831000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 870223000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 870223000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11412500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298066500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309479000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035572 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032036 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073970 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034228 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034228 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8975.635593 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9528.599606 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |