diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-25 13:14:42 -0400 |
| commit | 8fe556338db4cc50a3f1ba20306bc5e464941f2b (patch) | |
| tree | d95b1933c18d142f9c533f32ac7b84bd1f2d0da5 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | |
| parent | 66e331c7bb7d503c35808325e1bfaa9f18f4bdb9 (diff) | |
| download | gem5-8fe556338db4cc50a3f1ba20306bc5e464941f2b.tar.xz | |
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 1986 |
1 files changed, 1072 insertions, 914 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index ba361e6db..e568ced30 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,376 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.955746 # Number of seconds simulated -sim_ticks 1955746240500 # Number of ticks simulated -final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.950813 # Number of seconds simulated +sim_ticks 1950813247500 # Number of ticks simulated +final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1240365 # Simulator instruction rate (inst/s) -host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39831169965 # Simulator tick rate (ticks/s) -host_mem_usage 291792 # Number of bytes of host memory used -host_seconds 49.10 # Real time elapsed on the host -sim_insts 60902973 # Number of instructions simulated -sim_ops 60902973 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory +host_inst_rate 1287440 # Simulator instruction rate (inst/s) +host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41184614921 # Simulator tick rate (ticks/s) +host_mem_usage 325660 # Number of bytes of host memory used +host_seconds 47.37 # Real time elapsed on the host +sim_insts 60982794 # Number of instructions simulated +sim_ops 60982794 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory -system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory +system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory +system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448143 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12643014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1355431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 17998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 224193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14665068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 17998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3936642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3936642 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3936642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12643014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 17998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 224193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18601710 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 341281 # number of replacements -system.l2c.tagsinuse 65229.882617 # Cycle average of tags in use -system.l2c.total_refs 2441318 # Total number of references to valid blocks. -system.l2c.sampled_refs 406256 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.009309 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7648586000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55341.365970 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4865.877793 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4868.452553 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.161458 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 38.024844 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.844442 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.074247 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074287 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001772 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000580 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995329 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 685804 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664321 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 316190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 108937 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1775252 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 793334 # number of Writeback hits -system.l2c.Writeback_hits::total 793334 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 732 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126580 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47318 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173898 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 685804 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 316190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156255 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949150 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 685804 # number of overall hits -system.l2c.overall_hits::cpu0.data 790901 # number of overall hits -system.l2c.overall_hits::cpu1.inst 316190 # number of overall hits -system.l2c.overall_hits::cpu1.data 156255 # number of overall hits -system.l2c.overall_hits::total 1949150 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12970 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271621 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 244 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285396 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2948 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1741 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4689 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 895 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1787 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115480 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6627 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122107 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12970 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387101 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6871 # number of demand (read+write) misses -system.l2c.demand_misses::total 407503 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12970 # number of overall misses -system.l2c.overall_misses::cpu0.data 387101 # number of overall misses -system.l2c.overall_misses::cpu1.inst 561 # number of overall misses -system.l2c.overall_misses::cpu1.data 6871 # number of overall misses -system.l2c.overall_misses::total 407503 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 679344500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14131444000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 29382500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 12805500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14852976500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2720000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 22059498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24779498 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2047000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 521500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2568500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6014286500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 347569000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6361855500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 679344500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20145730500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 29382500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 360374500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21214832000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 679344500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20145730500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 29382500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 360374500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21214832000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 698774 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 935942 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 316751 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 109181 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2060648 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 793334 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 793334 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3131 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2290 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5421 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 927 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1844 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 242060 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 53945 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296005 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 698774 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1178002 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 316751 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 163126 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2356653 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 698774 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1178002 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 316751 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 163126 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2356653 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018561 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.290211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.001771 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002235 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138498 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941552 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760262 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.864970 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.962244 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976009 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969089 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.477072 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.122847 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.412517 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.328608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.001771 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.042121 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.172916 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.328608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.001771 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.042121 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.172916 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52378.141866 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52026.330807 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52375.222816 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52481.557377 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52043.394091 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 922.659430 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12670.590465 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5284.601834 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2294.843049 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.681564 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1437.325126 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52080.762903 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52447.412102 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52100.661715 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52060.554155 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52060.554155 # average overall miss latency +system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448189 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120412 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1358859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3950336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3950336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12675575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1358859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 448189 # Total number of read requests seen +system.physmem.writeReqs 120412 # Total number of write requests seen +system.physmem.cpureqs 599134 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28684096 # Total number of bytes read from memory +system.physmem.bytesWritten 7706368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28684096 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7706368 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27647 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7157 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 522 # Number of times wr buffer was full causing retry +system.physmem.totGap 1950759532000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 448189 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 120934 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 7172 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 409832 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1753 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 4346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2865774804 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests +system.physmem.totBusLat 1792528000 # Total cycles spent in databus access +system.physmem.totBankLat 6289598000 # Total cycles spent in bank access +system.physmem.avgQLat 6394.93 # Average queueing delay per request +system.physmem.avgBankLat 14035.15 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 24430.08 # Average memory access latency +system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgWrQLen 10.50 # Average write queue length over time +system.physmem.readRowHits 428033 # Number of row buffer hits during reads +system.physmem.writeRowHits 76777 # Number of row buffer hits during writes +system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes +system.physmem.avgGap 3430805.67 # Average gap between requests +system.l2c.replacements 341333 # number of replacements +system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use +system.l2c.total_refs 2438074 # Total number of references to valid blocks. +system.l2c.sampled_refs 406309 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.000541 # Average number of references to valid blocks. +system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 55545.297156 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4807.218464 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4686.690338 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 164.376104 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.847554 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 674220 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 658221 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 328583 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 113537 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774561 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 791464 # number of Writeback hits +system.l2c.Writeback_hits::total 791464 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 123896 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48958 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172854 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 674220 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 782117 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 328583 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 162495 # number of demand (read+write) hits +system.l2c.demand_hits::total 1947415 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 674220 # number of overall hits +system.l2c.overall_hits::cpu0.data 782117 # number of overall hits +system.l2c.overall_hits::cpu1.inst 328583 # number of overall hits +system.l2c.overall_hits::cpu1.data 162495 # number of overall hits +system.l2c.overall_hits::total 1947415 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2967 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4774 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1881 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115504 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6643 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122147 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387135 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6890 # number of demand (read+write) misses +system.l2c.demand_misses::total 407563 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses +system.l2c.overall_misses::cpu0.data 387135 # number of overall misses +system.l2c.overall_misses::cpu1.inst 612 # number of overall misses +system.l2c.overall_misses::cpu1.data 6890 # number of overall misses +system.l2c.overall_misses::total 407563 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 713316000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11504038499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 34128500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 15210000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 12266692999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 10405497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11649997 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 841000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 205500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1046500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5694760500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 427293500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6122054000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 713316000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 17198798999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 34128500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 442503500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 18388746999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 713316000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 17198798999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 34128500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 442503500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 18388746999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 687146 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 929852 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 329195 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 113784 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2059977 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 791464 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 791464 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3143 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2374 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5517 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 965 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1940 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 239400 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 55601 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295001 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 687146 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1169252 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 329195 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 169385 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2354978 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 687146 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1169252 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 329195 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 169385 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2354978 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018811 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.292123 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138553 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944003 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.761163 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.865325 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976166 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969588 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.482473 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.119476 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.414056 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018811 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.331096 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001859 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.040677 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173064 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018811 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.331096 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.040677 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173064 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55184.589200 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 42351.714270 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55765.522876 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 61578.947368 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 42978.294836 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 419.447253 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5758.437742 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2440.301005 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 895.633653 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 218.152866 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 556.353004 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49303.578231 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64322.369411 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50120.379543 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55184.589200 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 44425.843695 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 55765.522876 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 64224.020319 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 45118.784087 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55184.589200 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 44425.843695 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 55765.522876 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 64224.020319 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 45118.784087 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -221,119 +379,119 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 78778 # number of writebacks -system.l2c.writebacks::total 78778 # number of writebacks +system.l2c.writebacks::writebacks 78892 # number of writebacks +system.l2c.writebacks::total 78892 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12970 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271621 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 244 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285385 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2948 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1741 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4689 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 895 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1787 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 115480 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 6627 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122107 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12970 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387101 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6871 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407492 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12970 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387101 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6871 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407492 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 519097000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10870382000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 22042500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9816500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 11421338000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 117985500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 69640998 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 187626498 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 35714975 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 35800000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 71514975 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4619582000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 265544000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4885126000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 519097000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15489964000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 22042500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 275360500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16306464000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 519097000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15489964000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 22042500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 275360500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16306464000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370272000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18137500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1388409500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2141921500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673752500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2815674000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3512193500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691890000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4204083500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290211 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002235 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138493 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941552 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760262 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.864970 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.962244 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976009 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969089 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477072 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122847 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.412517 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328608 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.042121 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172911 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328608 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.042121 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172911 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40020.403430 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40231.557377 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.806980 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40022.218453 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000.573234 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40014.181702 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40039.209641 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40019.571908 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.307932 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40070.016599 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40006.928350 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.303500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40075.753165 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40016.648180 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.303500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40075.753165 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40016.648180 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 12926 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271631 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 601 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 247 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285405 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2967 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1807 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4774 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 939 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 942 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1881 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115504 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6643 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122147 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12926 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387135 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 601 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6890 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407552 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12926 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387135 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 601 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6890 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407552 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 549819387 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7975375490 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25997165 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12059975 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 8563252017 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29825962 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18084304 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47910266 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9405923 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9420942 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 18826865 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4202676375 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343429954 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4546106329 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 549819387 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12178051865 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 25997165 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 355489929 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 13109358346 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 549819387 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12178051865 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 25997165 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 355489929 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 13109358346 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370389500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18130000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1388519500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2151186500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 682990000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2834176500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3521576000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701120000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4222696000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292123 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138548 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944003 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.761163 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.865325 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976166 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969588 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482473 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.414056 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173060 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173060 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29361.065158 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48825.809717 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 30003.861239 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.565554 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10007.915883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.665270 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.965976 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36385.548336 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51698.021075 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37218.321604 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +503,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.569930 # Cycle average of tags in use +system.iocache.tagsinuse 0.562945 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1749614950000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.569930 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035621 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.562945 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -361,14 +519,14 @@ system.iocache.demand_misses::tsunami.ide 41728 # n system.iocache.demand_misses::total 41728 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 11453563806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 11453563806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 11474577804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 11474577804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 11474577804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 11474577804 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 9455401806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 9455401806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9476670804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9476670804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9476670804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9476670804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -385,19 +543,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275644.103918 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 275644.103918 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 274985.089245 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 274985.089245 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 199825 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 227555.877118 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 227555.877118 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227105.799559 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227105.799559 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 186741 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 24712 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23044 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.086152 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.103671 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -411,14 +569,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41728 system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11861998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9292859806 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 9292859806 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 9304721804 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9304721804 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 9304721804 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9304721804 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7292629022 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7292629022 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 7304745022 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 7304745022 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 7304745022 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 7304745022 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +585,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67397.715909 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67397.715909 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223644.103918 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 223644.103918 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175506.089286 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 175506.089286 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +610,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7486542 # DTB read hits +system.cpu0.dtb.read_hits 7424678 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5063820 # DTB write hits +system.cpu0.dtb.write_hits 5011102 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12550362 # DTB hits +system.cpu0.dtb.data_hits 12435780 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3500956 # ITB hits +system.cpu0.itb.fetch_hits 3481701 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3504827 # ITB accesses +system.cpu0.itb.fetch_accesses 3485572 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +638,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3910167080 # number of cpu cycles simulated +system.cpu0.numCycles 3900399022 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47719039 # Number of instructions committed -system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses -system.cpu0.num_func_calls 1200899 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44257119 # number of integer instructions -system.cpu0.num_fp_insts 210954 # number of float instructions -system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written -system.cpu0.num_mem_refs 12590587 # number of memory refs -system.cpu0.num_load_insts 7513713 # Number of load instructions -system.cpu0.num_store_insts 5076874 # Number of store instructions -system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles -system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles -system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles +system.cpu0.committedInsts 47350752 # Number of instructions committed +system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43919757 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses +system.cpu0.num_func_calls 1188579 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43919757 # number of integer instructions +system.cpu0.num_fp_insts 206365 # number of float instructions +system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written +system.cpu0.num_mem_refs 12475681 # number of memory refs +system.cpu0.num_load_insts 7451619 # Number of load instructions +system.cpu0.num_store_insts 5024062 # Number of store instructions +system.cpu0.num_idle_cycles 3698907701.219057 # Number of idle cycles +system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93050500 0.00% 97.36% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 759970000 0.04% 97.40% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1950199481000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -560,37 +718,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed -system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed +system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed +system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149688 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches +system.cpu0.kern.callpal::total 147588 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1285 -system.cpu0.kern.mode_good::user 1285 +system.cpu0.kern.mode_good::kernel 1283 +system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1946498286500 99.83% 99.83% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3408187000 0.17% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3071 # number of times the context was actually changed +system.cpu0.kern.swap_context 3025 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -622,51 +780,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 698187 # number of replacements -system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use -system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47028847 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47028847 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47028847 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47028847 # number of overall hits -system.cpu0.icache.overall_hits::total 47028847 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses -system.cpu0.icache.overall_misses::total 698792 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9694162500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9694162500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9694162500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9694162500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9694162500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9694162500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47727639 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47727639 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47727639 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47727639 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47727639 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47727639 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014641 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014641 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014641 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014641 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014641 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014641 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13872.743964 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13872.743964 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency +system.cpu0.icache.replacements 686559 # number of replacements +system.cpu0.icache.tagsinuse 509.179293 # Cycle average of tags in use +system.cpu0.icache.total_refs 46672188 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 687071 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.179293 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 46672188 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46672188 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46672188 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46672188 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46672188 # number of overall hits +system.cpu0.icache.overall_hits::total 46672188 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687164 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687164 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687164 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687164 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687164 # number of overall misses +system.cpu0.icache.overall_misses::total 687164 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9577778500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9577778500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9577778500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9577778500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9577778500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9577778500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359352 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47359352 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47359352 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47359352 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47359352 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47359352 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014510 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014510 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014510 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014510 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014510 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014510 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13938.126124 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13938.126124 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13938.126124 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13938.126124 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,112 +833,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8296578500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8296578500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8296578500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8296578500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8296578500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8296578500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014641 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11872.743964 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687164 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687164 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687164 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687164 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687164 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687164 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8203450500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8203450500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8203450500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8203450500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8203450500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8203450500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014510 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014510 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014510 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11938.126124 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1180402 # number of replacements -system.cpu0.dcache.tagsinuse 505.183019 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11360683 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1180820 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.621012 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 99461000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 505.183019 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.986686 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.986686 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6406782 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6406782 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4655760 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4655760 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140286 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140286 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147915 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147915 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11062542 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11062542 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11062542 # number of overall hits -system.cpu0.dcache.overall_hits::total 11062542 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938249 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938249 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251643 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251643 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13638 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13638 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5458 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5458 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1189892 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1189892 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1189892 # number of overall misses -system.cpu0.dcache.overall_misses::total 1189892 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23522563000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 23522563000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8201327000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8201327000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 147906000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 147906000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 67796500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 67796500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 31723890000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 31723890000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 31723890000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 31723890000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7345031 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7345031 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4907403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4907403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153924 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 153924 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153373 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153373 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12252434 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12252434 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12252434 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12252434 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127739 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127739 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051278 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051278 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088602 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088602 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035586 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035586 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097115 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097115 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097115 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097115 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25070.704046 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25070.704046 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32591.119165 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 32591.119165 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10845.138583 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10845.138583 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12421.491389 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12421.491389 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26661.150760 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26661.150760 # average overall miss latency +system.cpu0.dcache.replacements 1171741 # number of replacements +system.cpu0.dcache.tagsinuse 505.264481 # Cycle average of tags in use +system.cpu0.dcache.total_refs 11253752 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1172158 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.600883 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 505.264481 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6351991 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6351991 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4607363 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4607363 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138394 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138394 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10959354 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10959354 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10959354 # number of overall hits +system.cpu0.dcache.overall_hits::total 10959354 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 933040 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 933040 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249280 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249280 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13436 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13436 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1182320 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1182320 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1182320 # number of overall misses +system.cpu0.dcache.overall_misses::total 1182320 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20820883000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 20820883000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7761604000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7761604000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144502500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 144502500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43447000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 43447000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 28582487000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 28582487000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 28582487000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 28582487000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7285031 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856643 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4856643 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 151830 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12141674 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12141674 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12141674 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12141674 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051328 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051328 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088494 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088494 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097377 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097377 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097377 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097377 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22315.102246 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 22315.102246 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31136.087933 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 31136.087933 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10754.874963 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10754.874963 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7581.050427 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7581.050427 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24174.916266 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24174.916266 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,62 +947,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks -system.cpu0.dcache.writebacks::total 679069 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938249 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938249 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251643 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251643 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13638 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13638 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5458 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189892 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1189892 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189892 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7698041000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 120630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29344106000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 29344106000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2275733500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 672349 # number of writebacks +system.cpu0.dcache.writebacks::total 672349 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933040 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 933040 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249280 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249280 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13436 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13436 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182320 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1182320 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182320 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1182320 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18954803000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18954803000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7263044000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7263044000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117630500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31985000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31985000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26217847000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 26217847000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26217847000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26217847000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465453500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465453500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285524000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285524000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -856,22 +1014,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2425080 # DTB read hits +system.cpu1.dtb.read_hits 2500235 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1761000 # DTB write hits +system.cpu1.dtb.write_hits 1820988 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4186080 # DTB hits +system.cpu1.dtb.data_hits 4321223 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1964871 # ITB hits +system.cpu1.itb.fetch_hits 1990033 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1966087 # ITB accesses +system.cpu1.itb.fetch_accesses 1991249 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -884,51 +1042,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3911492481 # number of cpu cycles simulated +system.cpu1.numCycles 3901626495 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13183934 # Number of instructions committed -system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses -system.cpu1.num_func_calls 412685 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12160396 # number of integer instructions -system.cpu1.num_fp_insts 172922 # number of float instructions -system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written -system.cpu1.num_mem_refs 4209624 # number of memory refs -system.cpu1.num_load_insts 2439377 # Number of load instructions -system.cpu1.num_store_insts 1770247 # Number of store instructions -system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles +system.cpu1.committedInsts 13632042 # Number of instructions committed +system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses +system.cpu1.num_func_calls 426717 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12571491 # number of integer instructions +system.cpu1.num_fp_insts 180459 # number of float instructions +system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written +system.cpu1.num_mem_refs 4345531 # number of memory refs +system.cpu1.num_load_insts 2514982 # Number of load instructions +system.cpu1.num_store_insts 1830549 # Number of store instructions +system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles +system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -944,81 +1102,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed -system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed -system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed +system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed +system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71584 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 891 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 427 -system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73828 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches +system.cpu1.kern.mode_switch::user 465 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 915 +system.cpu1.kern.mode_good::user 465 +system.cpu1.kern.mode_good::idle 450 +system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1996 # number of times the context was actually changed -system.cpu1.icache.replacements 316204 # number of replacements -system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use -system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits -system.cpu1.icache.overall_hits::total 12870545 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses -system.cpu1.icache.overall_misses::total 316752 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4179857000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13187297 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13187297 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13187297 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13187297 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13187297 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13187297 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024019 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024019 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024019 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024019 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024019 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024019 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13195.992448 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.153899 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 18665784500 0.96% 0.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1711228500 0.09% 1.04% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1930435473000 98.96% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2086 # number of times the context was actually changed +system.cpu1.icache.replacements 328648 # number of replacements +system.cpu1.icache.tagsinuse 446.257828 # Cycle average of tags in use +system.cpu1.icache.total_refs 13306209 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 329160 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 40.424745 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1948917036000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 446.257828 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 13306209 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13306209 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13306209 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13306209 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13306209 # number of overall hits +system.cpu1.icache.overall_hits::total 13306209 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 329196 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 329196 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 329196 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 329196 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 329196 # number of overall misses +system.cpu1.icache.overall_misses::total 329196 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4347354500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4347354500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4347354500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4347354500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4347354500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4347354500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635405 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13635405 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13635405 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13635405 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13635405 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13635405 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024143 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024143 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024143 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024143 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024143 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024143 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13205.976075 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13205.976075 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13205.976075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13205.976075 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1027,112 +1185,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316752 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316752 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316752 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3546353000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3546353000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329196 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 329196 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 329196 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 329196 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 329196 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 329196 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688962500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688962500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3688962500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688962500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3688962500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024143 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024143 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11205.976075 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 166318 # number of replacements -system.cpu1.dcache.tagsinuse 487.121043 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4017452 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 166830 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.081113 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 63885131000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.121043 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951408 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951408 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2260833 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2260833 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1643465 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1643465 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48243 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48243 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50839 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50839 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3904298 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3904298 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3904298 # number of overall hits -system.cpu1.dcache.overall_hits::total 3904298 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118301 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118301 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62725 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62725 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8915 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8915 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5846 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5846 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 181026 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 181026 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 181026 # number of overall misses -system.cpu1.dcache.overall_misses::total 181026 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440550500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1440550500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1113565500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1113565500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81445500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81445500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 69062000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 69062000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2554116000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2554116000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2554116000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2554116000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2379134 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2379134 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1706190 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1706190 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56685 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56685 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4085324 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4085324 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4085324 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4085324 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049724 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049724 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036763 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036763 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155971 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155971 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103131 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103131 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044311 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044311 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044311 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044311 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12176.993432 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12176.993432 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17753.136708 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17753.136708 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.782389 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.782389 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11813.547725 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11813.547725 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14109.111398 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14109.111398 # average overall miss latency +system.cpu1.dcache.replacements 172786 # number of replacements +system.cpu1.dcache.tagsinuse 487.450805 # Cycle average of tags in use +system.cpu1.dcache.total_refs 4146223 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 173298 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 23.925394 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 62292634000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.450805 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 2329094 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2329094 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1699243 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1699243 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4028337 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4028337 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4028337 # number of overall hits +system.cpu1.dcache.overall_hits::total 4028337 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123236 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123236 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 64754 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 64754 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9347 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9347 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6143 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6143 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 187990 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 187990 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 187990 # number of overall misses +system.cpu1.dcache.overall_misses::total 187990 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1493692000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1493692000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166299500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1166299500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85390000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 85390000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44515500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 44515500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2659991500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2659991500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2659991500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2659991500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452330 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2452330 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763997 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1763997 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59567 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59567 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59070 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59070 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4216327 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4216327 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4216327 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4216327 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050253 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050253 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036709 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036709 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156916 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156916 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103995 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103995 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044586 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044586 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044586 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044586 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12120.581648 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12120.581648 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.234827 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.234827 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.551514 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.551514 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7246.540778 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7246.540778 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14149.643598 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14149.643598 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1141,62 +1299,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 114265 # number of writebacks -system.cpu1.dcache.writebacks::total 114265 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118301 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118301 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62725 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62725 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8915 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8915 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5846 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5846 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 181026 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 181026 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 181026 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 181026 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203948500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203948500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 988115500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 988115500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63615500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63615500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57370000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57370000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2192064000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2192064000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2192064000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2192064000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 119115 # number of writebacks +system.cpu1.dcache.writebacks::total 119115 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123236 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123236 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64754 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 64754 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9347 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9347 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6143 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6143 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 187990 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 187990 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 187990 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 187990 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247220000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247220000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036791500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1036791500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66696000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66696000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32229500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32229500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2284011500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284011500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2284011500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |