diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2032 |
1 files changed, 1023 insertions, 1009 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 9611b47c5..e64aeb301 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.957578 # Number of seconds simulated -sim_ticks 1957577582000 # Number of ticks simulated -final_tick 1957577582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.954209 # Number of seconds simulated +sim_ticks 1954209106000 # Number of ticks simulated +final_tick 1954209106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1866861 # Simulator instruction rate (inst/s) -host_op_rate 1866860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61595044213 # Simulator tick rate (ticks/s) -host_mem_usage 296940 # Number of bytes of host memory used -host_seconds 31.78 # Real time elapsed on the host -sim_insts 59331415 # Number of instructions simulated -sim_ops 59331415 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 825984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24749824 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 37440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 398080 # Number of bytes read from this memory -system.physmem.bytes_read::total 28662144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 825984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 37440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7684736 # Number of bytes written to this memory -system.physmem.bytes_written::total 7684736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386716 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 585 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6220 # Number of read requests responded to by this memory -system.physmem.num_reads::total 447846 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120074 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120074 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 421942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12643087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1354131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 19126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 203353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14641639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 421942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 19126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441068 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3925635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3925635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3925635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 421942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12643087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1354131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 19126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 203353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18567274 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 340832 # number of replacements -system.l2c.tagsinuse 65295.945000 # Cycle average of tags in use -system.l2c.total_refs 2492123 # Total number of references to valid blocks. -system.l2c.sampled_refs 405944 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.139081 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7739998000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55466.932424 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4795.907583 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4852.495880 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 163.850290 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 16.758824 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.846358 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.073180 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.074043 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.002500 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000256 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.996337 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 902441 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 771400 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 86210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 33732 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1793783 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 821051 # number of Writeback hits -system.l2c.Writeback_hits::total 821051 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 34 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 172323 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 12709 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 185032 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 902441 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 943723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 86210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 46441 # number of demand (read+write) hits -system.l2c.demand_hits::total 1978815 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 902441 # number of overall hits -system.l2c.overall_hits::cpu0.data 943723 # number of overall hits -system.l2c.overall_hits::cpu1.inst 86210 # number of overall hits -system.l2c.overall_hits::cpu1.data 46441 # number of overall hits -system.l2c.overall_hits::total 1978815 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12906 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271613 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 596 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 192 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285307 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2453 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 486 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2939 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 16 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 72 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 88 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115483 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6047 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121530 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12906 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387096 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 596 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6239 # number of demand (read+write) misses -system.l2c.demand_misses::total 406837 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12906 # number of overall misses -system.l2c.overall_misses::cpu0.data 387096 # number of overall misses -system.l2c.overall_misses::cpu1.inst 596 # number of overall misses -system.l2c.overall_misses::cpu1.data 6239 # number of overall misses -system.l2c.overall_misses::total 406837 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 671157500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14128859000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 30971000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 10024000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14841011500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 2088000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 624000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2712000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 260000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 468000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6005389000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 314450000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6319839000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 671157500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 20134248000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 30971000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 324474000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21160850500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 671157500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 20134248000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 30971000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 324474000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21160850500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915347 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1043013 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 86806 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 33924 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2079090 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 821051 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 821051 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2619 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 540 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3159 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 30 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 122 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 287806 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18756 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 306562 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915347 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1330819 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 86806 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 52680 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2385652 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915347 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1330819 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 86806 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 52680 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2385652 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014100 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.260412 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006866 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.005660 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.137227 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.936617 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.900000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930358 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.533333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.782609 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.721311 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.401253 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.322403 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.396429 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014100 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290871 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006866 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.118432 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.170535 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014100 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290871 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006866 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.118432 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.170535 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.525492 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.345955 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51964.765101 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52208.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52017.691469 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 851.202609 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1283.950617 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 922.762845 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16250 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2888.888889 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5318.181818 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.363984 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.992228 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52002.295729 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52013.092467 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52013.092467 # average overall miss latency +host_inst_rate 1820229 # Simulator instruction rate (inst/s) +host_op_rate 1820228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59866957581 # Simulator tick rate (ticks/s) +host_mem_usage 296900 # Number of bytes of host memory used +host_seconds 32.64 # Real time elapsed on the host +sim_insts 59416827 # Number of instructions simulated +sim_ops 59416827 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 717056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 23797184 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 145856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1424768 # Number of bytes read from this memory +system.physmem.bytes_read::total 28734208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 717056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 145856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 862912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7745216 # Number of bytes written to this memory +system.physmem.bytes_written::total 7745216 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 371831 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2279 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448972 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121019 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121019 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 366929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12177399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1355712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 74637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 729077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14703753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 366929 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 74637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3963351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3963351 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3963351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 366929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12177399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1355712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 74637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 729077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18667104 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 342059 # number of replacements +system.l2c.tagsinuse 65268.179703 # Cycle average of tags in use +system.l2c.total_refs 2559285 # Total number of references to valid blocks. +system.l2c.sampled_refs 407065 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.287165 # Average number of references to valid blocks. +system.l2c.warmup_cycle 7752825000 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40014.971542 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -344,39 +344,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41694 # number of replacements -system.iocache.tagsinuse 0.563379 # Cycle average of tags in use +system.iocache.replacements 41707 # number of replacements +system.iocache.tagsinuse 1.261560 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41723 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1750565168000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.563379 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035211 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035211 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.warmup_cycle 1747651126000 # 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miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 137656.040768 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137562.594162 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137562.594162 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183529.572728 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183529.572728 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183259.077933 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183259.077933 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7245000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7076 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6179.373554 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1023.883550 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41531 # number of writebacks +system.iocache.writebacks::total 41531 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559028000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 3559028000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3570032998 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3570032998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3570032998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3570032998 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11861000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465163000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5465163000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5477024000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5477024000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5477024000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5477024000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131525.871198 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131525.871198 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 8630502 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 6043026 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses -system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 14673528 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses -system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3852973 # ITB hits -system.cpu0.itb.fetch_misses 3871 # ITB misses -system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3856844 # ITB accesses +system.cpu0.dtb.read_hits 5733478 # DTB read hits +system.cpu0.dtb.read_misses 7687 # DTB read misses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_accesses 524201 # DTB read accesses +system.cpu0.dtb.write_hits 3961950 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses +system.cpu0.dtb.write_acv 115 # DTB write access violations +system.cpu0.dtb.write_accesses 195659 # DTB write accesses +system.cpu0.dtb.data_hits 9695428 # DTB hits +system.cpu0.dtb.data_misses 8485 # DTB misses +system.cpu0.dtb.data_acv 289 # DTB access violations +system.cpu0.dtb.data_accesses 719860 # DTB accesses +system.cpu0.itb.fetch_hits 3214168 # ITB hits +system.cpu0.itb.fetch_misses 3841 # ITB misses +system.cpu0.itb.fetch_acv 143 # ITB acv +system.cpu0.itb.fetch_accesses 3218009 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,117 +480,118 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3914070794 # number of cpu cycles simulated +system.cpu0.numCycles 3908418212 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 54051547 # Number of instructions committed -system.cpu0.committedOps 54051547 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 50023130 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses -system.cpu0.num_func_calls 1426247 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6235141 # number of instructions that are conditional controls -system.cpu0.num_int_insts 50023130 # number of integer instructions -system.cpu0.num_fp_insts 293967 # number of float instructions -system.cpu0.num_int_register_reads 68498295 # number of times the integer registers were read -system.cpu0.num_int_register_writes 37064173 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written -system.cpu0.num_mem_refs 14719518 # number of memory refs -system.cpu0.num_load_insts 8661793 # Number of load instructions -system.cpu0.num_store_insts 6057725 # Number of store instructions -system.cpu0.num_idle_cycles 3679914036.735006 # Number of idle cycles -system.cpu0.num_busy_cycles 234156757.264994 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059824 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940176 # Percentage of idle cycles +system.cpu0.committedInsts 36160823 # Number of instructions committed +system.cpu0.committedOps 36160823 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33648358 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 143029 # Number of float alu accesses +system.cpu0.num_func_calls 874754 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4239281 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33648358 # number of integer instructions +system.cpu0.num_fp_insts 143029 # number of float instructions +system.cpu0.num_int_register_reads 46246578 # number of times the integer registers were read +system.cpu0.num_int_register_writes 25142775 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 70823 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 71471 # number of times the floating registers were written +system.cpu0.num_mem_refs 9726012 # number of memory refs +system.cpu0.num_load_insts 5755191 # Number of load instructions +system.cpu0.num_store_insts 3970821 # Number of store instructions +system.cpu0.num_idle_cycles 3741416410.998085 # Number of idle cycles +system.cpu0.num_busy_cycles 167001801.001915 # Number of busy cycles +system.cpu0.not_idle_fraction 0.042729 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.957271 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6362 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 202969 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 72743 40.62% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1974 1.10% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 104206 58.20% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 179060 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 71376 49.27% 49.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1974 1.36% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 71370 49.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 144857 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1898820258500 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 78970000 0.00% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 565865000 0.03% 97.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 4687500 0.00% 97.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 57565586000 2.94% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1957035367000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981208 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4839 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 129052 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 41012 38.31% 38.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.12% 38.43% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1971 1.84% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 63918 59.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 107049 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 40581 48.74% 48.74% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1971 2.37% 51.26% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 17 0.02% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 40564 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 83264 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1905787793000 97.52% 97.52% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 88207500 0.00% 97.53% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 590484500 0.03% 97.56% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 12827000 0.00% 97.56% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 47728938000 2.44% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1954208250000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.989491 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684893 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808986 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.634626 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.777812 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed +system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed +system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed +system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed +system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 224 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed -system.cpu0.kern.callpal::swpipl 172198 91.50% 93.65% # number of callpals executed -system.cpu0.kern.callpal::rdps 6677 3.55% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed -system.cpu0.kern.callpal::rti 4750 2.52% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 188201 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7301 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::wripir 91 0.08% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed +system.cpu0.kern.callpal::swpctx 1959 1.72% 1.80% # number of callpals executed +system.cpu0.kern.callpal::tbi 44 0.04% 1.84% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.84% # number of callpals executed +system.cpu0.kern.callpal::swpipl 101151 88.59% 90.44% # number of callpals executed +system.cpu0.kern.callpal::rdps 6620 5.80% 96.24% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.24% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.24% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.01% 96.25% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.25% # number of callpals executed +system.cpu0.kern.callpal::rti 3778 3.31% 99.56% # number of callpals executed +system.cpu0.kern.callpal::callsys 356 0.31% 99.87% # number of callpals executed +system.cpu0.kern.callpal::imb 149 0.13% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 114173 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5323 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1229 +system.cpu0.kern.mode_good::user 1230 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.175729 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.230885 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.298928 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1953310949000 99.83% 99.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3370111000 0.17% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.375248 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1950524029000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3684214000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3895 # number of times the context was actually changed +system.cpu0.kern.swap_context 1960 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -622,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 914734 # number of replacements -system.cpu0.icache.tagsinuse 508.814250 # Cycle average of tags in use -system.cpu0.icache.total_refs 53144779 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 915246 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 58.066114 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 35914239000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.814250 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993778 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993778 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 53144779 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 53144779 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 53144779 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 53144779 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 53144779 # number of overall hits -system.cpu0.icache.overall_hits::total 53144779 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 915368 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915368 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 915368 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915368 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 915368 # number of overall misses -system.cpu0.icache.overall_misses::total 915368 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13361799000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13361799000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13361799000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13361799000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13361799000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13361799000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 54060147 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 54060147 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 54060147 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 54060147 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 54060147 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 54060147 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016932 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.016932 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016932 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.016932 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016932 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.016932 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14597.188235 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14597.188235 # average overall miss latency +system.cpu0.icache.replacements 489211 # number of replacements +system.cpu0.icache.tagsinuse 508.795621 # Cycle average of tags in use +system.cpu0.icache.total_refs 35679745 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 489723 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 72.856993 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 36113258000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.795621 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993741 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993741 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 35679745 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 35679745 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 35679745 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 35679745 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 35679745 # number of overall hits +system.cpu0.icache.overall_hits::total 35679745 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 489853 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 489853 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 489853 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 489853 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 489853 # number of overall misses +system.cpu0.icache.overall_misses::total 489853 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462564000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7462564000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7462564000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7462564000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7462564000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7462564000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169598 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36169598 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36169598 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36169598 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36169598 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36169598 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013543 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013543 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013543 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013543 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013543 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013543 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15234.292737 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15234.292737 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15234.292737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15234.292737 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,114 +676,114 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 55 # number of writebacks -system.cpu0.icache.writebacks::total 55 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915368 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915368 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915368 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915368 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915368 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915368 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10614998000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10614998000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10614998000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10614998000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10614998000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10614998000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016932 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.016932 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.016932 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 58 # number of writebacks +system.cpu0.icache.writebacks::total 58 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489853 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 489853 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 489853 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 489853 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 489853 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 489853 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992343500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992343500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992343500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5992343500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992343500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5992343500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.942332 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1337419 # number of replacements -system.cpu0.dcache.tagsinuse 506.341163 # Cycle average of tags in use -system.cpu0.dcache.total_refs 13344261 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1337832 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.974542 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 506.341163 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.988948 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.988948 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7419012 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7419012 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5558431 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5558431 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176349 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 176349 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191666 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 191666 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12977443 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12977443 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12977443 # number of overall hits -system.cpu0.dcache.overall_hits::total 12977443 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1034980 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1034980 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 291529 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 291529 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16694 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16694 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 411 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 411 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1326509 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1326509 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1326509 # number of overall misses -system.cpu0.dcache.overall_misses::total 1326509 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 25827814500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 25827814500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9022984000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9022984000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234039000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 234039000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2995000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2995000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34850798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34850798500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34850798500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34850798500 # 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Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.937268 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5008280 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5008280 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3627742 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3627742 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 122538 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8636022 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8636022 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8636022 # number of overall hits +system.cpu0.dcache.overall_hits::total 8636022 # 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average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33294.531672 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33294.531672 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -791,62 +792,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 790358 # 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mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092737 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4287.104623 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4287.104623 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73166000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73166000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6564000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6564000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24770377526 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24770377526 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24770377526 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 24770377526 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014438500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014438500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615647000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615647000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108672 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108672 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053990 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053990 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086491 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086491 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29656.293285 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29656.293285 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32176.546457 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32176.546457 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11149.954282 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11149.954282 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11317.241379 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11317.241379 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -858,22 +859,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1049963 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 651106 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses -system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 1701069 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses -system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1493400 # ITB hits -system.cpu1.itb.fetch_misses 1216 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1494616 # ITB accesses +system.cpu1.dtb.read_hits 3958078 # DTB read hits +system.cpu1.dtb.read_misses 2750 # DTB read misses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_accesses 205838 # DTB read accesses +system.cpu1.dtb.write_hits 2742847 # DTB write hits +system.cpu1.dtb.write_misses 356 # DTB write misses +system.cpu1.dtb.write_acv 48 # DTB write access violations +system.cpu1.dtb.write_accesses 97040 # DTB write accesses +system.cpu1.dtb.data_hits 6700925 # DTB hits +system.cpu1.dtb.data_misses 3106 # DTB misses +system.cpu1.dtb.data_acv 84 # DTB access violations +system.cpu1.dtb.data_accesses 302878 # DTB accesses +system.cpu1.itb.fetch_hits 2128502 # ITB hits +system.cpu1.itb.fetch_misses 1246 # ITB misses +system.cpu1.itb.fetch_acv 41 # ITB acv +system.cpu1.itb.fetch_accesses 2129748 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -886,141 +887,150 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3915155164 # number of cpu cycles simulated +system.cpu1.numCycles 3908222380 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5279868 # Number of instructions committed -system.cpu1.committedOps 5279868 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 4945263 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses -system.cpu1.num_func_calls 157997 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 510441 # number of instructions that are conditional controls -system.cpu1.num_int_insts 4945263 # number of integer instructions -system.cpu1.num_fp_insts 34031 # number of float instructions -system.cpu1.num_int_register_reads 6880916 # number of times the integer registers were read -system.cpu1.num_int_register_writes 3730475 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written -system.cpu1.num_mem_refs 1710522 # number of memory refs -system.cpu1.num_load_insts 1055970 # Number of load instructions -system.cpu1.num_store_insts 654552 # Number of store instructions -system.cpu1.num_idle_cycles 3896226886.998010 # Number of idle cycles -system.cpu1.num_busy_cycles 18928277.001990 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004835 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995165 # Percentage of idle cycles +system.cpu1.committedInsts 23256004 # Number of instructions committed +system.cpu1.committedOps 23256004 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 21401422 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 186242 # Number of float alu accesses +system.cpu1.num_func_calls 709842 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2519926 # number of instructions that are conditional controls +system.cpu1.num_int_insts 21401422 # number of integer instructions +system.cpu1.num_fp_insts 186242 # number of float instructions +system.cpu1.num_int_register_reads 29248159 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15707401 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 95219 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 97489 # number of times the floating registers were written +system.cpu1.num_mem_refs 6725970 # number of memory refs +system.cpu1.num_load_insts 3973767 # Number of load instructions +system.cpu1.num_store_insts 2752203 # Number of store instructions +system.cpu1.num_idle_cycles 3808684025.637170 # Number of idle cycles +system.cpu1.num_busy_cycles 99538354.362830 # Number of busy cycles +system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2314 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 36187 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 9288 32.15% 32.15% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 88 0.30% 39.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 17548 60.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 28893 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 9278 45.20% 45.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 88 0.43% 55.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 9190 44.77% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 20525 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1917614123000 97.96% 97.96% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 507941000 0.03% 97.98% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 53691000 0.00% 97.99% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 39401069000 2.01% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1957576824000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3849 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 109556 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 40729 40.60% 40.60% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1966 1.96% 42.56% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 91 0.09% 42.65% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 57540 57.35% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 100326 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 39783 48.79% 48.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1901560823500 97.31% 97.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 537428500 0.03% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 51953872000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1954111160000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.523706 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.710380 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.689816 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.812671 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed +system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed +system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed +system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed +system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed +system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed +system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed +system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 102 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed -system.cpu1.kern.callpal::swpipl 24305 82.25% 83.46% # number of callpals executed -system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 90.83% # number of callpals executed -system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2292 2.22% 2.24% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.01% 2.25% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.26% # number of callpals executed +system.cpu1.kern.callpal::swpipl 94758 91.98% 94.24% # number of callpals executed +system.cpu1.kern.callpal::rdps 2221 2.16% 96.40% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.40% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 96.40% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 96.40% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.41% # number of callpals executed +system.cpu1.kern.callpal::rti 3510 3.41% 99.81% # number of callpals executed +system.cpu1.kern.callpal::callsys 161 0.16% 99.97% # number of callpals executed +system.cpu1.kern.callpal::imb 31 0.03% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 29550 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 476 -system.cpu1.kern.mode_good::user 463 -system.cpu1.kern.mode_good::idle 13 -system.cpu1.kern.mode_switch_good::kernel 0.592777 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 103020 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2836 # number of protection mode switches +system.cpu1.kern.mode_switch::user 515 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2038 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 568 +system.cpu1.kern.mode_good::user 515 +system.cpu1.kern.mode_good::idle 53 +system.cpu1.kern.mode_switch_good::kernel 0.200282 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.285800 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3531821000 0.18% 0.18% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1727088000 0.09% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1952317913000 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 338 # number of times the context was actually changed -system.cpu1.icache.replacements 86261 # number of replacements -system.cpu1.icache.tagsinuse 419.419440 # Cycle average of tags in use -system.cpu1.icache.total_refs 5196422 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 86773 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 59.885241 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1941709468000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 419.419440 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.819179 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.819179 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 5196422 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5196422 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5196422 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5196422 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5196422 # number of overall hits -system.cpu1.icache.overall_hits::total 5196422 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 86809 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 86809 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 86809 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 86809 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 86809 # number of overall misses -system.cpu1.icache.overall_misses::total 86809 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1248608500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 1248608500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 1248608500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 1248608500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 1248608500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 1248608500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5283231 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5283231 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5283231 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5283231 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5283231 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5283231 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016431 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.016431 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016431 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14685.905389 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1029,114 +1039,114 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 14 # number of writebacks -system.cpu1.icache.writebacks::total 14 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86809 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 86809 # 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Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 416.168626 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.812829 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.812829 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 1003125 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1003125 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 616808 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 616808 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11818 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 11818 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11519 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 11519 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1619933 # 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number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 57413 # number of overall misses -system.cpu1.dcache.overall_misses::total 57413 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 492506000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 492506000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 549958000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 549958000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 11305000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 11305000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6352000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 6352000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 1042464000 # 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number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 635655 # number of overall misses +system.cpu1.dcache.overall_misses::total 635655 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202447500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7202447500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665469000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2665469000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183740000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 183740000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8466000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 8466000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9867916500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9867916500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9867916500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9867916500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3884382 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3884382 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2663241 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2663241 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 84228 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 84228 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 80861 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6547623 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6547623 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6547623 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6547623 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.132181 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.132181 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045890 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.045890 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155566 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155566 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007915 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007915 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097082 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.097082 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14027.827010 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14027.827010 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21809.671481 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21809.671481 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14022.742883 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14022.742883 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15524.013026 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15524.013026 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,62 +1155,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 30624 # number of writebacks -system.cpu1.dcache.writebacks::total 30624 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 36999 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 36999 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20414 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 20414 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 944 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 944 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 507 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 57413 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 57413 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 57413 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 57413 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 381507000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 381507000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 488716000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 488716000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8473000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8473000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4831000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4831000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 870223000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 870223000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 870223000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 870223000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11412500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11412500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298066500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298066500 # 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mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.034228 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034228 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8975.635593 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8975.635593 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9528.599606 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9528.599606 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 498964 # number of writebacks +system.cpu1.dcache.writebacks::total 498964 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513440 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 513440 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122215 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 122215 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13103 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13103 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 640 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 635655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 635655 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 635655 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 635655 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662112010 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662112010 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298824000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298824000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144431000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144431000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7960936010 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7960936010 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7960936010 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7960936010 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516397500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516397500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811433000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811433000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045890 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045890 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007915 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.796841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.796841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18809.671481 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18809.671481 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11022.742883 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11022.742883 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |