diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | |
parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2618 |
1 files changed, 1312 insertions, 1306 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 3f2e8762f..67605a567 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962613 # Number of seconds simulated -sim_ticks 1962612686500 # Number of ticks simulated -final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962608 # Number of seconds simulated +sim_ticks 1962608482500 # Number of ticks simulated +final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1118839 # Simulator instruction rate (inst/s) -host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36057415911 # Simulator tick rate (ticks/s) -host_mem_usage 319640 # Number of bytes of host memory used -host_seconds 54.43 # Real time elapsed on the host -sim_insts 60898638 # Number of instructions simulated -sim_ops 60898638 # Number of ops (including micro ops) simulated +host_inst_rate 1019388 # Simulator instruction rate (inst/s) +host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32859851956 # Simulator tick rate (ticks/s) +host_mem_usage 375280 # Number of bytes of host memory used +host_seconds 59.73 # Real time elapsed on the host +sim_insts 60884587 # Number of instructions simulated +sim_ops 60884587 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory +system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406851 # Number of read requests accepted -system.physmem.writeReqs 161902 # Number of write requests accepted -system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25141 # Per bank write bursts -system.physmem.perBankRdBursts::1 25398 # Per bank write bursts -system.physmem.perBankRdBursts::2 25524 # Per bank write bursts -system.physmem.perBankRdBursts::3 24918 # Per bank write bursts -system.physmem.perBankRdBursts::4 25169 # Per bank write bursts -system.physmem.perBankRdBursts::5 25258 # Per bank write bursts -system.physmem.perBankRdBursts::6 25808 # Per bank write bursts -system.physmem.perBankRdBursts::7 25541 # Per bank write bursts -system.physmem.perBankRdBursts::8 25675 # Per bank write bursts -system.physmem.perBankRdBursts::9 25330 # Per bank write bursts -system.physmem.perBankRdBursts::10 25284 # Per bank write bursts -system.physmem.perBankRdBursts::11 25615 # Per bank write bursts -system.physmem.perBankRdBursts::12 25647 # Per bank write bursts -system.physmem.perBankRdBursts::13 25653 # Per bank write bursts -system.physmem.perBankRdBursts::14 25754 # Per bank write bursts -system.physmem.perBankRdBursts::15 25033 # Per bank write bursts -system.physmem.perBankWrBursts::0 8965 # Per bank write bursts -system.physmem.perBankWrBursts::1 8625 # Per bank write bursts -system.physmem.perBankWrBursts::2 8456 # Per bank write bursts -system.physmem.perBankWrBursts::3 7799 # Per bank write bursts -system.physmem.perBankWrBursts::4 8065 # Per bank write bursts -system.physmem.perBankWrBursts::5 8041 # Per bank write bursts -system.physmem.perBankWrBursts::6 8610 # Per bank write bursts -system.physmem.perBankWrBursts::7 8172 # Per bank write bursts -system.physmem.perBankWrBursts::8 8465 # Per bank write bursts -system.physmem.perBankWrBursts::9 8053 # Per bank write bursts -system.physmem.perBankWrBursts::10 8222 # Per bank write bursts -system.physmem.perBankWrBursts::11 8481 # Per bank write bursts -system.physmem.perBankWrBursts::12 8850 # Per bank write bursts -system.physmem.perBankWrBursts::13 9510 # Per bank write bursts -system.physmem.perBankWrBursts::14 9309 # Per bank write bursts -system.physmem.perBankWrBursts::15 8651 # Per bank write bursts +system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406729 # Number of read requests accepted +system.physmem.writeReqs 120393 # Number of write requests accepted +system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25025 # Per bank write bursts +system.physmem.perBankRdBursts::1 25421 # Per bank write bursts +system.physmem.perBankRdBursts::2 25447 # Per bank write bursts +system.physmem.perBankRdBursts::3 24899 # Per bank write bursts +system.physmem.perBankRdBursts::4 25181 # Per bank write bursts +system.physmem.perBankRdBursts::5 25235 # Per bank write bursts +system.physmem.perBankRdBursts::6 25799 # Per bank write bursts +system.physmem.perBankRdBursts::7 25539 # Per bank write bursts +system.physmem.perBankRdBursts::8 25681 # Per bank write bursts +system.physmem.perBankRdBursts::9 25348 # Per bank write bursts +system.physmem.perBankRdBursts::10 25259 # Per bank write bursts +system.physmem.perBankRdBursts::11 25592 # Per bank write bursts +system.physmem.perBankRdBursts::12 25653 # Per bank write bursts +system.physmem.perBankRdBursts::13 25554 # Per bank write bursts +system.physmem.perBankRdBursts::14 25887 # Per bank write bursts +system.physmem.perBankRdBursts::15 25094 # Per bank write bursts +system.physmem.perBankWrBursts::0 7701 # Per bank write bursts +system.physmem.perBankWrBursts::1 7641 # Per bank write bursts +system.physmem.perBankWrBursts::2 7454 # Per bank write bursts +system.physmem.perBankWrBursts::3 6926 # Per bank write bursts +system.physmem.perBankWrBursts::4 7165 # Per bank write bursts +system.physmem.perBankWrBursts::5 7117 # Per bank write bursts +system.physmem.perBankWrBursts::6 7626 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7527 # Per bank write bursts +system.physmem.perBankWrBursts::9 7238 # Per bank write bursts +system.physmem.perBankWrBursts::10 7225 # Per bank write bursts +system.physmem.perBankWrBursts::11 7418 # Per bank write bursts +system.physmem.perBankWrBursts::12 7843 # Per bank write bursts +system.physmem.perBankWrBursts::13 8207 # Per bank write bursts +system.physmem.perBankWrBursts::14 8447 # Per bank write bursts +system.physmem.perBankWrBursts::15 7584 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 56 # Number of times write queue was full causing retry -system.physmem.totGap 1962566141500 # Total gap between requests +system.physmem.numWrRetry 20 # Number of times write queue was full causing retry +system.physmem.totGap 1962561950500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406851 # Read request sizes (log2) +system.physmem.readPktSize::6 406729 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 161902 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120393 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -158,190 +158,181 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads -system.physmem.totQLat 2137457500 # Total ticks spent queuing -system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads +system.physmem.totQLat 2204423500 # Total ticks spent queuing +system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage +system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing -system.physmem.readRowHits 364433 # Number of row buffer hits during reads -system.physmem.writeRowHits 110956 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes -system.physmem.avgGap 3450647.54 # Average gap between requests -system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.688732 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states -system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states +system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing +system.physmem.readRowHits 363741 # Number of row buffer hits during reads +system.physmem.writeRowHits 96228 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes +system.physmem.avgGap 3723164.56 # Average gap between requests +system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.630269 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states +system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.721130 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states -system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states +system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.683332 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states +system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7492205 # DTB read hits +system.cpu0.dtb.read_hits 7500026 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5067323 # DTB write hits +system.cpu0.dtb.write_hits 5074087 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12559528 # DTB hits +system.cpu0.dtb.data_hits 12574113 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3501951 # ITB hits +system.cpu0.itb.fetch_hits 3504450 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3505822 # ITB accesses +system.cpu0.itb.fetch_accesses 3508321 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,91 +345,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923838766 # number of cpu cycles simulated +system.cpu0.numCycles 3923838721 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47743384 # Number of instructions committed -system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses -system.cpu0.num_func_calls 1202353 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44279734 # number of integer instructions -system.cpu0.num_fp_insts 210698 # number of float instructions -system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599731 # number of memory refs -system.cpu0.num_load_insts 7519361 # Number of load instructions -system.cpu0.num_store_insts 5080370 # Number of store instructions -system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles -system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles -system.cpu0.Branches 7198745 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction -system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction +system.cpu0.committedInsts 47783493 # Number of instructions committed +system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses +system.cpu0.num_func_calls 1203861 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44315744 # number of integer instructions +system.cpu0.num_fp_insts 211234 # number of float instructions +system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written +system.cpu0.num_mem_refs 12614351 # number of memory refs +system.cpu0.num_load_insts 7527207 # Number of load instructions +system.cpu0.num_store_insts 5087144 # Number of store instructions +system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles +system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles +system.cpu0.Branches 7204257 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction +system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction -system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction +system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction +system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47751984 # Class of executed instruction +system.cpu0.op_class::total 47792093 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -470,124 +461,124 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed +system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149812 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches +system.cpu0.kern.callpal::total 150081 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1282 system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3068 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1180939 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu0.kern.swap_context 3073 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1181794 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses -system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101 # average overall miss latency +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # 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number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,126 +587,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks -system.cpu0.dcache.writebacks::total 679102 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses +system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks +system.cpu0.dcache.writebacks::total 679941 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10834 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17944 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits -system.cpu0.icache.overall_hits::total 47052596 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses -system.cpu0.icache.overall_misses::total 699388 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits +system.cpu0.icache.overall_hits::total 47091062 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses +system.cpu0.icache.overall_misses::total 701031 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -724,51 +715,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2419579 # DTB read hits +system.cpu1.dtb.read_hits 2409623 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1757217 # DTB write hits +system.cpu1.dtb.write_hits 1749165 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4176796 # DTB hits +system.cpu1.dtb.data_hits 4158788 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1964101 # ITB hits +system.cpu1.itb.fetch_hits 1960477 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1965317 # ITB accesses +system.cpu1.itb.fetch_accesses 1961693 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -781,87 +772,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3925225373 # number of cpu cycles simulated +system.cpu1.numCycles 3925216965 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13155254 # Number of instructions committed -system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses -system.cpu1.num_func_calls 411301 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12132982 # number of integer instructions -system.cpu1.num_fp_insts 173111 # number of float instructions -system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written -system.cpu1.num_mem_refs 4200357 # number of memory refs -system.cpu1.num_load_insts 2433886 # Number of load instructions -system.cpu1.num_store_insts 1766471 # Number of store instructions -system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles -system.cpu1.Branches 1871330 # Number of branches fetched -system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction -system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction +system.cpu1.committedInsts 13101094 # Number of instructions committed +system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses +system.cpu1.num_func_calls 409417 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12083765 # number of integer instructions +system.cpu1.num_fp_insts 172106 # number of float instructions +system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written +system.cpu1.num_mem_refs 4182249 # number of memory refs +system.cpu1.num_load_insts 2423870 # Number of load instructions +system.cpu1.num_store_insts 1758379 # Number of store instructions +system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles +system.cpu1.Branches 1864071 # Number of branches fetched +system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction +system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction -system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction +system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction +system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13158616 # Class of executed instruction +system.cpu1.op_class::total 13104456 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -877,124 +868,124 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed +system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71473 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 890 -system.cpu1.kern.mode_good::user 463 -system.cpu1.kern.mode_good::idle 427 -system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71137 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches +system.cpu1.kern.mode_switch::user 465 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 889 +system.cpu1.kern.mode_good::user 465 +system.cpu1.kern.mode_good::idle 424 +system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1998 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 166165 # number of replacements -system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1986 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 165381 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits -system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses -system.cpu1.dcache.overall_misses::total 180698 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits +system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses +system.cpu1.dcache.overall_misses::total 179876 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1003,128 +994,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks -system.cpu1.dcache.writebacks::total 114146 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks +system.cpu1.dcache.writebacks::total 113645 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3218 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3307 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 315648 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 313887 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits -system.cpu1.icache.overall_hits::total 12842415 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses -system.cpu1.icache.overall_misses::total 316202 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits +system.cpu1.icache.overall_hits::total 12790016 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses +system.cpu1.icache.overall_misses::total 314441 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1133,30 +1124,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1172,10 +1163,9 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55604 # Transaction distribution -system.iobus.trans_dist::WriteResp 14052 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55595 # Transaction distribution +system.iobus.trans_dist::WriteResp 55595 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1187,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1203,11 +1193,11 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1229,23 +1219,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1253,49 +1243,49 @@ system.iocache.tags.tag_accesses 375534 # Nu system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses system.iocache.demand_misses::total 174 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 174 # number of overall misses system.iocache.overall_misses::total 174 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1303,211 +1293,217 @@ system.iocache.writebacks::writebacks 41520 # nu system.iocache.writebacks::total 41520 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 341367 # number of replacements -system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use -system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy +system.l2c.tags.replacements 341250 # number of replacements +system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use +system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25960355 # Number of tag accesses -system.l2c.tags.data_accesses 25960355 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits -system.l2c.Writeback_hits::total 793248 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.tags.tag_accesses 35905885 # Number of tag accesses +system.l2c.tags.data_accesses 35905885 # Number of data accesses +system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits +system.l2c.Writeback_hits::total 793586 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 686297 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790979 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 315744 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 155940 # number of demand (read+write) hits -system.l2c.demand_hits::total 1948960 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 686297 # number of overall hits -system.l2c.overall_hits::cpu0.data 790979 # number of overall hits -system.l2c.overall_hits::cpu1.inst 315744 # number of overall hits -system.l2c.overall_hits::cpu1.data 155940 # number of overall hits -system.l2c.overall_hits::total 1948960 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13070 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271636 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 457 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 234 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285397 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1736 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4685 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1789 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115627 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 6589 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122216 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13070 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387263 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 457 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6823 # number of demand (read+write) misses -system.l2c.demand_misses::total 407613 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13070 # number of overall misses -system.l2c.overall_misses::cpu0.data 387263 # number of overall misses -system.l2c.overall_misses::cpu1.inst 457 # number of overall misses -system.l2c.overall_misses::cpu1.data 6823 # number of overall misses -system.l2c.overall_misses::total 407613 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1052716500 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 26033004000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1403353000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17974000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1421327000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2195335000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 686710000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2882045000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3598688000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 704684000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4303372000 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944337 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764109 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868304 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.953514 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973828 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.963626 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122956 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412685 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013288 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.289979 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002168 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260015 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172885 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172885 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292759 # Transaction distribution -system.membus.trans_dist::ReadResp 292759 # Transaction distribution -system.membus.trans_dist::WriteReq 14052 # Transaction distribution -system.membus.trans_dist::WriteResp 14052 # Transaction distribution -system.membus.trans_dist::Writeback 120350 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution -system.membus.trans_dist::ReadExReq 122543 # Transaction distribution -system.membus.trans_dist::ReadExResp 121713 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21558 # Total snoops (count) -system.membus.snoop_fanout::samples 618592 # Request fanout histogram +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292720 # Transaction distribution +system.membus.trans_dist::WriteReq 14043 # Transaction distribution +system.membus.trans_dist::WriteResp 14043 # Transaction distribution +system.membus.trans_dist::Writeback 120393 # Transaction distribution +system.membus.trans_dist::CleanEvict 261901 # Transaction distribution +system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution +system.membus.trans_dist::ReadExReq 122456 # Transaction distribution +system.membus.trans_dist::ReadExResp 121630 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution +system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21449 # Total snoops (count) +system.membus.snoop_fanout::samples 880387 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 618592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 618592 # Request fanout histogram -system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 880387 # Request fanout histogram +system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 98552 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3276706 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012746 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112175 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 480853 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3234942 98.73% 98.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41764 1.27% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3276706 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |