diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2680 |
1 files changed, 1330 insertions, 1350 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index c7b14a3ef..a66428f0b 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.963613 # Number of seconds simulated -sim_ticks 1963612574000 # Number of ticks simulated -final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962627 # Number of seconds simulated +sim_ticks 1962626573500 # Number of ticks simulated +final_tick 1962626573500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 811462 # Simulator instruction rate (inst/s) -host_op_rate 811461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26156331100 # Simulator tick rate (ticks/s) -host_mem_usage 332076 # Number of bytes of host memory used -host_seconds 75.07 # Real time elapsed on the host -sim_insts 60918165 # Number of instructions simulated -sim_ops 60918165 # Number of ops (including micro ops) simulated +host_inst_rate 944250 # Simulator instruction rate (inst/s) +host_op_rate 944250 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30421290331 # Simulator tick rate (ticks/s) +host_mem_usage 338248 # Number of bytes of host memory used +host_seconds 64.52 # Real time elapsed on the host +sim_insts 60918166 # Number of instructions simulated +sim_ops 60918166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 831680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24730496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 27968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 420288 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory -system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26011392 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 831680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 27968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7700672 # Number of bytes written to this memory +system.physmem.bytes_written::total 7700672 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6567 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406428 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120323 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120323 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12600714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 214146 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13253358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423759 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 438009 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3923656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3923656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3923656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12600714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 214146 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406688 # Number of read requests accepted -system.physmem.writeReqs 120457 # Number of write requests accepted -system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17177014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406428 # Number of read requests accepted +system.physmem.writeReqs 120323 # Number of write requests accepted +system.physmem.readBursts 406428 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120323 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26003904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue +system.physmem.bytesWritten 7699456 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26011392 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7700672 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25130 # Per bank write bursts -system.physmem.perBankRdBursts::1 25381 # Per bank write bursts -system.physmem.perBankRdBursts::2 25483 # Per bank write bursts -system.physmem.perBankRdBursts::3 24909 # Per bank write bursts -system.physmem.perBankRdBursts::4 25165 # Per bank write bursts -system.physmem.perBankRdBursts::5 25252 # Per bank write bursts -system.physmem.perBankRdBursts::6 25797 # Per bank write bursts -system.physmem.perBankRdBursts::7 25541 # Per bank write bursts -system.physmem.perBankRdBursts::8 25672 # Per bank write bursts -system.physmem.perBankRdBursts::9 25333 # Per bank write bursts -system.physmem.perBankRdBursts::10 25279 # Per bank write bursts -system.physmem.perBankRdBursts::11 25593 # Per bank write bursts -system.physmem.perBankRdBursts::12 25647 # Per bank write bursts -system.physmem.perBankRdBursts::13 25645 # Per bank write bursts -system.physmem.perBankRdBursts::14 25712 # Per bank write bursts -system.physmem.perBankRdBursts::15 25022 # Per bank write bursts -system.physmem.perBankWrBursts::0 7825 # Per bank write bursts -system.physmem.perBankWrBursts::1 7603 # Per bank write bursts -system.physmem.perBankWrBursts::2 7492 # Per bank write bursts -system.physmem.perBankWrBursts::3 6933 # Per bank write bursts -system.physmem.perBankWrBursts::4 7149 # Per bank write bursts -system.physmem.perBankWrBursts::5 7135 # Per bank write bursts -system.physmem.perBankWrBursts::6 7628 # Per bank write bursts -system.physmem.perBankWrBursts::7 7255 # Per bank write bursts -system.physmem.perBankWrBursts::8 7538 # Per bank write bursts -system.physmem.perBankWrBursts::9 7229 # Per bank write bursts -system.physmem.perBankWrBursts::10 7235 # Per bank write bursts -system.physmem.perBankWrBursts::11 7425 # Per bank write bursts -system.physmem.perBankWrBursts::12 7840 # Per bank write bursts -system.physmem.perBankWrBursts::13 8302 # Per bank write bursts -system.physmem.perBankWrBursts::14 8309 # Per bank write bursts -system.physmem.perBankWrBursts::15 7527 # Per bank write bursts +system.physmem.perBankRdBursts::0 25480 # Per bank write bursts +system.physmem.perBankRdBursts::1 25719 # Per bank write bursts +system.physmem.perBankRdBursts::2 25425 # Per bank write bursts +system.physmem.perBankRdBursts::3 24952 # Per bank write bursts +system.physmem.perBankRdBursts::4 24963 # Per bank write bursts +system.physmem.perBankRdBursts::5 25448 # Per bank write bursts +system.physmem.perBankRdBursts::6 25036 # Per bank write bursts +system.physmem.perBankRdBursts::7 25388 # Per bank write bursts +system.physmem.perBankRdBursts::8 25382 # Per bank write bursts +system.physmem.perBankRdBursts::9 25021 # Per bank write bursts +system.physmem.perBankRdBursts::10 25321 # Per bank write bursts +system.physmem.perBankRdBursts::11 25245 # Per bank write bursts +system.physmem.perBankRdBursts::12 25883 # Per bank write bursts +system.physmem.perBankRdBursts::13 25960 # Per bank write bursts +system.physmem.perBankRdBursts::14 25500 # Per bank write bursts +system.physmem.perBankRdBursts::15 25588 # Per bank write bursts +system.physmem.perBankWrBursts::0 8093 # Per bank write bursts +system.physmem.perBankWrBursts::1 7861 # Per bank write bursts +system.physmem.perBankWrBursts::2 7317 # Per bank write bursts +system.physmem.perBankWrBursts::3 6760 # Per bank write bursts +system.physmem.perBankWrBursts::4 6801 # Per bank write bursts +system.physmem.perBankWrBursts::5 7296 # Per bank write bursts +system.physmem.perBankWrBursts::6 7054 # Per bank write bursts +system.physmem.perBankWrBursts::7 7130 # Per bank write bursts +system.physmem.perBankWrBursts::8 7229 # Per bank write bursts +system.physmem.perBankWrBursts::9 7212 # Per bank write bursts +system.physmem.perBankWrBursts::10 7633 # Per bank write bursts +system.physmem.perBankWrBursts::11 7389 # Per bank write bursts +system.physmem.perBankWrBursts::12 8081 # Per bank write bursts +system.physmem.perBankWrBursts::13 8482 # Per bank write bursts +system.physmem.perBankWrBursts::14 7977 # Per bank write bursts +system.physmem.perBankWrBursts::15 7989 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 17 # Number of times write queue was full causing retry -system.physmem.totGap 1963565980500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 1962619726500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406688 # Read request sizes (log2) +system.physmem.readPktSize::6 406428 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120457 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120323 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -159,181 +159,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5737 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::32 5612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65759 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 512.528475 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.841182 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.690018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15231 23.16% 23.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12147 18.47% 41.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5552 8.44% 50.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3316 5.04% 55.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2308 3.51% 58.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1955 2.97% 61.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1491 2.27% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1296 1.97% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22463 34.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65759 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5364 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.747390 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2879.661653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5361 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads -system.physmem.totQLat 2148968000 # Total ticks spent queuing -system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5364 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5364 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.428039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.999012 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.364771 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4746 88.48% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 15 0.28% 88.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.30% 89.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 23 0.43% 89.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 212 3.95% 93.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 26 0.48% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.24% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 2 0.04% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.15% 94.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.15% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 13 0.24% 94.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.04% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.04% 95.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 18 0.34% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.07% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 23 0.43% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.06% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 170 3.17% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.06% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 8 0.15% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.06% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 4 0.07% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 12 0.22% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5364 # Writes before turning the bus around for reads +system.physmem.totQLat 2137214000 # Total ticks spent queuing +system.physmem.totMemAccLat 9755545250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2031555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5260.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24010.04 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing -system.physmem.readRowHits 364299 # Number of row buffer hits during reads -system.physmem.writeRowHits 96294 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes -system.physmem.avgGap 3724906.77 # Average gap between requests -system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.639531 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states -system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states +system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing +system.physmem.readRowHits 364061 # Number of row buffer hits during reads +system.physmem.writeRowHits 96795 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.45 # Row buffer hit rate for writes +system.physmem.avgGap 3725896.54 # Average gap between requests +system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 244346760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133324125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578805800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 377861760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66163184910 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119537594750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316224277385 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.644542 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862206979750 # Time in different power states +system.physmem_0.memoryStateTime::REF 65536380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34882447750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.691088 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states -system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states +system.physmem_1.actEnergy 252791280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 137931750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1590420000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 401708160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66247264755 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119463832250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316283107475 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.674522 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862086480750 # Time in different power states +system.physmem_1.memoryStateTime::REF 65536380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35002933000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7494168 # DTB read hits +system.cpu0.dtb.read_hits 7493005 # DTB read hits system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5065702 # DTB write hits +system.cpu0.dtb.write_hits 5064687 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12559870 # DTB hits +system.cpu0.dtb.data_hits 12557692 # DTB hits system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3501177 # ITB hits +system.cpu0.itb.fetch_hits 3501057 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3505048 # ITB accesses +system.cpu0.itb.fetch_accesses 3504928 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -346,46 +360,46 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13591 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6796 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272307750.367863 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432682187.397928 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6796 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 55000 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13585 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 272297667.010158 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 432721655.998866 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 104000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6796 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 113009102500 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850603471500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3925790590 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 112908521500 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849718052000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3923838819 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164897 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56819 40.19% 40.19% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1973 1.40% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 423 0.30% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82035 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141381 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56285 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 423 0.37% 51.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55862 48.71% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114674 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900334186500 96.86% 96.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93688500 0.00% 96.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 789357000 0.04% 96.91% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314729500 0.02% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60387418000 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919379500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680953 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811099 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -424,8 +438,8 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # nu system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134520 89.85% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed @@ -433,340 +447,340 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.76% # nu system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149727 # number of callpals executed +system.cpu0.kern.callpal::total 149713 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1282 -system.cpu0.kern.mode_good::user 1282 +system.cpu0.kern.mode_good::kernel 1283 +system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186320 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314114 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958165685500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3548030000 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3064 # number of times the context was actually changed -system.cpu0.committedInsts 47755591 # Number of instructions committed -system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses +system.cpu0.committedInsts 47738229 # Number of instructions committed +system.cpu0.committedOps 47738229 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44272305 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses -system.cpu0.num_func_calls 1202061 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44289668 # number of integer instructions +system.cpu0.num_func_calls 1201649 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5610320 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44272305 # number of integer instructions system.cpu0.num_fp_insts 210363 # number of float instructions -system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written +system.cpu0.num_int_register_reads 60851829 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32993694 # number of times the integer registers were written system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written -system.cpu0.num_mem_refs 12600044 # number of memory refs -system.cpu0.num_load_insts 7521304 # Number of load instructions -system.cpu0.num_store_insts 5078740 # Number of store instructions -system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles -system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles -system.cpu0.Branches 7206590 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction -system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction +system.cpu0.num_mem_refs 12597866 # number of memory refs +system.cpu0.num_load_insts 7520141 # Number of load instructions +system.cpu0.num_store_insts 5077725 # Number of store instructions +system.cpu0.num_idle_cycles 3698103141.291685 # Number of idle cycles +system.cpu0.num_busy_cycles 225735677.708315 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057529 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942471 # Percentage of idle cycles +system.cpu0.Branches 7202811 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2726604 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31424940 65.82% 71.53% # Class of executed instruction +system.cpu0.op_class::IntMult 52727 0.11% 71.64% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction -system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25705 0.05% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::MemRead 7695505 16.12% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5083820 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735872 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47764191 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1179864 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. +system.cpu0.op_class::total 47746829 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1179926 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.222517 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11367443 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1180345 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.630611 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits -system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses -system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.222517 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986763 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986763 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 394 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 25 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51462845 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51462845 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6409921 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6409921 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4656712 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4656712 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143926 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143926 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147979 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147979 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11066633 # 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number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 40050188500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 40050188500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 40050188500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7347792 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7347792 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4908197 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4908197 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157586 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157586 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153409 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153409 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12255989 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12255989 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12255989 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12255989 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127640 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127640 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051238 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051238 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086683 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086683 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035396 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035396 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097043 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097043 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097043 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097043 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.352253 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.352253 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43301.083564 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43301.083564 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11036.200586 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11036.200586 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5613.627993 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5613.627993 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33673.844080 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33673.844080 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks -system.cpu0.dcache.writebacks::total 678308 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses +system.cpu0.dcache.writebacks::writebacks 679177 # number of writebacks +system.cpu0.dcache.writebacks::total 679177 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937871 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 937871 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251485 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251485 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13660 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13660 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189356 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1189356 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189356 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1189356 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 698162 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28222744500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28222744500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10638088000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10638088000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137094500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137094500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25052000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25052000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38860832500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38860832500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38860832500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38860832500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578478000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578478000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578478000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578478000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127640 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051238 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051238 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086683 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086683 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035396 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035396 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097043 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097043 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.352253 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.352253 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42301.083564 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42301.083564 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10036.200586 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10036.200586 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4613.627993 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4613.627993 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222008.157525 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222008.157525 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87952.192567 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87952.192567 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 698827 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.151884 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47047389 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 699339 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.274082 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42438027500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.151884 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992484 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992484 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 349 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits -system.cpu0.icache.overall_hits::total 47065399 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses -system.cpu0.icache.overall_misses::total 698792 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48446269 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48446269 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 47047389 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47047389 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47047389 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47047389 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47047389 # number of overall hits +system.cpu0.icache.overall_hits::total 47047389 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 699440 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 699440 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 699440 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 699440 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 699440 # number of overall misses +system.cpu0.icache.overall_misses::total 699440 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10201863500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10201863500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10201863500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10201863500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10201863500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10201863500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47746829 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47746829 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47746829 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47746829 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47746829 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47746829 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014649 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014649 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014649 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014649 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014649 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014649 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14585.759322 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14585.759322 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14585.759322 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14585.759322 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks -system.cpu0.icache.writebacks::total 698162 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 698827 # number of writebacks +system.cpu0.icache.writebacks::total 698827 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699440 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 699440 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 699440 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 699440 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 699440 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 699440 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9502423500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9502423500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9502423500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9502423500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9502423500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9502423500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014649 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014649 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014649 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13585.759322 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2421538 # DTB read hits +system.cpu1.dtb.read_hits 2422670 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1759460 # DTB write hits +system.cpu1.dtb.write_hits 1760134 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4180998 # DTB hits +system.cpu1.dtb.data_hits 4182804 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1965348 # ITB hits +system.cpu1.itb.fetch_hits 1965215 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1966564 # ITB accesses +system.cpu1.itb.fetch_accesses 1966431 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -779,42 +793,42 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5480 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2740 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 707616074.452555 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 409900069.702285 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2740 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 76500 # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5486 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2743 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 706502118.118848 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 410575500.110236 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2743 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 98500 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2740 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 24744530000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1938868044000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3927225148 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 2743 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 24691263500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1937935310000 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3925253147 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2743 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78622 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26563 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 40238 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69272 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25720 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25216 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53407 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909399868000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 730527500 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 354535500 0.02% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52140917500 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962625848500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968264 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626671 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.770975 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -830,346 +844,338 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 423 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63023 88.06% 91.46% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::rti 3777 5.28% 99.75% # number of callpals executed system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71579 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches +system.cpu1.kern.callpal::total 71571 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2066 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2880 # number of protection mode switches system.cpu1.kern.mode_good::kernel 892 system.cpu1.kern.mode_good::user 464 system.cpu1.kern.mode_good::idle 428 -system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.431752 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.148611 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329760 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17773252500 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1704242000 0.09% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943148352000 99.01% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.committedInsts 13162574 # Number of instructions committed -system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses +system.cpu1.committedInsts 13179937 # Number of instructions committed +system.cpu1.committedOps 13179937 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12156604 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses -system.cpu1.num_func_calls 411749 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12139381 # number of integer instructions +system.cpu1.num_func_calls 411985 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1307841 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12156604 # number of integer instructions system.cpu1.num_fp_insts 173446 # number of float instructions -system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16739384 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8921370 # number of times the integer registers were written system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written -system.cpu1.num_mem_refs 4204594 # number of memory refs -system.cpu1.num_load_insts 2435865 # Number of load instructions -system.cpu1.num_store_insts 1768729 # Number of store instructions -system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles -system.cpu1.Branches 1871255 # Number of branches fetched -system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction -system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction -system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction -system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 4206400 # number of memory refs +system.cpu1.num_load_insts 2436997 # Number of load instructions +system.cpu1.num_store_insts 1769403 # Number of store instructions +system.cpu1.num_idle_cycles 3875870619.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49382527.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012581 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987419 # Percentage of idle cycles +system.cpu1.Branches 1874664 # Number of branches fetched +system.cpu1.op_class::No_OpClass 705658 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7796168 59.14% 64.49% # Class of executed instruction +system.cpu1.op_class::IntMult 21633 0.16% 64.65% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14181 0.11% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.78% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.78% # Class of executed instruction +system.cpu1.op_class::MemRead 2508903 19.03% 83.81% # Class of executed instruction +system.cpu1.op_class::MemWrite 1770394 13.43% 97.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 364376 2.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13165936 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 166516 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy +system.cpu1.op_class::total 13183299 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 166569 # number of replacements +system.cpu1.dcache.tags.tagsinuse 484.920851 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4014072 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 167081 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.024707 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 79208580000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.920851 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947111 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.947111 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits -system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses -system.cpu1.dcache.overall_misses::total 181092 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16965673 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16965673 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 2258295 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2258295 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1642687 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1642687 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48217 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48217 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50804 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50804 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3900982 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3900982 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3900982 # number of overall hits +system.cpu1.dcache.overall_hits::total 3900982 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118473 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118473 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62672 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62672 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8931 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8931 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5870 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5870 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 181145 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 181145 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 181145 # number of overall misses +system.cpu1.dcache.overall_misses::total 181145 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1450679500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1450679500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1216299000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1216299000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81854000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81854000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 32847500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 32847500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2666978500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2666978500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2666978500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2666978500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2376768 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2376768 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1705359 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1705359 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57148 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57148 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56674 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56674 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4082127 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4082127 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4082127 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4082127 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049846 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049846 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036750 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036750 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156278 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156278 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103575 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103575 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044375 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044375 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044375 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044375 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12244.811054 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12244.811054 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19407.374904 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19407.374904 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9165.155078 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9165.155078 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5595.826235 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5595.826235 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14722.893262 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14722.893262 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks -system.cpu1.dcache.writebacks::total 114398 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 114559 # number of writebacks +system.cpu1.dcache.writebacks::total 114559 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118473 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118473 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62672 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62672 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8931 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8931 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5870 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5870 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 181145 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 181145 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 181145 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 181145 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1332206500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1332206500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153627000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153627000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72923000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72923000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26977500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26977500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2485833500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2485833500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2485833500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2485833500 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049846 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049846 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036750 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036750 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156278 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156278 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103575 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103575 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044375 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044375 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11244.811054 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11244.811054 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18407.374904 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18407.374904 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8165.155078 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8165.155078 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4595.826235 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4595.826235 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 316153 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 316020 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.922081 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12866727 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316532 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.649056 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960698705500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.922081 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870942 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870942 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits -system.cpu1.icache.overall_hits::total 12849230 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses -system.cpu1.icache.overall_misses::total 316707 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13499873 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13499873 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 12866727 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12866727 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12866727 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12866727 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12866727 # number of overall hits +system.cpu1.icache.overall_hits::total 12866727 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316573 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316573 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316573 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316573 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316573 # number of overall misses +system.cpu1.icache.overall_misses::total 316573 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4250508000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4250508000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4250508000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4250508000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4250508000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4250508000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13183300 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13183300 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13183300 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13183300 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13183300 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13183300 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024013 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024013 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024013 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024013 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024013 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024013 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13426.628297 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13426.628297 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13426.628297 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13426.628297 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks -system.cpu1.icache.writebacks::total 316153 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 316020 # number of writebacks +system.cpu1.icache.writebacks::total 316020 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316573 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316573 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316573 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316573 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316573 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316573 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933935000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933935000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933935000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3933935000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933935000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3933935000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024013 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024013 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024013 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12426.628297 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1182,9 +1188,9 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 7375 # Transaction distribution +system.iobus.trans_dist::ReadResp 7375 # Transaction distribution system.iobus.trans_dist::WriteReq 55610 # Transaction distribution system.iobus.trans_dist::WriteResp 55610 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) @@ -1197,9 +1203,9 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125970 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1210,12 +1216,12 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743514 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 14952500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 763000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1223,60 +1229,60 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15838000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6057500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216134056 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 41696 # number of replacements +system.iocache.tags.tagsinuse 0.568010 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756490226000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.568010 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035501 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035501 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.tag_accesses 375552 # Number of tag accesses +system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses +system.iocache.demand_misses::total 41728 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses +system.iocache.overall_misses::total 41728 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22088883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22088883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858687173 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858687173 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4880776056 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4880776056 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4880776056 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4880776056 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1285,38 +1291,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125505.017045 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125505.017045 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116930.284294 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116930.284294 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116966.450729 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116966.450729 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 16 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13288883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13288883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778678942 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2778678942 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2791967825 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2791967825 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2791967825 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2791967825 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1325,208 +1331,196 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 341504 # number of replacements -system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use -system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75505.017045 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75505.017045 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.327253 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.327253 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 341251 # number of replacements +system.l2c.tags.tagsinuse 65397.203087 # Cycle average of tags in use +system.l2c.tags.total_refs 3991452 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406774 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.812456 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7305719000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 281.092347 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4857.550126 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 59344.826381 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 110.880269 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 802.853964 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004289 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.905530 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35882279 # Number of tag accesses -system.l2c.tags.data_accesses 35882279 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126431 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47312 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 173743 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 685790 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 316251 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1002041 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 663459 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 109055 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 772514 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 685790 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 789890 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 316251 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156367 # 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average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001603 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000443 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.001115 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475803 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.117511 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.410506 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018580 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001380 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013221 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290597 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260355 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018580 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001380 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.040211 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172649 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018580 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001380 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.040211 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172649 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44916.666667 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67128.746754 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72597.285782 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67414.036388 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71711.025908 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63242.401431 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 69739.316239 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63247.992806 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209503.516174 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209561.189054 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82998.272692 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::total 70971.021311 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 851905 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 404237 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 411 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292676 # Transaction distribution +system.membus.trans_dist::ReadResp 292704 # Transaction distribution system.membus.trans_dist::WriteReq 14058 # Transaction distribution system.membus.trans_dist::WriteResp 14058 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution -system.membus.trans_dist::CleanEvict 261938 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120323 # Transaction distribution +system.membus.trans_dist::CleanEvict 261806 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11056 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9461 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 122469 # Transaction distribution -system.membus.trans_dist::ReadExResp 121633 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution +system.membus.trans_dist::ReadExReq 122183 # Transaction distribution +system.membus.trans_dist::ReadExResp 121347 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285505 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1174875 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1217389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83439 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83439 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1300828 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31053824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31135706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21640 # Total snoops (count) -system.membus.snoopTraffic 27008 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 498117 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram +system.membus.pkt_size::total 33793946 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21651 # Total snoops (count) +system.membus.snoopTraffic 27136 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 491014 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001340 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036583 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram -system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 490356 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 658 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 498117 # Request fanout histogram -system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 491014 # Request fanout histogram +system.membus.reqLayer0.occupancy 40347000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314918038 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2173304250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 904117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4781747 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2390985 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 355114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 992 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 932 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102308 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 398828 # Total snoops (count) -system.toL2Bus.snoopTraffic 7391616 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 872539 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1014847 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 815207 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16306 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11300 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27606 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297851 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297851 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1016013 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079098 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 229 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2097686 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605272 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949165 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535742 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7187865 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89487744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118850496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40485888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17815770 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266639898 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 398766 # Total snoops (count) +system.toL2Bus.snoopTraffic 7394432 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2783305 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138476 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345638 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2398113 86.16% 86.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 384964 13.83% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 227 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2783305 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4217117493 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1049361097 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1811830165 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 476124465 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 281628843 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1808,28 +1788,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- |