diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2129 |
1 files changed, 1057 insertions, 1072 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e93e66fed..3e3128027 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,145 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.952724 # Number of seconds simulated -sim_ticks 1952724269500 # Number of ticks simulated -final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.954691 # Number of seconds simulated +sim_ticks 1954691371500 # Number of ticks simulated +final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1678586 # Simulator instruction rate (inst/s) -host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53851852439 # Simulator tick rate (ticks/s) -host_mem_usage 333452 # Number of bytes of host memory used -host_seconds 36.26 # Real time elapsed on the host -sim_insts 60867235 # Number of instructions simulated -sim_ops 60867235 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory -system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448125 # Total number of read requests seen -system.physmem.writeReqs 120294 # Total number of write requests seen -system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28680000 # Total number of bytes read from memory -system.physmem.bytesWritten 7698816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis +host_inst_rate 798728 # Simulator instruction rate (inst/s) +host_op_rate 798728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26318676085 # Simulator tick rate (ticks/s) +host_mem_usage 332420 # Number of bytes of host memory used +host_seconds 74.27 # Real time elapsed on the host +sim_insts 59321614 # Number of instructions simulated +sim_ops 59321614 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory +system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory +system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory +system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 447836 # Total number of read requests seen +system.physmem.writeReqs 119953 # Total number of write requests seen +system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28661504 # Total number of bytes read from memory +system.physmem.bytesWritten 7676992 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry -system.physmem.totGap 1952670553500 # Total gap between requests +system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry +system.physmem.totGap 1954684300500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448125 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121700 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.readPktSize::6 447836 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 119953 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -151,226 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5215 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1391253000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1972248000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 500755000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2473003000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3345330000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 518926000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3864256000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259875 # 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average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256904.620861 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -585,14 +570,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,22 +595,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7490982 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 8631552 # DTB read hits +system.cpu0.dtb.read_misses 7447 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5068153 # DTB write hits +system.cpu0.dtb.read_accesses 490676 # DTB read accesses +system.cpu0.dtb.write_hits 6044616 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12559135 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_hits 14676168 # DTB hits +system.cpu0.dtb.data_misses 8260 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3503456 # ITB hits +system.cpu0.dtb.data_accesses 678128 # DTB accesses +system.cpu0.itb.fetch_hits 3853435 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3507327 # ITB accesses +system.cpu0.itb.fetch_accesses 3857306 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,55 +623,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3904305293 # number of cpu cycles simulated +system.cpu0.numCycles 3908211536 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47706703 # Number of instructions committed -system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses -system.cpu0.num_func_calls 1201591 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44241786 # number of integer instructions -system.cpu0.num_fp_insts 211423 # number of float instructions -system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599388 # number of memory refs -system.cpu0.num_load_insts 7518173 # Number of load instructions -system.cpu0.num_store_insts 5081215 # Number of store instructions -system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles -system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles +system.cpu0.committedInsts 54061829 # Number of instructions committed +system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses +system.cpu0.num_func_calls 1426501 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50032862 # number of integer instructions +system.cpu0.num_fp_insts 294101 # number of float instructions +system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written +system.cpu0.num_mem_refs 14722187 # number of memory refs +system.cpu0.num_load_insts 8662865 # Number of load instructions +system.cpu0.num_store_insts 6059322 # Number of store instructions +system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles +system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles +system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -718,37 +703,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed -system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149953 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches +system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3896 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172217 91.50% 93.65% # number of callpals executed +system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 188224 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3075 # number of times the context was actually changed +system.cpu0.kern.swap_context 3897 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -780,51 +765,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 699703 # number of replacements -system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use -system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits -system.cpu0.icache.overall_hits::total 47014995 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses -system.cpu0.icache.overall_misses::total 700308 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency +system.cpu0.icache.replacements 915312 # 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number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53154487 # number of overall hits +system.cpu0.icache.overall_hits::total 53154487 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915946 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915946 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915946 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses +system.cpu0.icache.overall_misses::total 915946 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54070433 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54070433 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54070433 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016940 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016940 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +818,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # 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number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12979607 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits +system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326962 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190685500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8190685500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5851532 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193066 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 193066 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192099 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 192099 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14306569 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +932,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks -system.cpu0.dcache.writebacks::total 680601 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks +system.cpu0.dcache.writebacks::total 789805 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,22 +999,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2417694 # DTB read hits +system.cpu1.dtb.read_hits 1047086 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1754404 # DTB write hits +system.cpu1.dtb.write_hits 650181 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4172098 # DTB hits +system.cpu1.dtb.data_hits 1697267 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1961503 # ITB hits +system.cpu1.itb.fetch_hits 1487534 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1962719 # ITB accesses +system.cpu1.itb.fetch_accesses 1488750 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1042,51 +1027,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3905448539 # number of cpu cycles simulated +system.cpu1.numCycles 3909382743 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13160532 # Number of instructions committed -system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses -system.cpu1.num_func_calls 411397 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12141335 # number of integer instructions -system.cpu1.num_fp_insts 171917 # number of float instructions -system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written -system.cpu1.num_mem_refs 4195541 # number of memory refs -system.cpu1.num_load_insts 2431931 # Number of load instructions -system.cpu1.num_store_insts 1763610 # Number of store instructions -system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles +system.cpu1.committedInsts 5259785 # Number of instructions committed +system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses +system.cpu1.num_func_calls 156703 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4928462 # number of integer instructions +system.cpu1.num_fp_insts 34031 # number of float instructions +system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written +system.cpu1.num_mem_refs 1706720 # number of memory refs +system.cpu1.num_load_insts 1053093 # Number of load instructions +system.cpu1.num_store_insts 653627 # Number of store instructions +system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1102,81 +1087,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed -system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed +system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed +system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed +system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71284 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches -system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 889 -system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 424 -system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 28898 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 477 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 13 +system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1984 # number of times the context was actually changed -system.cpu1.icache.replacements 314891 # number of replacements -system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use -system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits -system.cpu1.icache.overall_hits::total 12848456 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses -system.cpu1.icache.overall_misses::total 315439 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 338 # number of times the context was actually changed +system.cpu1.icache.replacements 86368 # number of replacements +system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use +system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits +system.cpu1.icache.overall_hits::total 5176232 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses +system.cpu1.icache.overall_misses::total 86916 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1170,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 315439 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 315439 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 315439 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 315439 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11216.238322 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86916 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 86916 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 165415 # number of replacements -system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47962 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50536 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50536 # 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Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # 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miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081279 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042724 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042724 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1284,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks -system.cpu1.dcache.writebacks::total 113605 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # 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number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks +system.cpu1.dcache.writebacks::total 30630 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |