diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-10 11:57:37 -0400 |
| commit | d6283445744d5be2a9ac33f0adbc729d48e22c40 (patch) | |
| tree | 67910602fd144f50fa86b1c8a90e0e4f0e66ee90 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual | |
| parent | cf5935445f23d0ba2f41debc50952fe45d7c9f4a (diff) | |
| download | gem5-d6283445744d5be2a9ac33f0adbc729d48e22c40.tar.xz | |
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 1884 |
1 files changed, 940 insertions, 944 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 19b49bfc4..de241166d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,218 +1,218 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.954210 # Number of seconds simulated -sim_ticks 1954209529000 # Number of ticks simulated -final_tick 1954209529000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962054 # Number of seconds simulated +sim_ticks 1962054431000 # Number of ticks simulated +final_tick 1962054431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1320479 # Simulator instruction rate (inst/s) -host_op_rate 1320478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43430338961 # Simulator tick rate (ticks/s) -host_mem_usage 301360 # Number of bytes of host memory used -host_seconds 45.00 # Real time elapsed on the host -sim_insts 59416773 # Number of instructions simulated -sim_ops 59416773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 717056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 23797184 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 145856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1424768 # Number of bytes read from this memory -system.physmem.bytes_read::total 28734208 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 717056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 145856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 862912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7745216 # Number of bytes written to this memory -system.physmem.bytes_written::total 7745216 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 371831 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2279 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22262 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448972 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121019 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121019 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 366929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12177396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1355711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 74637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 729076 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 366929 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 74637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3963350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3963350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3963350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 366929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12177396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 74637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 729076 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18667100 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 342059 # number of replacements -system.l2c.tagsinuse 65268.160318 # Cycle average of tags in use -system.l2c.total_refs 2559182 # Total number of references to valid blocks. -system.l2c.sampled_refs 407064 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.286928 # Average number of references to valid blocks. -system.l2c.warmup_cycle 7752825000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55637.634903 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3742.497316 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4175.530834 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1176.828105 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 535.669160 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.848963 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.057106 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.063714 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.017957 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.008174 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995913 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 478624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 342590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 511938 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 491329 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1824481 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 858650 # number of Writeback hits -system.l2c.Writeback_hits::total 858650 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 95 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 22 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 101497 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 99318 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200815 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 478624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 444087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 511938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 590647 # number of demand (read+write) hits -system.l2c.demand_hits::total 2025296 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 478624 # number of overall hits -system.l2c.overall_hits::cpu0.data 444087 # number of overall hits -system.l2c.overall_hits::cpu1.inst 511938 # number of overall hits -system.l2c.overall_hits::cpu1.data 590647 # number of overall hits -system.l2c.overall_hits::total 2025296 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11204 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 270589 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2290 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1211 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285294 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2582 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 476 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3058 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 85 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 88 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 173 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 101602 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21093 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122695 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11204 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 372191 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2290 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 22304 # number of demand (read+write) misses -system.l2c.demand_misses::total 407989 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11204 # number of overall misses -system.l2c.overall_misses::cpu0.data 372191 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2290 # number of overall misses -system.l2c.overall_misses::cpu1.data 22304 # number of overall misses -system.l2c.overall_misses::total 407989 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 582910000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 14075669000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 119002000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 63420000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 14841001000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1144000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1924000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 3068000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 695000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 851000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5283582000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1096874000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6380456000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 582910000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 19359251000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 119002000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1160294000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 21221457000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 582910000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 19359251000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 119002000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1160294000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 21221457000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 489828 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 613179 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 514228 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 492540 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2109775 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 858650 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 858650 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2715 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 571 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 107 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 219 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 203099 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 120411 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 323510 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 489828 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 816278 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 514228 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 612951 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2433285 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 489828 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 816278 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 514228 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 612951 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2433285 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.022873 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.441289 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004453 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002459 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.135225 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951013 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833625 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.930615 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.794393 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.785714 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.789954 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.500258 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.175175 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.379262 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.022873 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.455961 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004453 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.036388 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.167670 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.022873 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.455961 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004453 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.036388 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.167670 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52026.954659 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.629730 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51965.938865 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52369.942197 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52020.024957 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 443.067390 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4042.016807 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1003.270111 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8176.470588 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1772.727273 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4919.075145 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736167 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52001.801546 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52002.575492 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52014.291049 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52014.777359 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52014.291049 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52014.777359 # average overall miss latency +host_inst_rate 2014980 # Simulator instruction rate (inst/s) +host_op_rate 2014979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66592137800 # Simulator tick rate (ticks/s) +host_mem_usage 297124 # Number of bytes of host memory used +host_seconds 29.46 # Real time elapsed on the host +sim_insts 59368818 # Number of instructions simulated +sim_ops 59368818 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 834816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24594240 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 29056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 572928 # Number of bytes read from this memory +system.physmem.bytes_read::total 28681856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 834816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 29056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7716416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7716416 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384285 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8952 # Number of read requests responded to by this memory +system.physmem.num_reads::total 448154 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120569 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120569 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 425481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12534943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14618277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 425481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3932825 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3932825 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 15391290000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 18183000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 360196000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16292038000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370658000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19250000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1389908000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1967340000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505194000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2472534000 # 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mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.603448 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.710526 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396328 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412613 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.397444 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.288994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005206 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.168917 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.170582 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.476762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40015.321323 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -344,39 +344,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41707 # number of replacements -system.iocache.tagsinuse 1.261563 # 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miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183535.950279 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183535.950279 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183265.428585 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183265.428585 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7316000 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183595.851126 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183595.851126 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183321.706302 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183321.706302 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183321.706302 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7551000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7050 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7072 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1037.730496 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1067.731900 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41531 # number of writebacks -system.iocache.writebacks::total 41531 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11861000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465428000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5465428000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5477289000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5477289000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5477289000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5477289000 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5467915000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5467915000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5479898000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5479898000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5479898000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5479898000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131532.248749 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131532.248749 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131592.101463 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131592.101463 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131317.948718 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131317.948718 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 5733461 # DTB read hits +system.cpu0.dtb.read_hits 8658373 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.read_acv 174 # DTB read access violations system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 3961949 # DTB write hits +system.cpu0.dtb.write_hits 6036768 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 9695410 # DTB hits +system.cpu0.dtb.data_hits 14695141 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.data_acv 289 # DTB access violations system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3214179 # ITB hits +system.cpu0.itb.fetch_hits 3948342 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3218020 # ITB accesses +system.cpu0.itb.fetch_accesses 3952183 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3908419058 # number of cpu cycles simulated +system.cpu0.numCycles 3924108862 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 36160769 # Number of instructions committed -system.cpu0.committedOps 36160769 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33648309 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 143029 # Number of float alu accesses -system.cpu0.num_func_calls 874750 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4239273 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33648309 # number of integer instructions -system.cpu0.num_fp_insts 143029 # number of float instructions -system.cpu0.num_int_register_reads 46246517 # number of times the integer registers were read -system.cpu0.num_int_register_writes 25142738 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 70823 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 71471 # number of times the floating registers were written -system.cpu0.num_mem_refs 9725994 # number of memory refs -system.cpu0.num_load_insts 5755174 # Number of load instructions -system.cpu0.num_store_insts 3970820 # Number of store instructions -system.cpu0.num_idle_cycles 3741414636.998085 # Number of idle cycles -system.cpu0.num_busy_cycles 167004421.001915 # Number of busy cycles -system.cpu0.not_idle_fraction 0.042729 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.957271 # Percentage of idle cycles +system.cpu0.committedInsts 54115388 # Number of instructions committed +system.cpu0.committedOps 54115388 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50086021 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 302769 # Number of float alu accesses +system.cpu0.num_func_calls 1426994 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6243543 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50086021 # number of integer instructions +system.cpu0.num_fp_insts 302769 # number of float instructions +system.cpu0.num_int_register_reads 68608752 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37121526 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 149232 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 152287 # number of times the floating registers were written +system.cpu0.num_mem_refs 14741011 # number of memory refs +system.cpu0.num_load_insts 8689642 # Number of load instructions +system.cpu0.num_store_insts 6051369 # Number of store instructions +system.cpu0.num_idle_cycles 3676810844.998126 # Number of idle cycles +system.cpu0.num_busy_cycles 247298017.001874 # Number of busy cycles +system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4839 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 129053 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 41012 38.31% 38.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.12% 38.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1971 1.84% 40.27% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 63919 59.71% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 107050 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 40581 48.74% 48.74% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1971 2.37% 51.26% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 17 0.02% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 40564 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 83264 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1905788612000 97.52% 97.52% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 88224500 0.00% 97.53% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 590412500 0.03% 97.56% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 12827000 0.00% 97.56% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 47728597000 2.44% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1954208673000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.989491 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6365 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202758 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72603 40.61% 40.61% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 134 0.07% 40.69% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104051 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 178773 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71234 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 134 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71230 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144583 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900684456500 96.87% 96.87% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 103099000 0.01% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 795217500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60465248000 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962053593000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.634616 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.777805 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684568 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808752 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -561,37 +561,37 @@ system.cpu0.kern.syscall::144 1 0.45% 99.11% # nu system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 224 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 91 0.08% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 1959 1.72% 1.80% # number of callpals executed -system.cpu0.kern.callpal::tbi 44 0.04% 1.84% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.84% # number of callpals executed -system.cpu0.kern.callpal::swpipl 101152 88.59% 90.44% # number of callpals executed -system.cpu0.kern.callpal::rdps 6620 5.80% 96.24% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.24% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.24% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.01% 96.25% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.25% # number of callpals executed -system.cpu0.kern.callpal::rti 3778 3.31% 99.56% # number of callpals executed -system.cpu0.kern.callpal::callsys 356 0.31% 99.87% # number of callpals executed -system.cpu0.kern.callpal::imb 149 0.13% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 114174 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5323 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1231 # number of protection mode switches +system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3870 2.06% 2.11% # number of callpals executed +system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed +system.cpu0.kern.callpal::swpipl 171949 91.52% 93.66% # number of callpals executed +system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed +system.cpu0.kern.callpal::rti 4706 2.50% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 187881 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7232 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1230 -system.cpu0.kern.mode_good::user 1231 +system.cpu0.kern.mode_good::kernel 1229 +system.cpu0.kern.mode_good::user 1230 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.231073 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.169939 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.375496 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1950522760000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3685906000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.290593 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958392751000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3660835000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1960 # number of times the context was actually changed +system.cpu0.kern.swap_context 3871 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 489206 # number of replacements -system.cpu0.icache.tagsinuse 508.795620 # Cycle average of tags in use -system.cpu0.icache.total_refs 35679696 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 489718 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 72.857636 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 36113258000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.795620 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.993741 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.993741 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 35679696 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 35679696 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 35679696 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 35679696 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 35679696 # number of overall hits -system.cpu0.icache.overall_hits::total 35679696 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 489848 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 489848 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 489848 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 489848 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 489848 # number of overall misses -system.cpu0.icache.overall_misses::total 489848 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462315000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7462315000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7462315000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7462315000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7462315000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7462315000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169544 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 36169544 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 36169544 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 36169544 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 36169544 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 36169544 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013543 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013543 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013543 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013543 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013543 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013543 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15233.939916 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15233.939916 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15233.939916 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15233.939916 # average overall miss latency +system.cpu0.icache.replacements 914730 # number of replacements +system.cpu0.icache.tagsinuse 508.781983 # Cycle average of tags in use +system.cpu0.icache.total_refs 53208794 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915241 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.136375 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 508.781983 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53208794 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53208794 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53208794 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53208794 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53208794 # number of overall hits +system.cpu0.icache.overall_hits::total 53208794 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915369 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915369 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915369 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915369 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915369 # number of overall misses +system.cpu0.icache.overall_misses::total 915369 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13645389000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13645389000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13645389000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13645389000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13645389000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13645389000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54124163 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54124163 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54124163 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54124163 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54124163 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54124163 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016912 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016912 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016912 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016912 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016912 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016912 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.981775 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.981775 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14906.981775 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.981775 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14906.981775 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,112 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489848 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 489848 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 489848 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 489848 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 489848 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 489848 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992109500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992109500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992109500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5992109500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992109500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5992109500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.589497 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915369 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915369 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915369 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915369 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915369 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915369 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10898588000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10898588000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10898588000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10898588000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10898588000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10898588000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016912 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016912 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016912 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016912 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11906.223610 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11906.223610 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11906.223610 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 817819 # number of replacements -system.cpu0.dcache.tagsinuse 479.881496 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8879648 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 818331 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 10.850925 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 85697000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.881496 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.937269 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5008276 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5008276 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3627744 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3627744 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 122538 # 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number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 817638 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 817638 # number of overall misses -system.cpu0.dcache.overall_misses::total 817638 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940652000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 19940652000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7284412000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7284412000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92857000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 92857000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8303000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 8303000 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 123118 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9453658 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9453658 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9453658 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9453658 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108670 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.108670 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053989 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.053989 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004711 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004711 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086489 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086489 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086489 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086489 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32657.364372 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32657.364372 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35184.277131 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35184.277131 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14150.716245 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14150.716245 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14315.517241 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14315.517241 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33297.209768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33297.209768 # average overall miss latency +system.cpu0.dcache.replacements 1337806 # number of replacements +system.cpu0.dcache.tagsinuse 506.531092 # Cycle average of tags in use +system.cpu0.dcache.total_refs 13370025 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 1338318 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 9.990170 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 506.531092 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.989319 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.989319 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7444474 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7444474 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5554839 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5554839 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175825 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 175825 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191178 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 191178 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12999313 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12999313 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12999313 # number of overall hits +system.cpu0.dcache.overall_hits::total 12999313 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1037616 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1037616 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 289306 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 289306 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16762 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 16762 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 448 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 448 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1326922 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1326922 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1326922 # number of overall misses +system.cpu0.dcache.overall_misses::total 1326922 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113316000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 26113316000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963970000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8963970000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238512000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 238512000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4951000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4951000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 35077286000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 35077286000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 35077286000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 35077286000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482090 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8482090 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844145 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5844145 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192587 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 192587 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191626 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191626 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14326235 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14326235 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14326235 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14326235 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122330 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.122330 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049504 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049504 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087036 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087036 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002338 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002338 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.647392 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.647392 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30984.390230 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30984.390230 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14229.328242 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14229.328242 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11051.339286 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11051.339286 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26435.077570 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26435.077570 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 26435.077570 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -790,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 359687 # number of writebacks -system.cpu0.dcache.writebacks::total 359687 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610602 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 610602 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207036 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 207036 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6562 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 580 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 580 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 817638 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 817638 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 817638 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 817638 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18108780524 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18108780524 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6663302002 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6663302002 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73171000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73171000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6563000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6563000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24772082526 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24772082526 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24772082526 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 24772082526 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601210500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014423500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014423500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615634000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615634000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108670 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108670 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053989 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086489 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086489 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29657.257140 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29657.257140 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32184.267480 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32184.267480 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11150.716245 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11150.716245 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11315.517241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11315.517241 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 785164 # number of writebacks +system.cpu0.dcache.writebacks::total 785164 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037616 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1037616 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289306 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 289306 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16762 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16762 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 448 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326922 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326922 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326922 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326922 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000405022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000405022 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8096051001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8096051001 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188226000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188226000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3606001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3606001 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096456023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31096456023 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096456023 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31096456023 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1463096000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1463096000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2089087000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2089087000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3552183000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3552183000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122330 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122330 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049504 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049504 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002338 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.586697 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.586697 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27984.386777 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27984.386777 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11229.328242 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11229.328242 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8049.109375 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8049.109375 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23435.029356 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23435.029356 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -857,22 +857,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3958078 # DTB read hits +system.cpu1.dtb.read_hits 1027490 # DTB read hits system.cpu1.dtb.read_misses 2750 # DTB read misses system.cpu1.dtb.read_acv 36 # DTB read access violations system.cpu1.dtb.read_accesses 205838 # DTB read accesses -system.cpu1.dtb.write_hits 2742847 # DTB write hits +system.cpu1.dtb.write_hits 663174 # DTB write hits system.cpu1.dtb.write_misses 356 # DTB write misses system.cpu1.dtb.write_acv 48 # DTB write access violations system.cpu1.dtb.write_accesses 97040 # DTB write accesses -system.cpu1.dtb.data_hits 6700925 # DTB hits +system.cpu1.dtb.data_hits 1690664 # DTB hits system.cpu1.dtb.data_misses 3106 # DTB misses system.cpu1.dtb.data_acv 84 # DTB access violations system.cpu1.dtb.data_accesses 302878 # DTB accesses -system.cpu1.itb.fetch_hits 2128502 # ITB hits +system.cpu1.itb.fetch_hits 1394882 # ITB hits system.cpu1.itb.fetch_misses 1246 # ITB misses system.cpu1.itb.fetch_acv 41 # ITB acv -system.cpu1.itb.fetch_accesses 2129748 # ITB accesses +system.cpu1.itb.fetch_accesses 1396128 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -885,51 +885,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3908222400 # number of cpu cycles simulated +system.cpu1.numCycles 3923836450 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 23256004 # Number of instructions committed -system.cpu1.committedOps 23256004 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 21401422 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 186242 # Number of float alu accesses -system.cpu1.num_func_calls 709842 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2519926 # number of instructions that are conditional controls -system.cpu1.num_int_insts 21401422 # number of integer instructions -system.cpu1.num_fp_insts 186242 # number of float instructions -system.cpu1.num_int_register_reads 29248159 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15707401 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 95219 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 97489 # number of times the floating registers were written -system.cpu1.num_mem_refs 6725970 # number of memory refs -system.cpu1.num_load_insts 3973767 # Number of load instructions -system.cpu1.num_store_insts 2752203 # Number of store instructions -system.cpu1.num_idle_cycles 3808683702.691761 # Number of idle cycles -system.cpu1.num_busy_cycles 99538697.308239 # Number of busy cycles -system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles +system.cpu1.committedInsts 5253430 # Number of instructions committed +system.cpu1.committedOps 5253430 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4920456 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses +system.cpu1.num_func_calls 157592 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 506756 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4920456 # number of integer instructions +system.cpu1.num_fp_insts 25430 # number of float instructions +system.cpu1.num_int_register_reads 6826440 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3699681 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written +system.cpu1.num_mem_refs 1700289 # number of memory refs +system.cpu1.num_load_insts 1033544 # Number of load instructions +system.cpu1.num_store_insts 666745 # Number of store instructions +system.cpu1.num_idle_cycles 3903109824.944130 # Number of idle cycles +system.cpu1.num_busy_cycles 20726625.055870 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005282 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994718 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3849 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 109556 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 40729 40.60% 40.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1966 1.96% 42.56% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 91 0.09% 42.65% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 57540 57.35% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 100326 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 39783 48.79% 48.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1901560916500 97.31% 97.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 537337500 0.03% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 51953880000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1954111170000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 35943 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17500 60.96% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28707 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1920768070500 97.90% 97.90% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 725778000 0.04% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 67189500 0.00% 97.94% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 40357157000 2.06% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961918195000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.689816 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.812671 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.516800 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.705159 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed @@ -953,82 +953,82 @@ system.cpu1.kern.syscall::132 2 1.96% 99.02% # nu system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 102 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2292 2.22% 2.24% # number of callpals executed -system.cpu1.kern.callpal::tbi 10 0.01% 2.25% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.26% # number of callpals executed -system.cpu1.kern.callpal::swpipl 94758 91.98% 94.24% # number of callpals executed -system.cpu1.kern.callpal::rdps 2221 2.16% 96.40% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.40% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.40% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 96.40% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.41% # number of callpals executed -system.cpu1.kern.callpal::rti 3510 3.41% 99.81% # number of callpals executed -system.cpu1.kern.callpal::callsys 161 0.16% 99.97% # number of callpals executed -system.cpu1.kern.callpal::imb 31 0.03% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed +system.cpu1.kern.callpal::swpipl 24055 81.82% 83.15% # number of callpals executed +system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.54% # number of callpals executed +system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # number of callpals executed +system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed +system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 103020 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2836 # number of protection mode switches -system.cpu1.kern.mode_switch::user 515 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2038 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 568 -system.cpu1.kern.mode_good::user 515 -system.cpu1.kern.mode_good::idle 53 -system.cpu1.kern.mode_switch_good::kernel 0.200282 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 29400 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches +system.cpu1.kern.mode_switch::user 516 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 532 +system.cpu1.kern.mode_good::user 516 +system.cpu1.kern.mode_good::idle 16 +system.cpu1.kern.mode_switch_good::kernel 0.605233 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.026006 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.210800 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 72317077000 3.70% 3.70% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1608073000 0.08% 3.78% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1879348652000 96.22% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2293 # number of times the context was actually changed -system.cpu1.icache.replacements 513692 # number of replacements -system.cpu1.icache.tagsinuse 501.294138 # Cycle average of tags in use -system.cpu1.icache.total_refs 22744965 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 514204 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 44.233349 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 96225204000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 501.294138 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.979090 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.979090 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 22744965 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22744965 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22744965 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22744965 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22744965 # number of overall hits -system.cpu1.icache.overall_hits::total 22744965 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 514229 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 514229 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 514229 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 514229 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 514229 # number of overall misses -system.cpu1.icache.overall_misses::total 514229 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551928500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7551928500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7551928500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7551928500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7551928500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7551928500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23259194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23259194 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23259194 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23259194 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23259194 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23259194 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022109 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022109 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022109 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022109 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022109 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022109 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.924948 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.924948 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14685.924948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14685.924948 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.306628 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4074736000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1594048000 0.08% 0.29% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1955463610000 99.71% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 366 # number of times the context was actually changed +system.cpu1.icache.replacements 86665 # number of replacements +system.cpu1.icache.tagsinuse 419.761966 # Cycle average of tags in use +system.cpu1.icache.total_refs 5169415 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 87177 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.297923 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1958459766000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 419.761966 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819848 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819848 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5169415 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5169415 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5169415 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5169415 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5169415 # number of overall hits +system.cpu1.icache.overall_hits::total 5169415 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 87205 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 87205 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 87205 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 87205 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 87205 # number of overall misses +system.cpu1.icache.overall_misses::total 87205 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1314538500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1314538500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1314538500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1314538500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1314538500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1314538500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5256620 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5256620 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5256620 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5256620 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5256620 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5256620 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15074.118457 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15074.118457 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15074.118457 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15074.118457 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15074.118457 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1037,112 +1037,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514229 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 514229 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 514229 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 514229 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 514229 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 514229 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009175500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009175500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009175500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6009175500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009175500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6009175500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022109 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022109 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022109 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.796600 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87205 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 87205 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 87205 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 87205 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 87205 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 87205 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1052891500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1052891500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1052891500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1052891500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1052891500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1052891500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12073.751505 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12073.751505 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12073.751505 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 642542 # number of replacements -system.cpu1.dcache.tagsinuse 493.349728 # Cycle average of tags in use -system.cpu1.dcache.total_refs 6059289 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 642979 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 9.423774 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 54205321000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 493.349728 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.963574 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.963574 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 3370941 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3370941 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2541028 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2541028 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71125 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 71125 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80221 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80221 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5911969 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5911969 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5911969 # number of overall hits -system.cpu1.dcache.overall_hits::total 5911969 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 513441 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14028.008087 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14028.008087 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21811.378495 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21811.378495 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14021.750744 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14021.750744 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # 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number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 35620 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 35620 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 22610 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 22610 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 543 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 543 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 58230 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 58230 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 58230 # number of overall misses +system.cpu1.dcache.overall_misses::total 58230 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484449000 # 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average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20244.066632 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20244.066632 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20244.066632 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1151,66 +1151,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 498963 # 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number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 635654 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662217009 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662217009 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298995000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298995000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144418000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144418000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7961212009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7961212009 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7961212009 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7961212009 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516366500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516366500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811402000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811402000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045889 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007915 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.979863 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.979863 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18811.378495 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18811.378495 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11021.750744 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11021.750744 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 35190 # number of writebacks +system.cpu1.dcache.writebacks::total 35190 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35620 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 35620 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22610 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 22610 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 543 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 543 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 58230 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 58230 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 58230 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 58230 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377581004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377581004 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626529004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626529004 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9184000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9184000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5453000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5453000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004110008 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1004110008 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004110008 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1004110008 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534607500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534607500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555172500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555172500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034978 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034978 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034835 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044323 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044323 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034922 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034922 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034922 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10600.252779 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10600.252779 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27710.261123 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27710.261123 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9156.530409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9156.530409 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10042.357274 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10042.357274 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17243.860690 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17243.860690 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |