diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt | 2548 |
1 files changed, 1229 insertions, 1319 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 14efebcaa..85845c2fe 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.960910 # Number of seconds simulated -sim_ticks 1960909874500 # Number of ticks simulated -final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961814 # Number of seconds simulated +sim_ticks 1961813569500 # Number of ticks simulated +final_tick 1961813569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1305982 # Simulator instruction rate (inst/s) -host_op_rate 1305981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42027651646 # Simulator tick rate (ticks/s) -host_mem_usage 309852 # Number of bytes of host memory used -host_seconds 46.66 # Real time elapsed on the host -sim_insts 60933947 # Number of instructions simulated -sim_ops 60933947 # Number of ops (including micro ops) simulated +host_inst_rate 1769979 # Simulator instruction rate (inst/s) +host_op_rate 1769979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57024152249 # Simulator tick rate (ticks/s) +host_mem_usage 311592 # Number of bytes of host memory used +host_seconds 34.40 # Real time elapsed on the host +sim_insts 60892925 # Number of instructions simulated +sim_ops 60892925 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory -system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory -system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449082 # Number of read requests accepted -system.physmem.writeReqs 120995 # Number of write requests accepted -system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue -system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu0.inst 833088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24884096 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 31936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 337152 # Number of bytes read from this memory +system.physmem.bytes_read::total 28737152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7735232 # Number of bytes written to this memory +system.physmem.bytes_written::total 7735232 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388814 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449018 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120863 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120863 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12684231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1351240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14648258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424652 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3942899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3942899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3942899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12684231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1351240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 449018 # Number of read requests accepted +system.physmem.writeReqs 120863 # Number of write requests accepted +system.physmem.readBursts 449018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120863 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28729600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7733952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28737152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7735232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28167 # Per bank write bursts -system.physmem.perBankRdBursts::1 28459 # Per bank write bursts -system.physmem.perBankRdBursts::2 28057 # Per bank write bursts -system.physmem.perBankRdBursts::3 27664 # Per bank write bursts -system.physmem.perBankRdBursts::4 27762 # Per bank write bursts -system.physmem.perBankRdBursts::5 27793 # Per bank write bursts -system.physmem.perBankRdBursts::6 28259 # Per bank write bursts -system.physmem.perBankRdBursts::7 27872 # Per bank write bursts -system.physmem.perBankRdBursts::8 28083 # Per bank write bursts -system.physmem.perBankRdBursts::9 27730 # Per bank write bursts -system.physmem.perBankRdBursts::10 27672 # Per bank write bursts -system.physmem.perBankRdBursts::11 28135 # Per bank write bursts -system.physmem.perBankRdBursts::12 28179 # Per bank write bursts -system.physmem.perBankRdBursts::13 28505 # Per bank write bursts -system.physmem.perBankRdBursts::14 28654 # Per bank write bursts -system.physmem.perBankRdBursts::15 28035 # Per bank write bursts -system.physmem.perBankWrBursts::0 7928 # Per bank write bursts -system.physmem.perBankWrBursts::1 7868 # Per bank write bursts -system.physmem.perBankWrBursts::2 7543 # Per bank write bursts -system.physmem.perBankWrBursts::3 7157 # Per bank write bursts -system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7314 # Per bank write bursts -system.physmem.perBankWrBursts::6 7747 # Per bank write bursts -system.physmem.perBankWrBursts::7 7251 # Per bank write bursts -system.physmem.perBankWrBursts::8 7322 # Per bank write bursts -system.physmem.perBankWrBursts::9 7110 # Per bank write bursts -system.physmem.perBankWrBursts::10 7099 # Per bank write bursts -system.physmem.perBankWrBursts::11 7523 # Per bank write bursts -system.physmem.perBankWrBursts::12 7681 # Per bank write bursts -system.physmem.perBankWrBursts::13 8141 # Per bank write bursts -system.physmem.perBankWrBursts::14 8335 # Per bank write bursts -system.physmem.perBankWrBursts::15 7684 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6983 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28166 # Per bank write bursts +system.physmem.perBankRdBursts::1 28350 # Per bank write bursts +system.physmem.perBankRdBursts::2 28054 # Per bank write bursts +system.physmem.perBankRdBursts::3 27500 # Per bank write bursts +system.physmem.perBankRdBursts::4 27615 # Per bank write bursts +system.physmem.perBankRdBursts::5 27605 # Per bank write bursts +system.physmem.perBankRdBursts::6 28127 # Per bank write bursts +system.physmem.perBankRdBursts::7 27851 # Per bank write bursts +system.physmem.perBankRdBursts::8 28176 # Per bank write bursts +system.physmem.perBankRdBursts::9 27723 # Per bank write bursts +system.physmem.perBankRdBursts::10 27750 # Per bank write bursts +system.physmem.perBankRdBursts::11 28018 # Per bank write bursts +system.physmem.perBankRdBursts::12 28330 # Per bank write bursts +system.physmem.perBankRdBursts::13 28694 # Per bank write bursts +system.physmem.perBankRdBursts::14 28891 # Per bank write bursts +system.physmem.perBankRdBursts::15 28050 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7797 # Per bank write bursts +system.physmem.perBankWrBursts::2 7545 # Per bank write bursts +system.physmem.perBankWrBursts::3 7029 # Per bank write bursts +system.physmem.perBankWrBursts::4 7135 # Per bank write bursts +system.physmem.perBankWrBursts::5 7129 # Per bank write bursts +system.physmem.perBankWrBursts::6 7643 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7395 # Per bank write bursts +system.physmem.perBankWrBursts::9 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7104 # Per bank write bursts +system.physmem.perBankWrBursts::11 7401 # Per bank write bursts +system.physmem.perBankWrBursts::12 7833 # Per bank write bursts +system.physmem.perBankWrBursts::13 8315 # Per bank write bursts +system.physmem.perBankWrBursts::14 8551 # Per bank write bursts +system.physmem.perBankWrBursts::15 7701 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1960902862500 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1961806557500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449082 # Read request sizes (log2) +system.physmem.readPktSize::6 449018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120995 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120863 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1052 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1569 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1719 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -143,456 +143,370 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 64 0.13% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 84 0.17% 90.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 51 0.10% 90.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 54 0.11% 91.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 70 0.14% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 45 0.09% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 72 0.15% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 49 0.10% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 40 0.08% 91.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 72 0.15% 91.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 42 0.09% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 45 0.09% 91.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 69 0.14% 92.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 44 0.09% 92.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 64 0.13% 92.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 43 0.09% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 76 0.15% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 39 0.08% 92.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 46 0.09% 92.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 67 0.14% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 46 0.09% 93.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 66 0.13% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 46 0.09% 93.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 37 0.07% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 72 0.15% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 38 0.08% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 42 0.09% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 69 0.14% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 43 0.09% 93.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 64 0.13% 94.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 42 0.09% 94.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 41 0.08% 94.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 74 0.15% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 37 0.07% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 43 0.09% 94.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 66 0.13% 94.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 46 0.09% 94.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 64 0.13% 94.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 43 0.09% 94.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 37 0.07% 95.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 404 0.82% 95.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 34 0.07% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 44 0.09% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 36 0.07% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 44 0.09% 96.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 34 0.07% 96.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 44 0.09% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 33 0.07% 96.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 41 0.08% 96.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 51 0.10% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 44 0.09% 96.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 32 0.06% 96.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 40 0.08% 96.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 37 0.07% 96.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 43 0.09% 96.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 35 0.07% 97.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 40 0.08% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 33 0.07% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 47 0.10% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 34 0.07% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 43 0.09% 97.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 35 0.07% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 44 0.09% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 34 0.07% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 44 0.09% 97.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 38 0.08% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 42 0.09% 97.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 35 0.07% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 43 0.09% 98.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 32 0.06% 98.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 40 0.08% 98.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 37 0.07% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 41 0.08% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 32 0.06% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 431 0.87% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 10 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 2 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation -system.physmem.totQLat 6346588750 # Total ticks spent queuing -system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks -system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 48187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 641.951066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 418.430190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 422.843508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8213 17.04% 17.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7073 14.68% 31.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2891 6.00% 37.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1720 3.57% 41.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1328 2.76% 44.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 906 1.88% 45.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 669 1.39% 47.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 536 1.11% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24851 51.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48187 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 65.095418 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2542.617511 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6893 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6896 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6896 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.523637 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.253710 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.981541 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4466 64.76% 64.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 342 4.96% 69.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 377 5.47% 75.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1323 19.19% 94.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 32 0.46% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.23% 95.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 12 0.17% 95.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.32% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 43 0.62% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 30 0.44% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 27 0.39% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 32 0.46% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 29 0.42% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 31 0.45% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 6 0.09% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 8 0.12% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.15% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.04% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 4 0.06% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 4 0.06% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 3 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 5 0.07% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.04% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 3 0.04% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 3 0.04% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 6 0.09% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 12 0.17% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 5 0.07% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 7 0.10% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 3 0.04% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 5 0.07% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 6 0.09% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6896 # Writes before turning the bus around for reads +system.physmem.totQLat 7845433250 # Total ticks spent queuing +system.physmem.totMemAccLat 16453873250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2244500000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6363940000 # Total ticks spent accessing banks +system.physmem.avgQLat 17477.02 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14176.74 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36653.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing -system.physmem.readRowHits 424775 # Number of row buffer hits during reads -system.physmem.writeRowHits 95849 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes -system.physmem.avgGap 3439715.80 # Average gap between requests -system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18666756 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292805 # Transaction distribution -system.membus.trans_dist::ReadResp 292805 # Transaction distribution -system.membus.trans_dist::WriteReq 14109 # Transaction distribution -system.membus.trans_dist::WriteResp 14109 # Transaction distribution -system.membus.trans_dist::Writeback 120995 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution -system.membus.trans_dist::ReadExReq 164894 # Transaction distribution -system.membus.trans_dist::ReadExResp 164048 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36567218 # Total data (bytes) -system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks) +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.52 # Average write queue length when enqueuing +system.physmem.readRowHits 403422 # Number of row buffer hits during reads +system.physmem.writeRowHits 97436 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.87 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.62 # Row buffer hit rate for writes +system.physmem.avgGap 3442484.58 # Average gap between requests +system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.55 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18651494 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292756 # Transaction distribution +system.membus.trans_dist::ReadResp 292756 # Transaction distribution +system.membus.trans_dist::WriteReq 14067 # Transaction distribution +system.membus.trans_dist::WriteResp 14067 # Transaction distribution +system.membus.trans_dist::Writeback 120863 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16150 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11271 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6986 # Transaction distribution +system.membus.trans_dist::ReadExReq 164854 # Transaction distribution +system.membus.trans_dist::ReadExResp 164030 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930030 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 972562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1097228 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31164224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31246178 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36554338 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36554338 # Total data (bytes) +system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 43154000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1578633000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3834132000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376702000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342160 # number of replacements -system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use -system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy +system.l2c.tags.replacements 342098 # number of replacements +system.l2c.tags.tagsinuse 65220.106735 # Cycle average of tags in use +system.l2c.tags.total_refs 2445213 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407285 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.003690 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8658635750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55273.758884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4807.212496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4935.163888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 160.761256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 43.210211 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.843411 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.075305 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002453 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995180 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 761 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5186 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7242 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51881 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7171 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51861 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25932224 # Number of tag accesses -system.l2c.tags.data_accesses 25932224 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits -system.l2c.Writeback_hits::total 791641 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129054 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42974 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172028 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 684719 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 793579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 317383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 150404 # number of demand (read+write) hits -system.l2c.demand_hits::total 1946085 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 684719 # number of overall hits -system.l2c.overall_hits::cpu0.data 793579 # number of overall hits -system.l2c.overall_hits::cpu1.inst 317383 # number of overall hits -system.l2c.overall_hits::cpu1.data 150404 # number of overall hits -system.l2c.overall_hits::total 1946085 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13026 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271672 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285443 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1793 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4742 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117950 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5055 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123005 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13026 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389622 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5297 # number of demand (read+write) misses -system.l2c.demand_misses::total 408448 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13026 # number of overall misses -system.l2c.overall_misses::cpu0.data 389622 # number of overall misses -system.l2c.overall_misses::cpu1.inst 503 # number of overall misses -system.l2c.overall_misses::cpu1.data 5297 # number of overall misses -system.l2c.overall_misses::total 408448 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 997409492 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17552881248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 35450000 # 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number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 529 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 713 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 64 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 130516 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 42247 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172763 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 690864 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 798814 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 311515 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 146457 # number of demand (read+write) hits +system.l2c.demand_hits::total 1947650 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -728,14 +642,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.570482 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.569649 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754531382000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755503918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569649 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035603 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035603 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -749,14 +663,14 @@ system.iocache.demand_misses::tsunami.ide 41726 # n system.iocache.demand_misses::total 41726 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21249133 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21249133 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12966402814 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12966402814 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 12987651947 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12987651947 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 12987651947 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21248883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21248883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13129991411 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13129991411 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13151240294 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13151240294 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13151240294 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13151240294 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -773,19 +687,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122120.017241 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 315989.396684 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 315180.949384 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 315180.949384 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 388544 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28481 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.642218 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -799,14 +713,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41726 system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10966952411 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10966952411 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10979152294 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10979152294 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10979152294 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10979152294 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -815,14 +729,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -840,22 +754,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7532654 # DTB read hits -system.cpu0.dtb.read_misses 7812 # DTB read misses +system.cpu0.dtb.read_hits 7562587 # DTB read hits +system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524694 # DTB read accesses -system.cpu0.dtb.write_hits 5120278 # DTB write hits -system.cpu0.dtb.write_misses 919 # DTB write misses -system.cpu0.dtb.write_acv 139 # DTB write access violations -system.cpu0.dtb.write_accesses 202960 # DTB write accesses -system.cpu0.dtb.data_hits 12652932 # DTB hits -system.cpu0.dtb.data_misses 8731 # DTB misses -system.cpu0.dtb.data_acv 349 # DTB access violations -system.cpu0.dtb.data_accesses 727654 # DTB accesses -system.cpu0.itb.fetch_hits 3655515 # ITB hits -system.cpu0.itb.fetch_misses 4023 # ITB misses +system.cpu0.dtb.read_accesses 524069 # DTB read accesses +system.cpu0.dtb.write_hits 5147352 # DTB write hits +system.cpu0.dtb.write_misses 910 # DTB write misses +system.cpu0.dtb.write_acv 133 # DTB write access violations +system.cpu0.dtb.write_accesses 202595 # DTB write accesses +system.cpu0.dtb.data_hits 12709939 # DTB hits +system.cpu0.dtb.data_misses 8675 # DTB misses +system.cpu0.dtb.data_acv 343 # DTB access violations +system.cpu0.dtb.data_accesses 726664 # DTB accesses +system.cpu0.itb.fetch_hits 3660806 # ITB hits +system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3659538 # ITB accesses +system.cpu0.itb.fetch_accesses 3664790 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -868,56 +782,56 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3921819749 # number of cpu cycles simulated +system.cpu0.numCycles 3923627139 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47983654 # Number of instructions committed -system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses -system.cpu0.num_func_calls 1203620 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44515044 # number of integer instructions -system.cpu0.num_fp_insts 211401 # number of float instructions -system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written -system.cpu0.num_mem_refs 12694028 # number of memory refs -system.cpu0.num_load_insts 7560495 # Number of load instructions -system.cpu0.num_store_insts 5133533 # Number of store instructions -system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles -system.cpu0.Branches 7227606 # Number of branches fetched +system.cpu0.committedInsts 48127942 # Number of instructions committed +system.cpu0.committedOps 48127942 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44644072 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 213646 # Number of float alu accesses +system.cpu0.num_func_calls 1209779 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5646914 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44644072 # number of integer instructions +system.cpu0.num_fp_insts 213646 # number of float instructions +system.cpu0.num_int_register_reads 61387929 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33243119 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 104403 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 106204 # number of times the floating registers were written +system.cpu0.num_mem_refs 12751056 # number of memory refs +system.cpu0.num_load_insts 7590434 # Number of load instructions +system.cpu0.num_store_insts 5160622 # Number of store instructions +system.cpu0.num_idle_cycles 3699531471.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 224095667.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057114 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942886 # Percentage of idle cycles +system.cpu0.Branches 7246727 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 166332 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 57240 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.39% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82451 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142220 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56707 49.09% 49.09% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1974 1.71% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902164041000 96.96% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 95225000 0.00% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767277500 0.04% 97.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314374500 0.02% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58471894000 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961812812000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682624 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812256 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -949,37 +863,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed -system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed -system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3107 2.06% 2.40% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135267 89.81% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149515 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches +system.cpu0.kern.callpal::total 150615 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7022 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1377 -system.cpu0.kern.mode_good::user 1378 +system.cpu0.kern.mode_good::kernel 1371 +system.cpu0.kern.mode_good::user 1372 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195244 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.326781 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958041026500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3771781000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3091 # number of times the context was actually changed +system.cpu0.kern.swap_context 3108 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1011,47 +925,47 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103937669 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201437426 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks) +system.toL2Bus.throughput 103965077 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2102306 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102291 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792911 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16363 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11335 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27698 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 339143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297593 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134857 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5619111 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45048576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120057312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19969408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16548674 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 201623970 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 201613666 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2346432 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4795947858 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3170057255 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5536383084 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1404201241 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 776393157 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1399302 # Throughput (bytes/s) +system.iobus.throughput 1398487 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55661 # Transaction distribution -system.iobus.trans_dist::WriteResp 55661 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 55619 # Transaction distribution +system.iobus.trans_dist::WriteResp 55619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1063,11 +977,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1079,12 +993,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2743906 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2743570 # Total data (bytes) +system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1106,67 +1020,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380082294 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43185000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 697136 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 703274 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.380970 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47433057 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 703786 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.396989 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40278267250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.380970 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992932 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992932 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48690501 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48690501 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits -system.cpu0.icache.overall_hits::total 47294969 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses -system.cpu0.icache.overall_misses::total 697766 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48840865 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48840865 # 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average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1186229 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # 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Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51851796 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51851796 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # 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number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420082 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7420082 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4989599 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155267 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 155267 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154715 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 154715 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12409681 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12409681 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12409681 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12409681 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127046 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127046 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051712 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051712 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088345 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088345 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035239 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035239 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096756 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096756 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096756 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096756 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7701.648569 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7701.648569 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1296,66 +1210,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks -system.cpu0.dcache.writebacks::total 682519 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 686471 # number of writebacks +system.cpu0.dcache.writebacks::total 686471 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942691 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942691 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258024 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 258024 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13717 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13717 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200715 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1200715 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200715 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1200715 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25249299743 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25249299743 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9714288061 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9714288061 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 123443500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 123443500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31083612 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31083612 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34963587804 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34963587804 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34963587804 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34963587804 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2280051500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2280051500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3745653500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3745653500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051712 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051712 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088345 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035239 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035239 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096756 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096756 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8999.307429 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8999.307429 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5701.322817 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5701.322817 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1367,22 +1277,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2383442 # DTB read hits +system.cpu1.dtb.read_hits 2348422 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1706844 # DTB write hits +system.cpu1.dtb.write_hits 1677006 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4090286 # DTB hits +system.cpu1.dtb.data_hits 4025428 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1814139 # ITB hits +system.cpu1.itb.fetch_hits 1801062 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1815203 # ITB accesses +system.cpu1.itb.fetch_accesses 1802126 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1395,52 +1305,52 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3919927793 # number of cpu cycles simulated +system.cpu1.numCycles 3921881188 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12950293 # Number of instructions committed -system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses -system.cpu1.num_func_calls 410658 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11929999 # number of integer instructions -system.cpu1.num_fp_insts 174217 # number of float instructions -system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written -system.cpu1.num_mem_refs 4113222 # number of memory refs -system.cpu1.num_load_insts 2397194 # Number of load instructions -system.cpu1.num_store_insts 1716028 # Number of store instructions -system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles -system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles -system.cpu1.Branches 1846576 # Number of branches fetched +system.cpu1.committedInsts 12764983 # Number of instructions committed +system.cpu1.committedOps 12764983 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11763372 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses +system.cpu1.num_func_calls 404056 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1265589 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11763372 # number of integer instructions +system.cpu1.num_fp_insts 170364 # number of float instructions +system.cpu1.num_int_register_reads 16177579 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8656447 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written +system.cpu1.num_mem_refs 4047975 # number of memory refs +system.cpu1.num_load_insts 2361944 # Number of load instructions +system.cpu1.num_store_insts 1686031 # Number of store instructions +system.cpu1.num_idle_cycles 3873256564.808130 # Number of idle cycles +system.cpu1.num_busy_cycles 48624623.191870 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012398 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987602 # Percentage of idle cycles +system.cpu1.Branches 1821589 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77081 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26132 38.19% 38.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39821 58.19% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68428 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25288 48.13% 48.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24782 47.16% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 52545 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909614205500 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700881500 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 353850000 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50271627000 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940564000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967702 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.622335 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.767887 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1456,87 +1366,87 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed +system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62267 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::rti 3685 5.22% 99.77% # number of callpals executed system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71838 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches +system.cpu1.kern.callpal::total 70661 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1917 # number of protection mode switches system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 809 +system.cpu1.kern.mode_switch::idle 2889 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 798 system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 441 -system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 430 +system.cpu1.kern.mode_switch_good::kernel 0.416275 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 317336 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.450379 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12635285 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 317847 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.752727 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1958987590000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.148840 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.308465 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17543884000 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1484004500 0.08% 0.97% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941017048000 99.03% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1956 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 311472 # number of replacements +system.cpu1.icache.tags.tagsinuse 449.263709 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12455839 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 311983 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.924736 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960006992500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 449.263709 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.877468 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.877468 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 437 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13271059 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13271059 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12635285 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12635285 # number of overall hits -system.cpu1.icache.overall_hits::total 12635285 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 317887 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 317887 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 317887 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 317887 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 317887 # number of overall misses -system.cpu1.icache.overall_misses::total 317887 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4180819492 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4180819492 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4180819492 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4180819492 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4180819492 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4180819492 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953172 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12953172 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12953172 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12953172 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12953172 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12953172 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024541 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024541 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024541 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024541 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024541 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024541 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13151.904582 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13151.904582 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13079885 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13079885 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12455839 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12455839 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12455839 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12455839 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12455839 # number of overall hits +system.cpu1.icache.overall_hits::total 12455839 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 312023 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 312023 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 312023 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 312023 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 312023 # number of overall misses +system.cpu1.icache.overall_misses::total 312023 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4106650741 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4106650741 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4106650741 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4106650741 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4106650741 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4106650741 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12767862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12767862 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12767862 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12767862 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12767862 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024438 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024438 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024438 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024438 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024438 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024438 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13161.371889 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13161.371889 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1545,118 +1455,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317887 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 317887 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 317887 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 317887 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 317887 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 317887 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3544847508 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3544847508 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3544847508 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3544847508 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3544847508 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3544847508 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024541 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024541 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024541 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312023 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 312023 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 312023 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 312023 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 312023 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 312023 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3482409259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3482409259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3482409259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3482409259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3482409259 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3482409259 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024438 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024438 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024438 # 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Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.619316 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16587420 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16587420 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # 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number of cycles access was blocked @@ -1665,62 +1575,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks -system.cpu1.dcache.writebacks::total 109122 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # 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number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 106440 # number of writebacks +system.cpu1.dcache.writebacks::total 106440 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113735 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 113735 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55930 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 55930 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8863 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8863 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5883 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 169665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 169665 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 169665 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 169665 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144290000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 895105752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 895105752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62746000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62746000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31539091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31539091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2039395752 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2039395752 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2039395752 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2039395752 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713537000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732313500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732313500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049377 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049377 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158744 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158744 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106262 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106262 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043206 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043206 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.544172 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.544172 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.055754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.055754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |