diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual')
4 files changed, 1517 insertions, 1515 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 3ede85d66..7dde96a20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -115,7 +115,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -166,7 +166,7 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -268,7 +268,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -319,7 +319,7 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -467,7 +467,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -513,7 +513,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -611,27 +611,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -651,6 +651,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -660,7 +661,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -682,9 +683,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 5e8bf0780..d5fb9a1a9 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:25 -gem5 executing on e108600-lin, pid 39587 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28056 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 722572000 -Exiting @ tick 1963612574000 because m5_exit instruction encountered +info: Launching CPU 1 @ 752919000 +Exiting @ tick 1966741627000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a66428f0b..de3485335 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962627 # Number of seconds simulated -sim_ticks 1962626573500 # Number of ticks simulated -final_tick 1962626573500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.966742 # Number of seconds simulated +sim_ticks 1966741627000 # Number of ticks simulated +final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 944250 # Simulator instruction rate (inst/s) -host_op_rate 944250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30421290331 # Simulator tick rate (ticks/s) -host_mem_usage 338248 # Number of bytes of host memory used -host_seconds 64.52 # Real time elapsed on the host -sim_insts 60918166 # Number of instructions simulated -sim_ops 60918166 # Number of ops (including micro ops) simulated +host_inst_rate 801704 # Simulator instruction rate (inst/s) +host_op_rate 801704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25865455419 # Simulator tick rate (ticks/s) +host_mem_usage 334360 # Number of bytes of host memory used +host_seconds 76.04 # Real time elapsed on the host +sim_insts 60959478 # Number of instructions simulated +sim_ops 60959478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 831680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24730496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 27968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 420288 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26011392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 27968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7700672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7700672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6567 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory +system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406428 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120323 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12600714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 214146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13253358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423759 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 438009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3923656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3923656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3923656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12600714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 214146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17177014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406428 # Number of read requests accepted -system.physmem.writeReqs 120323 # Number of write requests accepted -system.physmem.readBursts 406428 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120323 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26003904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 7699456 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26011392 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7700672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408131 # Number of read requests accepted +system.physmem.writeReqs 121489 # Number of write requests accepted +system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25480 # Per bank write bursts -system.physmem.perBankRdBursts::1 25719 # Per bank write bursts -system.physmem.perBankRdBursts::2 25425 # Per bank write bursts -system.physmem.perBankRdBursts::3 24952 # Per bank write bursts -system.physmem.perBankRdBursts::4 24963 # Per bank write bursts -system.physmem.perBankRdBursts::5 25448 # Per bank write bursts -system.physmem.perBankRdBursts::6 25036 # Per bank write bursts -system.physmem.perBankRdBursts::7 25388 # Per bank write bursts -system.physmem.perBankRdBursts::8 25382 # Per bank write bursts -system.physmem.perBankRdBursts::9 25021 # Per bank write bursts -system.physmem.perBankRdBursts::10 25321 # Per bank write bursts -system.physmem.perBankRdBursts::11 25245 # Per bank write bursts -system.physmem.perBankRdBursts::12 25883 # Per bank write bursts -system.physmem.perBankRdBursts::13 25960 # Per bank write bursts -system.physmem.perBankRdBursts::14 25500 # Per bank write bursts -system.physmem.perBankRdBursts::15 25588 # Per bank write bursts -system.physmem.perBankWrBursts::0 8093 # Per bank write bursts -system.physmem.perBankWrBursts::1 7861 # Per bank write bursts -system.physmem.perBankWrBursts::2 7317 # Per bank write bursts -system.physmem.perBankWrBursts::3 6760 # Per bank write bursts -system.physmem.perBankWrBursts::4 6801 # Per bank write bursts -system.physmem.perBankWrBursts::5 7296 # Per bank write bursts -system.physmem.perBankWrBursts::6 7054 # Per bank write bursts -system.physmem.perBankWrBursts::7 7130 # Per bank write bursts -system.physmem.perBankWrBursts::8 7229 # Per bank write bursts -system.physmem.perBankWrBursts::9 7212 # Per bank write bursts -system.physmem.perBankWrBursts::10 7633 # Per bank write bursts -system.physmem.perBankWrBursts::11 7389 # Per bank write bursts -system.physmem.perBankWrBursts::12 8081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8482 # Per bank write bursts -system.physmem.perBankWrBursts::14 7977 # Per bank write bursts -system.physmem.perBankWrBursts::15 7989 # Per bank write bursts +system.physmem.perBankRdBursts::0 25299 # Per bank write bursts +system.physmem.perBankRdBursts::1 25599 # Per bank write bursts +system.physmem.perBankRdBursts::2 25910 # Per bank write bursts +system.physmem.perBankRdBursts::3 25657 # Per bank write bursts +system.physmem.perBankRdBursts::4 25586 # Per bank write bursts +system.physmem.perBankRdBursts::5 25177 # Per bank write bursts +system.physmem.perBankRdBursts::6 26012 # Per bank write bursts +system.physmem.perBankRdBursts::7 25110 # Per bank write bursts +system.physmem.perBankRdBursts::8 25002 # Per bank write bursts +system.physmem.perBankRdBursts::9 25326 # Per bank write bursts +system.physmem.perBankRdBursts::10 25348 # Per bank write bursts +system.physmem.perBankRdBursts::11 25350 # Per bank write bursts +system.physmem.perBankRdBursts::12 25736 # Per bank write bursts +system.physmem.perBankRdBursts::13 25396 # Per bank write bursts +system.physmem.perBankRdBursts::14 25673 # Per bank write bursts +system.physmem.perBankRdBursts::15 25838 # Per bank write bursts +system.physmem.perBankWrBursts::0 7888 # Per bank write bursts +system.physmem.perBankWrBursts::1 7973 # Per bank write bursts +system.physmem.perBankWrBursts::2 7891 # Per bank write bursts +system.physmem.perBankWrBursts::3 7697 # Per bank write bursts +system.physmem.perBankWrBursts::4 7528 # Per bank write bursts +system.physmem.perBankWrBursts::5 7375 # Per bank write bursts +system.physmem.perBankWrBursts::6 8079 # Per bank write bursts +system.physmem.perBankWrBursts::7 7030 # Per bank write bursts +system.physmem.perBankWrBursts::8 7056 # Per bank write bursts +system.physmem.perBankWrBursts::9 7058 # Per bank write bursts +system.physmem.perBankWrBursts::10 7243 # Per bank write bursts +system.physmem.perBankWrBursts::11 7671 # Per bank write bursts +system.physmem.perBankWrBursts::12 7657 # Per bank write bursts +system.physmem.perBankWrBursts::13 7555 # Per bank write bursts +system.physmem.perBankWrBursts::14 7813 # Per bank write bursts +system.physmem.perBankWrBursts::15 7948 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1962619726500 # Total gap between requests +system.physmem.numWrRetry 71 # Number of times write queue was full causing retry +system.physmem.totGap 1966734334500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406428 # Read request sizes (log2) +system.physmem.readPktSize::6 408131 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120323 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121489 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -159,195 +159,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65759 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 512.528475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.841182 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.690018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15231 23.16% 23.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12147 18.47% 41.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5552 8.44% 50.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3316 5.04% 55.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2308 3.51% 58.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1955 2.97% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1491 2.27% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1296 1.97% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22463 34.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65759 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5364 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.747390 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2879.661653 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5361 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5364 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.428039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.999012 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.364771 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4746 88.48% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 15 0.28% 88.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.30% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 23 0.43% 89.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 212 3.95% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 26 0.48% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.24% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.04% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.15% 94.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.15% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 13 0.24% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.04% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 18 0.34% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.07% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 23 0.43% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 170 3.17% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.06% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 8 0.15% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.06% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.07% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 12 0.22% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5364 # Writes before turning the bus around for reads -system.physmem.totQLat 2137214000 # Total ticks spent queuing -system.physmem.totMemAccLat 9755545250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2031555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5260.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads +system.physmem.totQLat 6252046750 # Total ticks spent queuing +system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24010.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing -system.physmem.readRowHits 364061 # Number of row buffer hits during reads -system.physmem.writeRowHits 96795 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.45 # Row buffer hit rate for writes -system.physmem.avgGap 3725896.54 # Average gap between requests -system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244346760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133324125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578805800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 377861760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 66163184910 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119537594750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316224277385 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.644542 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862206979750 # Time in different power states -system.physmem_0.memoryStateTime::REF 65536380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34882447750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 252791280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 137931750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1590420000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401708160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66247264755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119463832250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316283107475 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.674522 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862086480750 # Time in different power states -system.physmem_1.memoryStateTime::REF 65536380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35002933000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing +system.physmem.readRowHits 365911 # Number of row buffer hits during reads +system.physmem.writeRowHits 97586 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes +system.physmem.avgGap 3713482.00 # Average gap between requests +system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.237247 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states +system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.444709 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7493005 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7479115 # DTB read hits +system.cpu0.dtb.read_misses 7764 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5064687 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses -system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12557692 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses -system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3501057 # ITB hits -system.cpu0.itb.fetch_misses 3871 # ITB misses +system.cpu0.dtb.read_accesses 524068 # DTB read accesses +system.cpu0.dtb.write_hits 5079820 # DTB write hits +system.cpu0.dtb.write_misses 909 # DTB write misses +system.cpu0.dtb.write_acv 133 # DTB write access violations +system.cpu0.dtb.write_accesses 202594 # DTB write accesses +system.cpu0.dtb.data_hits 12558935 # DTB hits +system.cpu0.dtb.data_misses 8673 # DTB misses +system.cpu0.dtb.data_acv 343 # DTB access violations +system.cpu0.dtb.data_accesses 726662 # DTB accesses +system.cpu0.itb.fetch_hits 3638634 # ITB hits +system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3504928 # ITB accesses +system.cpu0.itb.fetch_accesses 3642618 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -360,427 +360,430 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13585 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272297667.010158 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432721655.998866 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 104000 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 112908521500 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849718052000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3923838819 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3933483254 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164897 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56819 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.40% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 423 0.30% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82035 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141381 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56285 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 423 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55862 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114674 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900334186500 96.86% 96.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93688500 0.00% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 789357000 0.04% 96.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314729500 0.02% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60387418000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919379500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680953 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811099 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134520 89.85% 92.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149713 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed +system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed +system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 148125 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1368 +system.cpu0.kern.mode_good::user 1369 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186320 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314114 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958165685500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3548030000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3064 # number of times the context was actually changed -system.cpu0.committedInsts 47738229 # Number of instructions committed -system.cpu0.committedOps 47738229 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44272305 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses -system.cpu0.num_func_calls 1201649 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5610320 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44272305 # number of integer instructions -system.cpu0.num_fp_insts 210363 # number of float instructions -system.cpu0.num_int_register_reads 60851829 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32993694 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written -system.cpu0.num_mem_refs 12597866 # number of memory refs -system.cpu0.num_load_insts 7520141 # Number of load instructions -system.cpu0.num_store_insts 5077725 # Number of store instructions -system.cpu0.num_idle_cycles 3698103141.291685 # Number of idle cycles -system.cpu0.num_busy_cycles 225735677.708315 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057529 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942471 # Percentage of idle cycles -system.cpu0.Branches 7202811 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2726604 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31424940 65.82% 71.53% # Class of executed instruction -system.cpu0.op_class::IntMult 52727 0.11% 71.64% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25705 0.05% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 7695505 16.12% 87.81% # Class of executed instruction -system.cpu0.op_class::MemWrite 5083820 10.65% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735872 1.54% 100.00% # Class of executed instruction +system.cpu0.kern.swap_context 3065 # number of times the context was actually changed +system.cpu0.committedInsts 47690735 # Number of instructions committed +system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses +system.cpu0.num_func_calls 1190980 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44243506 # number of integer instructions +system.cpu0.num_fp_insts 210072 # number of float instructions +system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599733 # number of memory refs +system.cpu0.num_load_insts 7506744 # Number of load instructions +system.cpu0.num_store_insts 5092989 # Number of store instructions +system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles +system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles +system.cpu0.Branches 7182999 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction +system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction +system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::MemRead 7680863 16.10% 87.77% # Class of executed instruction +system.cpu0.op_class::MemWrite 5099104 10.69% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47746829 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1179926 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.222517 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11367443 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1180345 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.630611 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.222517 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986763 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986763 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 394 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51462845 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51462845 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6409921 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6409921 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4656712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4656712 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143926 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 143926 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147979 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147979 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11066633 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11066633 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11066633 # number of overall hits -system.cpu0.dcache.overall_hits::total 11066633 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 937871 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 937871 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251485 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251485 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13660 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13660 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1189356 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1189356 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1189356 # number of overall misses -system.cpu0.dcache.overall_misses::total 1189356 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29160615500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 29160615500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10889573000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10889573000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150754500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150754500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 30482000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 30482000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 40050188500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 40050188500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 40050188500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 40050188500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7347792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7347792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4908197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4908197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157586 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157586 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153409 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153409 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12255989 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12255989 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12255989 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12255989 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127640 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127640 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051238 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051238 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035396 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035396 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097043 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097043 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097043 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097043 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.352253 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.352253 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43301.083564 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43301.083564 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11036.200586 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11036.200586 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5613.627993 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5613.627993 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33673.844080 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33673.844080 # average overall miss latency +system.cpu0.op_class::total 47699751 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1183172 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses +system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 679177 # number of writebacks -system.cpu0.dcache.writebacks::total 679177 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937871 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 937871 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251485 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251485 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13660 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13660 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189356 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1189356 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189356 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1189356 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28222744500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28222744500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10638088000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10638088000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137094500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137094500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25052000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25052000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38860832500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38860832500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38860832500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38860832500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578478000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578478000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578478000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578478000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086683 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086683 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035396 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035396 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097043 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097043 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.352253 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.352253 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42301.083564 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42301.083564 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10036.200586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10036.200586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4613.627993 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4613.627993 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222008.157525 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222008.157525 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87952.192567 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87952.192567 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 698827 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.151884 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47047389 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 699339 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.274082 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42438027500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.151884 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992484 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992484 # Average percentage of cache occupancy +system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks +system.cpu0.dcache.writebacks::total 681271 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 692001 # number of replacements +system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 349 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48446269 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48446269 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47047389 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47047389 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47047389 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47047389 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47047389 # number of overall hits -system.cpu0.icache.overall_hits::total 47047389 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 699440 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 699440 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 699440 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 699440 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 699440 # number of overall misses -system.cpu0.icache.overall_misses::total 699440 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10201863500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10201863500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10201863500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10201863500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10201863500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10201863500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47746829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47746829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47746829 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47746829 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47746829 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47746829 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014649 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014649 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014649 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014649 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014649 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014649 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14585.759322 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14585.759322 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14585.759322 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14585.759322 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits +system.cpu0.icache.overall_hits::total 47007113 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses +system.cpu0.icache.overall_misses::total 692639 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 698827 # number of writebacks -system.cpu0.icache.writebacks::total 698827 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699440 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 699440 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 699440 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 699440 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 699440 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 699440 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9502423500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9502423500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9502423500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9502423500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9502423500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9502423500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014649 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014649 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014649 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13585.759322 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks +system.cpu0.icache.writebacks::total 692001 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2422670 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2442522 # DTB read hits +system.cpu1.dtb.read_misses 2621 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1760134 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses -system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4182804 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses -system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1965215 # ITB hits -system.cpu1.itb.fetch_misses 1216 # ITB misses +system.cpu1.dtb.read_accesses 205338 # DTB read accesses +system.cpu1.dtb.write_hits 1749235 # DTB write hits +system.cpu1.dtb.write_misses 236 # DTB write misses +system.cpu1.dtb.write_acv 24 # DTB write access violations +system.cpu1.dtb.write_accesses 89740 # DTB write accesses +system.cpu1.dtb.data_hits 4191757 # DTB hits +system.cpu1.dtb.data_misses 2857 # DTB misses +system.cpu1.dtb.data_acv 24 # DTB access violations +system.cpu1.dtb.data_accesses 295078 # DTB accesses +system.cpu1.itb.fetch_hits 1826928 # ITB hits +system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1966431 # ITB accesses +system.cpu1.itb.fetch_accesses 1827992 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -793,389 +796,387 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5486 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 706502118.118848 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 410575500.110236 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2743 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 98500 # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 24691263500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1937935310000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3925253147 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3931646339 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2743 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78622 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26563 38.35% 38.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40238 58.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69272 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25720 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25216 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53407 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909399868000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 730527500 0.04% 97.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 354535500 0.02% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 52140917500 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962625848500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968264 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626671 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.770975 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 423 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63023 88.06% 91.46% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3777 5.28% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed +system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed +system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71571 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2066 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2880 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 892 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 428 -system.cpu1.kern.mode_switch_good::kernel 0.431752 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73259 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 816 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 449 +system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148611 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329760 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17773252500 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1704242000 0.09% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943148352000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.committedInsts 13179937 # Number of instructions committed -system.cpu1.committedOps 13179937 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12156604 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses -system.cpu1.num_func_calls 411985 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307841 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12156604 # number of integer instructions -system.cpu1.num_fp_insts 173446 # number of float instructions -system.cpu1.num_int_register_reads 16739384 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8921370 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written -system.cpu1.num_mem_refs 4206400 # number of memory refs -system.cpu1.num_load_insts 2436997 # Number of load instructions -system.cpu1.num_store_insts 1769403 # Number of store instructions -system.cpu1.num_idle_cycles 3875870619.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49382527.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012581 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987419 # Percentage of idle cycles -system.cpu1.Branches 1874664 # Number of branches fetched -system.cpu1.op_class::No_OpClass 705658 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7796168 59.14% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 21633 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14181 0.11% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.78% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::MemRead 2508903 19.03% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1770394 13.43% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 364376 2.76% 100.00% # Class of executed instruction +system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2017 # number of times the context was actually changed +system.cpu1.committedInsts 13268743 # Number of instructions committed +system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses +system.cpu1.num_func_calls 423393 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12224543 # number of integer instructions +system.cpu1.num_fp_insts 175144 # number of float instructions +system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written +system.cpu1.num_mem_refs 4214824 # number of memory refs +system.cpu1.num_load_insts 2456352 # Number of load instructions +system.cpu1.num_store_insts 1758472 # Number of store instructions +system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles +system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles +system.cpu1.Branches 1899015 # Number of branches fetched +system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction +system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction +system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::MemRead 2529811 19.06% 84.00% # Class of executed instruction +system.cpu1.op_class::MemWrite 1759476 13.26% 97.25% # Class of executed instruction +system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13183299 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 166569 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.920851 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4014072 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 167081 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.024707 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 79208580000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.920851 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947111 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947111 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16965673 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16965673 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2258295 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2258295 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1642687 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1642687 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48217 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48217 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50804 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50804 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3900982 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3900982 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3900982 # number of overall hits -system.cpu1.dcache.overall_hits::total 3900982 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118473 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118473 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62672 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62672 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8931 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8931 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 181145 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 181145 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 181145 # number of overall misses -system.cpu1.dcache.overall_misses::total 181145 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1450679500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1450679500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1216299000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1216299000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81854000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81854000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 32847500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 32847500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2666978500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2666978500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2666978500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2666978500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2376768 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2376768 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1705359 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1705359 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57148 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57148 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56674 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56674 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4082127 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4082127 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4082127 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4082127 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049846 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049846 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036750 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036750 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156278 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156278 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044375 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044375 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044375 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044375 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12244.811054 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12244.811054 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19407.374904 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19407.374904 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9165.155078 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9165.155078 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5595.826235 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5595.826235 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14722.893262 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14722.893262 # average overall miss latency +system.cpu1.op_class::total 13271624 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 162095 # number of replacements +system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits +system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses +system.cpu1.dcache.overall_misses::total 177419 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 114559 # number of writebacks -system.cpu1.dcache.writebacks::total 114559 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118473 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118473 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62672 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62672 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8931 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8931 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 181145 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 181145 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 181145 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 181145 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1332206500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1332206500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153627000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153627000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72923000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72923000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26977500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26977500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2485833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2485833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2485833500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2485833500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049846 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049846 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036750 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036750 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156278 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156278 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103575 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103575 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044375 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044375 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11244.811054 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11244.811054 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18407.374904 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18407.374904 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8165.155078 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8165.155078 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4595.826235 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4595.826235 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 316020 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.922081 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12866727 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 316532 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.649056 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960698705500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.922081 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870942 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870942 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13499873 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13499873 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12866727 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12866727 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12866727 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12866727 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12866727 # number of overall hits -system.cpu1.icache.overall_hits::total 12866727 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316573 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316573 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316573 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316573 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316573 # number of overall misses -system.cpu1.icache.overall_misses::total 316573 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4250508000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4250508000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4250508000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4250508000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4250508000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4250508000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13183300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13183300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13183300 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13183300 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13183300 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13183300 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024013 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024013 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024013 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024013 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024013 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024013 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13426.628297 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13426.628297 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13426.628297 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13426.628297 # average overall miss latency +system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks +system.cpu1.dcache.writebacks::total 111600 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 326538 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits +system.cpu1.icache.overall_hits::total 12944535 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses +system.cpu1.icache.overall_misses::total 327089 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 316020 # number of writebacks -system.cpu1.icache.writebacks::total 316020 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316573 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316573 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316573 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316573 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316573 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316573 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933935000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933935000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933935000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3933935000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933935000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3933935000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024013 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024013 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024013 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12426.628297 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks +system.cpu1.icache.writebacks::total 326538 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1188,13 +1189,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7375 # Transaction distribution -system.iobus.trans_dist::ReadResp 7375 # Transaction distribution -system.iobus.trans_dist::WriteReq 55610 # Transaction distribution -system.iobus.trans_dist::WriteResp 55610 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 55675 # Transaction distribution +system.iobus.trans_dist::WriteResp 55675 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1202,12 +1203,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1215,74 +1216,74 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743514 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 14952500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 763000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15838000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6057500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216134056 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.568010 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756490226000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568010 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035501 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035501 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22088883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22088883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858687173 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858687173 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4880776056 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4880776056 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4880776056 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4880776056 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1291,38 +1292,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125505.017045 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125505.017045 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116930.284294 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116930.284294 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116966.450729 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116966.450729 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 16 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13288883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13288883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778678942 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778678942 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2791967825 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2791967825 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2791967825 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2791967825 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1331,196 +1332,196 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75505.017045 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75505.017045 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.327253 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.327253 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 341251 # number of replacements -system.l2c.tags.tagsinuse 65397.203087 # Cycle average of tags in use -system.l2c.tags.total_refs 3991452 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406774 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.812456 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7305719000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 281.092347 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4857.550126 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 59344.826381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 110.880269 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 802.853964 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.905530 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012251 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997882 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65523 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6255 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57986 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999802 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35595123 # Number of tag accesses -system.l2c.tags.data_accesses 35595123 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 793736 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 793736 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 747944 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 747944 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2258 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5373 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 912 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 927 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1839 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126843 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 174433 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 686424 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 316124 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1002548 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 663180 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 109254 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 772434 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 686424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790023 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 316124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156844 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949415 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 686424 # number of overall hits -system.l2c.overall_hits::cpu0.data 790023 # number of overall hits -system.l2c.overall_hits::cpu1.inst 316124 # number of overall hits -system.l2c.overall_hits::cpu1.data 156844 # number of overall hits -system.l2c.overall_hits::total 1949415 # number of overall hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 342937 # number of replacements +system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use +system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35591920 # Number of tag accesses +system.l2c.tags.data_accesses 35591920 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 792871 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792871 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44916.666667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67128.746754 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72597.285782 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67414.036388 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71711.025908 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63242.401431 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 69739.316239 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63247.992806 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209503.516174 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209561.189054 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82998.272692 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70971.021311 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 851905 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 404237 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 411 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292704 # Transaction distribution -system.membus.trans_dist::WriteReq 14058 # Transaction distribution -system.membus.trans_dist::WriteResp 14058 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120323 # Transaction distribution -system.membus.trans_dist::CleanEvict 261806 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11056 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9461 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 7198 # Transaction distribution +system.membus.trans_dist::ReadResp 292654 # Transaction distribution +system.membus.trans_dist::WriteReq 14123 # Transaction distribution +system.membus.trans_dist::WriteResp 14123 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution +system.membus.trans_dist::CleanEvict 262335 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 122183 # Transaction distribution -system.membus.trans_dist::ReadExResp 121347 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285505 # Transaction distribution +system.membus.trans_dist::ReadExReq 123969 # Transaction distribution +system.membus.trans_dist::ReadExResp 123101 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1174875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1217389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1300828 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31053824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31135706 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33793946 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21651 # Total snoops (count) -system.membus.snoopTraffic 27136 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 491014 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001340 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036583 # Request fanout histogram +system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22774 # Total snoops (count) +system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 493929 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 490356 99.87% 99.87% # Request fanout histogram -system.membus.snoop_fanout::1 658 0.13% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 491014 # Request fanout histogram -system.membus.reqLayer0.occupancy 40347000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 493929 # Request fanout histogram +system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314918038 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2173304250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 904117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4781747 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2390985 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 355114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 992 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 932 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102308 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872539 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1014847 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815207 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16306 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11300 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27606 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297851 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297851 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1016013 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079098 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 229 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2097686 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605272 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535742 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7187865 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89487744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118850496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40485888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17815770 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266639898 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 398766 # Total snoops (count) -system.toL2Bus.snoopTraffic 7394432 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2783305 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.138476 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345638 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 403246 # Total snoops (count) +system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2398113 86.16% 86.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 384964 13.83% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 227 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2783305 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4217117493 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1049361097 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1811830165 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 476124465 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 281628843 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1788,28 +1789,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index b603b455c..fff26b301 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 38 cycles, load miss latency 162 cycles +
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 |