diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1538 |
1 files changed, 727 insertions, 811 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 1efa023f6..5b0dc7b99 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920428 # Number of seconds simulated -sim_ticks 1920428041000 # Number of ticks simulated -final_tick 1920428041000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920416 # Number of seconds simulated +sim_ticks 1920416181000 # Number of ticks simulated +final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1405906 # Simulator instruction rate (inst/s) -host_op_rate 1405905 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48056353161 # Simulator tick rate (ticks/s) -host_mem_usage 307800 # Number of bytes of host memory used -host_seconds 39.96 # Real time elapsed on the host -sim_insts 56182750 # Number of instructions simulated -sim_ops 56182750 # Number of ops (including micro ops) simulated +host_inst_rate 1752736 # Simulator instruction rate (inst/s) +host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59896862792 # Simulator tick rate (ticks/s) +host_mem_usage 308520 # Number of bytes of host memory used +host_seconds 32.06 # Real time elapsed on the host +sim_insts 56196255 # Number of instructions simulated +sim_ops 56196255 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24846912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28349952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7389824 # Number of bytes written to this memory -system.physmem.bytes_written::total 7389824 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13292 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388233 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory +system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442968 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115466 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115466 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12938216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1381125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14762309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442968 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3848009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3848009 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3848009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12938216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1381125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18610318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442968 # Number of read requests accepted -system.physmem.writeReqs 115466 # Number of write requests accepted -system.physmem.readBursts 442968 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115466 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28346688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue -system.physmem.bytesWritten 7389440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28349952 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7389824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443177 # Number of read requests accepted +system.physmem.writeReqs 115717 # Number of write requests accepted +system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue +system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27966 # Per bank write bursts -system.physmem.perBankRdBursts::1 28089 # Per bank write bursts -system.physmem.perBankRdBursts::2 28297 # Per bank write bursts -system.physmem.perBankRdBursts::3 28053 # Per bank write bursts -system.physmem.perBankRdBursts::4 27407 # Per bank write bursts -system.physmem.perBankRdBursts::5 27545 # Per bank write bursts -system.physmem.perBankRdBursts::6 26911 # Per bank write bursts -system.physmem.perBankRdBursts::7 26762 # Per bank write bursts -system.physmem.perBankRdBursts::8 27807 # Per bank write bursts -system.physmem.perBankRdBursts::9 27255 # Per bank write bursts -system.physmem.perBankRdBursts::10 27714 # Per bank write bursts -system.physmem.perBankRdBursts::11 27327 # Per bank write bursts -system.physmem.perBankRdBursts::12 27431 # Per bank write bursts -system.physmem.perBankRdBursts::13 28073 # Per bank write bursts -system.physmem.perBankRdBursts::14 28024 # Per bank write bursts -system.physmem.perBankRdBursts::15 28256 # Per bank write bursts -system.physmem.perBankWrBursts::0 7722 # Per bank write bursts -system.physmem.perBankWrBursts::1 7593 # Per bank write bursts -system.physmem.perBankWrBursts::2 7833 # Per bank write bursts -system.physmem.perBankWrBursts::3 7543 # Per bank write bursts -system.physmem.perBankWrBursts::4 7010 # Per bank write bursts -system.physmem.perBankWrBursts::5 6982 # Per bank write bursts -system.physmem.perBankWrBursts::6 6469 # Per bank write bursts -system.physmem.perBankWrBursts::7 6223 # Per bank write bursts -system.physmem.perBankWrBursts::8 7224 # Per bank write bursts -system.physmem.perBankWrBursts::9 6661 # Per bank write bursts -system.physmem.perBankWrBursts::10 7099 # Per bank write bursts -system.physmem.perBankWrBursts::11 6780 # Per bank write bursts -system.physmem.perBankWrBursts::12 7009 # Per bank write bursts -system.physmem.perBankWrBursts::13 7722 # Per bank write bursts -system.physmem.perBankWrBursts::14 7773 # Per bank write bursts -system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.perBankRdBursts::0 27851 # Per bank write bursts +system.physmem.perBankRdBursts::1 28132 # Per bank write bursts +system.physmem.perBankRdBursts::2 28319 # Per bank write bursts +system.physmem.perBankRdBursts::3 28010 # Per bank write bursts +system.physmem.perBankRdBursts::4 27531 # Per bank write bursts +system.physmem.perBankRdBursts::5 27552 # Per bank write bursts +system.physmem.perBankRdBursts::6 26732 # Per bank write bursts +system.physmem.perBankRdBursts::7 26855 # Per bank write bursts +system.physmem.perBankRdBursts::8 27890 # Per bank write bursts +system.physmem.perBankRdBursts::9 27110 # Per bank write bursts +system.physmem.perBankRdBursts::10 27744 # Per bank write bursts +system.physmem.perBankRdBursts::11 27465 # Per bank write bursts +system.physmem.perBankRdBursts::12 27482 # Per bank write bursts +system.physmem.perBankRdBursts::13 28199 # Per bank write bursts +system.physmem.perBankRdBursts::14 28116 # Per bank write bursts +system.physmem.perBankRdBursts::15 28068 # Per bank write bursts +system.physmem.perBankWrBursts::0 7630 # Per bank write bursts +system.physmem.perBankWrBursts::1 7636 # Per bank write bursts +system.physmem.perBankWrBursts::2 7854 # Per bank write bursts +system.physmem.perBankWrBursts::3 7535 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 6994 # Per bank write bursts +system.physmem.perBankWrBursts::6 6317 # Per bank write bursts +system.physmem.perBankWrBursts::7 6319 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts +system.physmem.perBankWrBursts::9 6529 # Per bank write bursts +system.physmem.perBankWrBursts::10 7110 # Per bank write bursts +system.physmem.perBankWrBursts::11 6915 # Per bank write bursts +system.physmem.perBankWrBursts::12 7060 # Per bank write bursts +system.physmem.perBankWrBursts::13 7819 # Per bank write bursts +system.physmem.perBankWrBursts::14 7860 # Per bank write bursts +system.physmem.perBankWrBursts::15 7680 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1920416169000 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1920404309000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 442968 # Read request sizes (log2) +system.physmem.readPktSize::6 443177 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115466 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 403787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 10503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2702 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1247 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115717 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -133,289 +133,205 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 22 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 46254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 772.575777 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.901205 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1785.674907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 16351 35.35% 35.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 6669 14.42% 49.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 4598 9.94% 59.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2705 5.85% 65.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1760 3.81% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1480 3.20% 72.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1070 2.31% 74.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 848 1.83% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 733 1.58% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 614 1.33% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 629 1.36% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 417 0.90% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 327 0.71% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 305 0.66% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 281 0.61% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 335 0.72% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 208 0.45% 85.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 173 0.37% 85.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 157 0.34% 85.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 138 0.30% 86.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 163 0.35% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 903 1.95% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 167 0.36% 88.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 98 0.21% 88.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 103 0.22% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 86 0.19% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 86 0.19% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 55 0.12% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 76 0.16% 89.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 70 0.15% 89.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 69 0.15% 90.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 49 0.11% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 76 0.16% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 62 0.13% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 63 0.14% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 35 0.08% 90.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 62 0.13% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 58 0.13% 90.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 65 0.14% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 35 0.08% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 74 0.16% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 59 0.13% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 59 0.13% 91.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 26 0.06% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 59 0.13% 91.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 60 0.13% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 63 0.14% 92.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 34 0.07% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 64 0.14% 92.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 58 0.13% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 54 0.12% 92.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 33 0.07% 92.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 54 0.12% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 58 0.13% 92.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 64 0.14% 92.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 34 0.07% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 65 0.14% 93.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 57 0.12% 93.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 56 0.12% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 28 0.06% 93.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 54 0.12% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 53 0.11% 93.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 65 0.14% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 31 0.07% 93.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 67 0.14% 94.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 53 0.11% 94.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 55 0.12% 94.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 27 0.06% 94.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 54 0.12% 94.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 56 0.12% 94.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 66 0.14% 94.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 372 0.80% 95.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 49 0.11% 95.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4739 28 0.06% 95.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 48 0.10% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 28 0.06% 95.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 51 0.11% 95.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 28 0.06% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 52 0.11% 96.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 28 0.06% 96.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 51 0.11% 96.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 40 0.09% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 53 0.11% 96.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 25 0.05% 96.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 51 0.11% 96.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 26 0.06% 96.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 51 0.11% 96.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5635 24 0.05% 96.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 50 0.11% 97.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5763 28 0.06% 97.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 50 0.11% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 26 0.06% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 50 0.11% 97.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 27 0.06% 97.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 51 0.11% 97.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 28 0.06% 97.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 50 0.11% 97.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 26 0.06% 97.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 49 0.11% 97.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 26 0.06% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 52 0.11% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6531 25 0.05% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 52 0.11% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6659 25 0.05% 98.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 52 0.11% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 425 0.92% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 13 0.03% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 4 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 2 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8963 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11587 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13187 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 3 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14851 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 35 0.08% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 180 0.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 46254 # Bytes accessed per row activation -system.physmem.totQLat 6257775000 # Total ticks spent queuing -system.physmem.totMemAccLat 14505282500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2214585000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6032922500 # Total ticks spent accessing banks -system.physmem.avgQLat 14128.55 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13620.89 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads +system.physmem.totQLat 7790286250 # Total ticks spent queuing +system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks +system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32749.44 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 14.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.76 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.25 # Average write queue length when enqueuing -system.physmem.readRowHits 419360 # Number of row buffer hits during reads -system.physmem.writeRowHits 92763 # Number of row buffer hits during writes -system.physmem.readRowHitRate 94.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.34 # Row buffer hit rate for writes -system.physmem.avgGap 3438931.31 # Average gap between requests -system.physmem.pageHitRate 91.72 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.52 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18651952 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292310 # Transaction distribution -system.membus.trans_dist::ReadResp 292310 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing +system.physmem.readRowHits 398457 # Number of row buffer hits during reads +system.physmem.writeRowHits 94179 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes +system.physmem.avgGap 3436079.67 # Average gap between requests +system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 18667397 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292363 # Transaction distribution +system.membus.trans_dist::ReadResp 292363 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115466 # Transaction distribution +system.membus.trans_dist::Writeback 115717 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158141 # Transaction distribution -system.membus.trans_dist::ReadExResp 158141 # Transaction distribution +system.membus.trans_dist::ReadExReq 158297 # Transaction distribution +system.membus.trans_dist::ReadExResp 158297 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 877537 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1035377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30430656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475220 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35784340 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35784340 # Total data (bytes) +system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35813780 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1489694250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3746415596 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376299750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352288 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753529489000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352288 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -429,14 +345,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134383 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 12989922573 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12989922573 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13011056956 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13011056956 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13011056956 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13011056956 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles +system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -453,19 +369,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122164.063584 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122164.063584 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312618.467775 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 312618.467775 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 311828.806615 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 311828.806615 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 311828.806615 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 403484 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 29141 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.845922 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -479,14 +395,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137383 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10827670073 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10827670073 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10839807456 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10839807456 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10839807456 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10839807456 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -495,14 +411,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70158.283237 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70158.283237 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260581.201218 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 260581.201218 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259791.670605 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 259791.670605 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -521,22 +437,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064966 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9066711 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6356267 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6357503 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15421233 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15424214 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973920 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974520 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978917 # ITB accesses +system.cpu.itb.fetch_accesses 4979530 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -549,52 +465,52 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840856082 # number of cpu cycles simulated +system.cpu.numCycles 3840832362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56182750 # Number of instructions committed -system.cpu.committedOps 56182750 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054772 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses -system.cpu.num_func_calls 1483342 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468084 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054772 # number of integer instructions -system.cpu.num_fp_insts 324326 # number of float instructions -system.cpu.num_int_register_reads 71321847 # number of times the integer registers were read -system.cpu.num_int_register_writes 38521555 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written -system.cpu.num_mem_refs 15473812 # number of memory refs -system.cpu.num_load_insts 9101789 # Number of load instructions -system.cpu.num_store_insts 6372023 # Number of store instructions -system.cpu.num_idle_cycles 3588896828.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251959253.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065600 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934400 # Percentage of idle cycles -system.cpu.Branches 8421946 # Number of branches fetched +system.cpu.committedInsts 56196255 # Number of instructions committed +system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1483738 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls +system.cpu.num_int_insts 52067788 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read +system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15476821 # number of memory refs +system.cpu.num_load_insts 9103557 # Number of load instructions +system.cpu.num_store_insts 6373264 # Number of store instructions +system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934436 # Percentage of idle cycles +system.cpu.Branches 8424076 # Number of branches fetched system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211963 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106216 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183174 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858257404500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91623500 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737068500 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61341210500 3.19% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920427307000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692250 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814084 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -630,10 +546,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175953 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -642,21 +558,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192898 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches -system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.callpal::total 192909 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1739 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323225 # fraction of useful protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391907 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46222890000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5212630500 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868991784500 97.32% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4176 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -688,7 +604,7 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409150 # Throughput (bytes/s) +system.iobus.throughput 1409159 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution system.iobus.trans_dist::WriteReq 51202 # Transaction distribution @@ -748,67 +664,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 377727206 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42674250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928358 # number of replacements -system.cpu.icache.tags.tagsinuse 508.321671 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55265541 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928869 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.497670 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39723654250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.321671 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992816 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992816 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928494 # number of replacements +system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57123599 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57123599 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55265541 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55265541 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55265541 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55265541 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55265541 # number of overall hits -system.cpu.icache.overall_hits::total 55265541 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929029 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929029 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929029 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929029 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929029 # number of overall misses -system.cpu.icache.overall_misses::total 929029 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12961853258 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12961853258 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12961853258 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12961853258 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12961853258 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12961853258 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194570 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194570 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194570 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194570 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194570 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194570 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13952.043755 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13952.043755 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13952.043755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13952.043755 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13952.043755 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55278924 # number of overall hits +system.cpu.icache.overall_hits::total 55278924 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929165 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929165 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929165 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929165 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929165 # number of overall misses +system.cpu.icache.overall_misses::total 929165 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12919006759 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12919006759 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12919006759 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12919006759 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12919006759 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12919006759 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56208089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56208089 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56208089 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56208089 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56208089 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56208089 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016531 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016531 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016531 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016531 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016531 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016531 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13903.888716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13903.888716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -817,135 +733,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929029 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929029 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929029 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929029 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929029 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929029 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11098555742 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11098555742 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11098555742 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11098555742 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21665599142 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334146000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895641500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895641500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250214 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141490 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141506 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014308 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279367 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60282.085233 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53658.965934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53877.906173 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1021,13 +937,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391286 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099982 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107796250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978892 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1035,72 +951,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63152102 # 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number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17233 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374071 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374071 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374071 # number of overall misses +system.cpu.dcache.overall_misses::total 1374071 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29019471009 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29019471009 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10854033885 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10854033885 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228736500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228736500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39873504894 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39873504894 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39873504894 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39873504894 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885833 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157920 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200260 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200260 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043753 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043753 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043753 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043753 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120361 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120361 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049459 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086053 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086053 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091338 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091338 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091338 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091338 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27133.451901 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27133.451901 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35638.175101 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35638.175101 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13273.167760 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13273.167760 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29018.518617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29018.518617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29018.518617 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1109,54 +1025,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835114 # number of writebacks -system.cpu.dcache.writebacks::total 835114 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069470 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069470 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304370 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304370 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17259 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17259 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373840 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373840 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373840 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373840 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26604805241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26604805241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10372104863 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10372104863 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194393750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194393750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36976910104 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36976910104 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36976910104 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36976910104 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011442000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011442000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks +system.cpu.dcache.writebacks::total 835359 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374071 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374071 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374071 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26755042991 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26755042991 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10192844115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10192844115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194257500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194257500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36947887106 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36947887106 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36947887106 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36947887106 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011441500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011441500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120380 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049437 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049437 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086189 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086189 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091341 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091341 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091341 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24876.626031 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24876.626031 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34077.290347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34077.290347 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11263.326380 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11263.326380 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26915.004734 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26915.004734 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1164,31 +1080,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105179195 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2022861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022844 # Transaction distribution +system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835114 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 345905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304355 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3650630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5508668 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59456576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142531220 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201987796 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201977684 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2425850000 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1396163258 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2191612646 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |