all: Update stats for memory per master and total fix.

1 files changed, 108 insertions, 16 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index d0852c317..42fcfede1 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,23 +4,40 @@ sim_seconds                                  1.915549                       # Nu
 sim_ticks                                1915548867000                       # Number of ticks simulated
 final_tick                               1915548867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 646342                       # Simulator instruction rate (inst/s)
-host_op_rate                                   646342                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            22054916762                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292620                       # Number of bytes of host memory used
-host_seconds                                    86.85                       # Real time elapsed on the host
+host_inst_rate                                1238015                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1238014                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            42244373047                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292960                       # Number of bytes of host memory used
+host_seconds                                    45.34                       # Real time elapsed on the host
 sim_insts                                    56137087                       # Number of instructions simulated
 sim_ops                                      56137087                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read                    29663360                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                 943040                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10122368                       # Number of bytes written to this memory
-system.physmem.num_reads                       463490                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      158162                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       15485567                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    492308                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       5284317                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      20769884                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst            943040                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          26067904                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2652416                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             29663360                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       943040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          943040                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     10122368                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          10122368                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              14735                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             407311                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41444                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                463490                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          158162                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               158162                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               492308                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13608582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1384677                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15485567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          492308                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             492308                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           5284317                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5284317                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           5284317                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              492308                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13608582                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1384677                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               20769884                       # Total bandwidth to/from this memory (bytes/s)
 system.l2c.replacements                        389289                       # number of replacements
 system.l2c.tagsinuse                     34352.038344                       # Cycle average of tags in use
 system.l2c.total_refs                         2311163                       # Total number of references to valid blocks.
@@ -92,20 +109,30 @@ system.l2c.overall_accesses::cpu.data         1390437                       # nu
 system.l2c.overall_accesses::total            2318771                       # number of overall (read+write) accesses
 system.l2c.ReadReq_miss_rate::cpu.inst       0.015873                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu.data       0.266420                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.150967                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.538462                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.538462                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu.data     0.388905                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.388905                       # miss rate for ReadExReq accesses
 system.l2c.demand_miss_rate::cpu.inst        0.015873                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu.data        0.293215                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.182179                       # miss rate for demand accesses
 system.l2c.overall_miss_rate::cpu.inst       0.015873                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu.data       0.293215                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.182179                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52016.540189                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 35428.571429                       # average UpgradeReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52003.930884                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.data 52013.377582                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52013.009194                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.data 52013.377582                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52013.009194                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -150,23 +177,36 @@ system.l2c.overall_mshr_uncacheable_latency::cpu.data   1856492500
 system.l2c.overall_mshr_uncacheable_latency::total   1856492500                       # number of overall MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.266420                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.150967                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.538462                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.538462                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.388905                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.388905                       # mshr miss rate for ReadExReq accesses
 system.l2c.demand_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu.data     0.293215                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.182179                       # mshr miss rate for demand accesses
 system.l2c.overall_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu.data     0.293215                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.182179                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.522105                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45714.285714                       # average UpgradeReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.930884                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40012.996175                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40012.996175                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.tagsinuse                     1.340325                       # Cycle average of tags in use
@@ -202,13 +242,21 @@ system.iocache.demand_accesses::total           41725                       # nu
 system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
 system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 115265.884393                       # average ReadReq miss latency
 system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 137714.208847                       # average WriteReq miss latency
 system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 137621.133709                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 137621.133709                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      64604060                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
@@ -236,13 +284,21 @@ system.iocache.demand_mshr_miss_latency::total   3572392988
 system.iocache.overall_mshr_miss_latency::tsunami.ide   3572392988                       # number of overall MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::total   3572392988                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
 system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 63265.884393                       # average ReadReq mshr miss latency
 system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 85710.627407                       # average WriteReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 85617.567118                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 85617.567118                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -332,6 +388,7 @@ system.cpu.kern.ipl_used::0                  0.981746                       # fr
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::31                 0.692298                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.814116                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -389,7 +446,7 @@ system.cpu.kern.mode_good::idle                   168
 system.cpu.kern.mode_switch_good::kernel     0.322887                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::idle       0.080306                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      1.403193                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.391657                       # fraction of useful protection mode switches
 system.cpu.kern.mode_ticks::kernel        45253274000      2.36%      2.36% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::user           5124228000      0.27%      2.63% # number of ticks spent at the given mode
 system.cpu.kern.mode_ticks::idle         1865170605000     97.37%    100.00% # number of ticks spent at the given mode
@@ -459,11 +516,17 @@ system.cpu.icache.demand_accesses::total     56148907                       # nu
 system.cpu.icache.overall_accesses::cpu.inst     56148907                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     56148907                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016534                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016534                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.016534                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016534                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.016534                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016534                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14667.218001                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14667.218001                       # average overall miss latency
 system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14667.218001                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -487,11 +550,17 @@ system.cpu.icache.demand_mshr_miss_latency::total  10830625500
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10830625500                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total  10830625500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016534                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016534                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016534                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11666.482290                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11666.482290                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11666.482290                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1390115                       # number of replacements
 system.cpu.dcache.tagsinuse                511.984023                       # Cycle average of tags in use
@@ -547,15 +616,25 @@ system.cpu.dcache.demand_accesses::total     15029535                       # nu
 system.cpu.dcache.overall_accesses::cpu.data     15029535                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15029535                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120441                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.120441                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049462                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049462                       # miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085908                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.085908                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.091383                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091383                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.091383                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091383                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25368.690313                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30323.439631                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14300.331376                       # average LoadLockedReq miss latency
 system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26466.589124                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26466.589124                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -593,18 +672,31 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1199607500
 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2062370500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total   2062370500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120441                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120441                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049462                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049462                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085908                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085908                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091383                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091383                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22368.647754                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27323.439631                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11300.331376                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23466.555996                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23466.555996                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------