diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 684 |
1 files changed, 343 insertions, 341 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 37d46853e..9ceba3cc3 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1512910 # Simulator instruction rate (inst/s) -host_op_rate 1512909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52275426747 # Simulator tick rate (ticks/s) -host_mem_usage 372644 # Number of bytes of host memory used -host_seconds 37.14 # Real time elapsed on the host +host_inst_rate 780683 # Simulator instruction rate (inst/s) +host_op_rate 780683 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26974878622 # Simulator tick rate (ticks/s) +host_mem_usage 326192 # Number of bytes of host memory used +host_seconds 71.97 # Real time elapsed on the host sim_insts 56182685 # Number of instructions simulated sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -149,85 +149,85 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5708 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 172 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 104 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 179 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 64912 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 509.974858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.431433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.117715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15298 23.57% 23.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.437414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.111966 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15297 23.57% 23.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 11509 17.73% 41.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4967 7.65% 48.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4968 7.65% 48.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3096 4.77% 53.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2467 3.80% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4201 6.47% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2466 3.80% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4203 6.47% 63.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1427 2.20% 66.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2061 3.18% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2060 3.17% 69.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 19886 30.64% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 64912 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5093 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.826036 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2956.913485 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5090 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::samples 5094 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.810561 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2956.623385 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5091 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5093 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5093 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.729433 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.333640 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.082746 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4499 88.34% 88.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.57% 88.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 20 0.39% 89.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 41 0.81% 90.10% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5094 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5094 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.724971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.335038 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.028996 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4499 88.32% 88.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.57% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 21 0.41% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 41 0.80% 90.11% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-55 209 4.10% 94.21% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-63 11 0.22% 94.42% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-71 11 0.22% 94.64% # Writes before turning the bus around for reads @@ -241,20 +241,20 @@ system.physmem.wrPerTurnAround::128-135 8 0.16% 99.31% # Wr system.physmem.wrPerTurnAround::136-143 5 0.10% 99.41% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-167 4 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.10% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.10% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 7 0.14% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.12% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 6 0.12% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-247 1 0.02% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::256-263 4 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5093 # Writes before turning the bus around for reads -system.physmem.totQLat 2720413750 # Total ticks spent queuing -system.physmem.totMemAccLat 10248182500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.wrPerTurnAround::total 5094 # Writes before turning the bus around for reads +system.physmem.totQLat 2720435750 # Total ticks spent queuing +system.physmem.totMemAccLat 10248204500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6775.95 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6776.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25525.95 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25526.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -276,28 +276,28 @@ system.physmem_0.preEnergy 131096625 # En system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71567841690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1101986721000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302659881995 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.032847 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1832974788000 # Time in different power states +system.physmem_0.actBackEnergy 71567881875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101986685750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302659886930 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.032849 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832974732500 # Time in different power states system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43477648250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43477703750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 250470360 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 136665375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72629101890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.109728 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states +system.physmem_1.actBackEnergy 72629135235 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101055761750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302809133000 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109730 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831423337250 # Time in different power states system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45029099000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states system.bridge.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states @@ -336,15 +336,15 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.numPwrStateTransitions 12750 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281084846.274667 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439246514.470007 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281084850.117804 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439246512.061173 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 6374 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 6375 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 149360100999 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1791915895001 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::ON 149360076499 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1791915919501 # Cumulative time (in ticks) in various power states system.cpu.numCycles 3882551992 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -361,10 +361,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860509936500 95.84% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94066500 0.00% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1860509959000 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94068000 0.00% 95.84% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 770529000 0.04% 95.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79900730000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79900706000 4.12% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -429,9 +429,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323121 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48613441500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5603081000 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887058737500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 48613391500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5603093000 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887058775500 97.21% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.committedInsts 56182685 # Number of instructions committed system.cpu.committedOps 56182685 # Number of ops (including micro ops) committed @@ -448,8 +448,8 @@ system.cpu.num_fp_register_writes 166486 # nu system.cpu.num_mem_refs 15473452 # number of memory refs system.cpu.num_load_insts 9101488 # Number of load instructions system.cpu.num_store_insts 6371964 # Number of store instructions -system.cpu.num_idle_cycles 3583831790.000154 # Number of idle cycles -system.cpu.num_busy_cycles 298720201.999846 # Number of busy cycles +system.cpu.num_idle_cycles 3583831839.000154 # Number of idle cycles +system.cpu.num_busy_cycles 298720152.999846 # Number of busy cycles system.cpu.not_idle_fraction 0.076939 # Percentage of non-idle cycles system.cpu.idle_fraction 0.923061 # Percentage of idle cycles system.cpu.Branches 8422715 # Number of branches fetched @@ -489,11 +489,11 @@ system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 56194518 # Class of executed instruction system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390402 # number of replacements +system.cpu.dcache.tags.replacements 1390398 # number of replacements system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14048965 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390910 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.100556 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy @@ -503,41 +503,41 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 63150415 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63150415 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7814386 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814386 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852266 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852266 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666648 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666648 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666648 # number of overall hits -system.cpu.dcache.overall_hits::total 13666648 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069359 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069359 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304327 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304327 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 13666652 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666652 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666652 # number of overall hits +system.cpu.dcache.overall_hits::total 13666652 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069356 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069356 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304326 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304326 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17246 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17246 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373686 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373686 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373686 # number of overall misses -system.cpu.dcache.overall_misses::total 1373686 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772641000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44772641000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635172000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17635172000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1373682 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373682 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373682 # number of overall misses +system.cpu.dcache.overall_misses::total 1373682 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772600000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44772600000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635207000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17635207000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232797500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 232797500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62407813000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62407813000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62407813000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62407813000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62407807000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62407807000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62407807000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62407807000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8883742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8883742 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6156592 # number of WriteReq accesses(hits+misses) @@ -550,8 +550,8 @@ system.cpu.dcache.demand_accesses::cpu.data 15040334 # system.cpu.dcache.demand_accesses::total 15040334 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15040334 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15040334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120373 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120373 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120372 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120372 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086109 # miss rate for LoadLockedReq accesses @@ -560,56 +560,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.671793 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.671793 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.101877 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.101877 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.750912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.750912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.407300 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.407300 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45430.915799 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45430.915799 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45431.043720 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45431.043720 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45431.043720 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45431.043720 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks -system.cpu.dcache.writebacks::total 834944 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069359 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304327 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304327 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 834943 # number of writebacks +system.cpu.dcache.writebacks::total 834943 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069356 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069356 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304326 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304326 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373686 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373686 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373686 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373686 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373682 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373682 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373682 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373682 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43703282000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43703282000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330845000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43703244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43703244000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330881000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330881000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034127000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61034127000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526978500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526978500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034125000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61034125000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034125000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61034125000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526980000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526980000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1526980000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 1526980000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120372 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120372 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses @@ -618,20 +618,20 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.671793 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.671793 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.101877 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.101877 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.750912 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.750912 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.407300 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.407300 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92080.956401 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92080.956401 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44431.043720 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44431.043720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44431.043720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44431.043720 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.434343 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.434343 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92081.046855 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92081.046855 # average overall mshr uncacheable latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 928931 # number of replacements system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use @@ -663,12 +663,12 @@ system.cpu.icache.demand_misses::cpu.inst 929602 # n system.cpu.icache.demand_misses::total 929602 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 929602 # number of overall misses system.cpu.icache.overall_misses::total 929602 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686117000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13686117000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13686117000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13686117000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13686117000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13686117000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686093000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13686093000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13686093000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13686093000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13686093000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13686093000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56194519 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56194519 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56194519 # number of demand (read+write) accesses @@ -681,12 +681,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.555459 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14722.555459 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14722.555459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14722.555459 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.529642 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14722.529642 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.529642 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14722.529642 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.529642 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14722.529642 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -701,32 +701,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 929602 system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756515000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12756515000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756515000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12756515000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756515000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12756515000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756491000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12756491000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756491000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12756491000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756491000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12756491000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.529642 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.529642 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.529642 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.529642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.529642 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.529642 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 336393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65234.359958 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3930396 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.787932 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.787915 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820493 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 55072.820449 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.121272 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418237 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy @@ -740,27 +740,27 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 37812907 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37812907 # Number of data accesses system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 834943 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 834943 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187490 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187489 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187489 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916382 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 916382 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814634 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 814634 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814631 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 814631 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 916382 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002124 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918506 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1002120 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918502 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 916382 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002124 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918506 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1002120 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918502 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses @@ -777,64 +777,64 @@ system.cpu.l2cache.overall_misses::cpu.data 388791 # system.cpu.l2cache.overall_misses::total 401991 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 315000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 315000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14901349500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14901349500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1726796000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1726796000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33721236500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33721236500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1726796000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48622586000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50349382000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1726796000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48622586000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50349382000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 834944 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 834944 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14901397500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14901397500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1726772000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1726772000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33721234500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33721234500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1726772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48622632000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50349404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1726772000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48622632000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50349404000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 834943 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 834943 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 928709 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 928709 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304310 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304310 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304309 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304309 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929582 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 929582 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086605 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1086605 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086602 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1086602 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 929582 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390915 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320497 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390911 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320493 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 929582 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320497 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390911 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320493 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383886 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383886 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250294 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250294 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250295 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250295 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279522 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279523 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.173235 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279522 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279523 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.173235 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.204931 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.204931 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130817.878788 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130817.878788 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.353538 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.353538 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125250.023010 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.615819 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.615819 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130816.060606 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130816.060606 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.346184 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.346184 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130816.060606 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125061.104810 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125250.077738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130816.060606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125061.104810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125250.077738 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -865,100 +865,101 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 893500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 893500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13733149500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13733149500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594796000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594796000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31001526500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31001526500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594796000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734676000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46329472000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594796000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440322500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440322500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13733197500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13733197500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594772000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594772000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31001524500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31001524500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594772000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734722000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46329494000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594772000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734722000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46329494000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440324000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440324000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1440324000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1440324000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383886 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383886 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250294 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250294 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250295 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250295 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279523 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.173235 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279523 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.173235 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.204931 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.204931 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120817.878788 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120817.878788 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.353538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.353538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.363927 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.363927 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.615819 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.615819 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120816.060606 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120816.060606 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.346184 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.346184 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120816.060606 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115061.104810 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.077738 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120816.060606 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115061.104810 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.077738 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.961039 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.961039 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86855.454381 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 86855.454381 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4639859 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319495 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023291 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 950744 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817740 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304310 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304309 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304309 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 929602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086778 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086775 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2788115 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6993704 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6993692 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118944832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509612 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261454444 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509292 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261454124 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 419988 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2756928 # Request fanout histogram +system.cpu.toL2Bus.snoopTraffic 7422592 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2756924 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.031847 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2754129 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2754125 99.90% 99.90% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2799 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2756928 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4096926500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2756924 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4096921500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1394403000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098137500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098131500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1003,7 +1004,7 @@ system.iobus.pkt_size_system.bridge.master::total 44588 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5340500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5341000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 759000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1053,12 +1054,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5266456167 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5266456167 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5266456167 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5266456167 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244723284 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5244723284 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5266466167 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5266466167 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5266466167 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5266466167 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1077,12 +1078,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126218.242469 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126218.242469 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126218.242469 # average overall miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.718233 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126220.718233 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126218.482133 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126218.482133 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126218.482133 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126218.482133 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1101,12 +1102,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725 system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3178407867 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3178407867 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3178407867 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3178407867 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165324984 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165324984 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3178417867 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3178417867 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3178417867 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3178417867 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1117,12 +1118,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.143607 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76175.143607 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.439931 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.439931 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76175.383271 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76175.383271 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76175.383271 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76175.383271 # average overall mshr miss latency system.membus.pwrStateResidencyTicks::UNDEFINED 1941275996000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 292274 # Transaction distribution @@ -1149,6 +1150,7 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) +system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 837673 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram @@ -1160,9 +1162,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 837673 # Request fanout histogram -system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 30123000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287200717 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |